An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. The dither circuit utilizes a long sequence pseudo-random number generator to drive a dither DAC whose output is summed with the output of the sample and hold amplifier. This randomizes the location of the input signal on the ADC’s transfer function. This dithered signal is then propagated through the ADC pipeline stages. The random number fed to the dither DAC is subtracted from the ADC result just before the digital output word is transmitted. Dithering the signal in this manner ensures the ADC will not always use the same set of output codes and will randomize the location on the transfer curve such that the signal may avoid always operating on a non-linear region. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off.