The LTC2274 maintains high 16-bit performance of 77.5dB SNR (signal-to-noise ratio) and industry-leading 100dB SFDR (spurious-free dynamic range) at baseband while communicating data via a high-speed 2-wire interface. A PGA front end provides selection between two input ranges to maximize dynamic range performance. Serial test patterns are available to facilitate testing of the serial interface and verify bit error rate (BER). This feature is invaluable for debugging the interface, but is not required by the JEDEC specification. The JESD204 specification outlines an optional scrambler which scrambles the data before it is encoded for transmission. This helps to avoid unwanted spectral peaks that can occur with high-speed serial transmission. By scrambling the data, the octets that are encoded are data-independent, which will eliminate spectral artifacts that can occur with certain data-dependent signals. In addition to the data scrambler, the LTC2274 also offers internal transparent dither to improve SFDR performance for low-level signals. This feature is only offered inside Analog Devices' family of 16-bit high-performance ADCs and will be discussed in more detail in the next set of slides. The JESD204 serial interface offered on the LTC2274 is compatible with many high-speed SerDes interfaces. Reference designs utilizing the LTC2274 are already available from each of the FPGA manufacturers listed. The 16-bit 80Msps LTC2273 and 65Msps LTC2272 are pin-compatible versions of the LTC2274 and are all offered in space-saving 6mm x 6mm QFN packages.