JESD204 provides benefits over conventional serial transmission by using a running disparity to eliminate DC imbalance in the signal. By removing any DC offset, the signal can be transmitted through high pass elements, such as transformers or optical receivers. The unique features of 8B/10B encoding allow the data clock to be embedded in the data itself, and the framing to be maintained with COMMA characters through initial frame synchronization. The new serial interface allows data converters implementing JESD204 to interface with the dedicated SerDes ports on FPGAs rather than consuming general purpose I/O. Routing just two wires across to an FPGA eases layout concerns and consumes less board real estate than a conventional parallel interface, a significant benefit for multi-channel applications. Routing a single differential pair enables easy isolation of sensitive analog circuitry from the noisy digital logic, which helps reduce digital feedback.