The MPC8306/S and MPC8309 processors both feature 16 KB of L1 instruction and data caches, dual FPU and integer units, and on-chip memory management units (MMUs). These versatile processors also feature twin DMA engines together with a DDR2 memory controller, running at 266 MHz. A communications complex, based on NXP’s QUICC Engine offload technology, forms the heart of the networking capability of these processors. The NXP QUICC Engine integrates multiple peripheral controllers together with a dedicated 32-bit RISC engine. Protocol processing is carried out by the main workhorses of the device - the five unified communication controllers (UCCs). Each of the five programmable UCCs can support a variety of communication protocols, including 10/100 Mbps Ethernet, TDM or high-level data link control (HDLC). In addition, two of the UCCs can be used to support IEEE 1588 version-2 time stamping over Ethernet. The QUICC Engine also enables customers to bridge between industrial Ethernet and fieldbus network protocols, eliminating the need for an expensive FPGA and freeing processing headroom on the core processor. The MPC8306/S and MPC8309 also support low-cost boot options, including boot from NAND and NOR flash.