Use Modules with Integrated Amplifiers to Remove the “Black Magic” from High-Speed ADC Design
Contributed By Digi-Key's North American Editors
Designers of systems such as data acquisition, hardware in the loop (HiL), and power analyzers need an analog signal converter chain that can achieve high resolution and high accuracy at very high sample rates, often up to 15 mega samples per second (MSPS). However, high-speed analog designs can look like “black magic” to many designers, especially when faced with a series of hidden parasitics that impact the signal integrity.
For example, typical designs are discrete and contain several ICs and components, including a fully differential amplifier (FDA), a first (1st) order low-pass filter (LPF), a voltage reference, and a high-speed, high-resolution analog-to-digital converter (ADC). The capacitive and resistive parasitics are within and around the ADC driver amplifier (the FDA), the ADC input filter, and the ADC.
Eliminating, reducing, or mitigating the effects of these parasitics is challenging. It requires a high degree of skill and can require many circuit design cycles and pc board layout iterations, compromising design schedules and budgets. What’s required is a more complete and integrated solution that solves many of these design issues.
This article will describe a discrete data acquisition circuit and related layout issues, and then introduce an integrated module that contains a high-resolution, high-speed successive approximation register (SAR) ADC with a front-end FDA. The article shows how Analog Devices’ ADAQ23875 complete module and its associated development board overcomes high-speed design headaches by simplifying and accelerating the design process while still achieving the required high-resolution, high-speed conversion results.
High-speed data acquisition signal path
High-performance ADCs use differential inputs to improve overall performance by balancing the input signals and rejecting common-mode noise and interference. An analog ADC driver achieves optimum performance when the inputs to the analog ADC driver and ADC are fully differential (Figure 1). The use of a low-voltage differential signaling (LVDS) serial interface (right) allows the system to run at extremely high speeds to service data acquisition, HiL, and power analyzer applications.
Figure 1: A high-frequency data acquisition system with a front-end FDA, 1st order analog filter, and differential input SAR-ADC with a high-speed LVDS serial interface. (Image source: Bonnie Baker)
The configuration in Figure 1 performs many essential functions, including amplitude scaling, single-ended to differential conversion, buffering, common-mode offset adjustment, and filtering.
FDA driver technology
The FDA voltage feedback ADC driver’s operation is like a traditional amplifier except for two differences. First, the FDA has a differential output with an additional negative output terminal (VON). Second, it has an added input terminal (VOCM) that sets the output common-mode voltage (Figure 2).
Figure 2: The FDA has two inputs with feedback loops and voltage control (VOCM) of the output common-mode voltage. This configuration creates an independent differential input (VIN, dm) and differential output (VOUT, dm) voltages. (Image source: Analog Devices)
Internally, the FDA has three amplifiers: two at the input and the third acting as the output stage. The negative feedback (RF1, RF2) and high open-loop gain of two internal input amplifiers dictate the behavior of the input terminals, VA+ and VA–, to be virtually equal. Instead of a single-ended output, the FDA produces a balanced differential output between VOP and VON, with a common-mode voltage of VOCM.
The differential input signals (VIP and VIN) are equal in amplitude and opposite in phase around a common-mode reference voltage (VIN, cm) with a balanced input signal. Equations 1 and 2 show how to calculate the differential-mode input voltage (VIN, dm) and the common-mode input voltage (VIN, cm).
Equations 3 and 4 provide the output differential and common-mode definitions.
Note the addition of the VOCM in Equation 4.
As with typical amplifier circuits, the FDA system’s gain depends on RGx and RFx values. Equations 5 and 6 define the two input feedback factors, β1 and β2, for the FDA.
When β1 equals β2, Equation 7 gives the ideal closed-loop gain for the FDA.
VOUT, dm provides insight into the performance of resistive mismatches. The general closed-loop equation for VOUT, dm includes VIP, VIN, β1, β2, and VOCM. Equation 8 shows the formula for VOUT, dm with the amplifier’s open-loop voltage gain shown as A(s).
When β1 ≠ β2, the differential output voltage (VOUT, dm) error primarily depends on VOCM. This undesirable outcome produces an offset and excess noise in the differential output. If β1 = β2 ≡ β, Equation 8 becomes Equation 9.
The two output balance components are amplitude and phase. Amplitude balance measures whether the two output amplitudes are matching; ideally, they match exactly. The phase balance measures the closeness of the phase differences between the two outputs with the ideal equaling 180°.
FDA stability considerations are the same as for standard op-amps. The key specification is phase margin. Product datasheets provide the phase margin of a particular amplifier configuration; however, the pc board layout parasitic effects can significantly reduce the stability. In the case of a negative voltage feedback amplifier, it’s fairly straightforward: stability depends on its loop gain, A(s) × β, sign, and magnitude. The FDA, in contrast, has two feedback factors. Equations 8 and 9 have the loop gain in their denominators. Equation 10 describes the loop gain for the unmatched feedback factor case (β1 ≠ β2).
The mitigation of all the above errors depends on the tedious and expensive matching process with the discrete resistors RG1, RG2, RF1, and RF2.
FDA and ADC combined performance
The FDA, discrete resistors, 1st order filter, and ADC combination tell the story about the signal-to-noise ratio (SNR), total harmonic distortion (THD), signal-to-noise and distortion (SINAD), and spurious-free dynamic range (SFDR) that add to the FDA’s performance characteristics in the overall circuit accuracy and resolution. The combined specifications include the SNR, THD, SINAD, and SFDR. The FDA has numerous specifications that impact these frequency specifications, such as bandwidth, output voltage noise, distortion, stability, and settling time, all of which affect the ADC’s performance. The ADC has its own set of specifications. The significant challenge is to select the appropriate FDA to match the ADC.
Pc board layout is the last step in the design process. Unfortunately, layout can be an overlooked design step, resulting in a poor board design that can compromise or render the circuit useless. This complete discrete circuit has three integrated circuits, six resistors, and multiple decoupling capacitors (Figure 3).
Figure 3: FDA and SAR-ADC with 1st order LPF with power supply decoupling capacitors. (Image source: Analog Devices)
In Figure 3, the parasitic elements that undermine high-speed circuit performance are the pc board parasitic capacitance and inductance. Component pads, traces, vias, and ground in parallel with power planes are the culprits. These capacitances and inductances are especially dangerous at the amplifier’s summing nodes where they introduce poles and zeros in the feedback response, causing peaking and instability.
SAR converters can offer an FDA, crucial passive components, 1st order filters, a voltage reference, and decoupling capacitors to enhance the effective resolution. For instance, Analog Devices’ ADAQ23875 is a 16-bit, 15 MSPS data acquisition module with all these elements (Figure 4). As such, it reduces the development cycle of precision measurement systems by transferring the design load of component selection, optimization, and layout from the designer to the integrated circuit.
Figure 4: The ADAQ23875 simplifies the design of high-speed ADCs by combining an FDA, 1st order filter, SAR-ADC onto a single module supported by laser-trimmed gain resistors around the FDA, as well as on-chip decoupling capacitors. (Image source: Analog Devices)
The passive on-chip resistive components possess superior matching and drift characteristics to minimize parasitic dependent error sources and offer optimized performance to ensure the close matching of β1 and β2. The matching of these loop gains helps create the module’s ±1 millivolt (mV) offset and 91.6 microvolt root mean square (µVRMS) total RMS noise specifications.
The bandgap 2.048-volt voltage reference has low noise and low drift (20 parts per million per degree Celsius (ppm/°C)) to support the FDA and 16-bit ADC system. In conjunction with the FDA, these specifications translate to SAR-ADC 90 dB SNR accuracy and ±1 ppm/°C gain drift. The FDA’s VOCM pin uses the reference’s 2.048 volts to provide its output common-mode voltage.
An internal reference buffer gains the 2.048-volt reference by two to create 4.096 volts for the ADC reference voltage. The voltage difference between the ADC’s reference and GND determines the full-scale input range of the ADAQ23875’s SAR-ADC. Also, the ADAQ23875 has an on-chip 10 microfarad (μF) decoupling capacitor between reference buffer and GND to absorb SAR-ADC reference conversion charge spikes and alleviate the discrete design layout limitations.
As Figure 4 shows, the FDA’s input common-mode voltage is independent of the FDA’s output common-mode voltage. In examples one through three, the power supply voltages are:
VS+ = 7 volts (FDA positive supply voltage)
VS- = -2 volts (FDA negative supply voltage)
VDD = +5 volts (ADC supply voltage)
VIO = 2.5 volts (analog and digital output power supply)
Example 1 shows an input voltage range of ±1.024 volts with an input common-mode voltage of -1 volts. The FDA applies a 2 volt/volt gain to these signals, and the FDA level shifts the output voltage by the value at VCMO or 2.048 volts. The process presents a signal range of ±2.048 volts with a common-mode voltage from VCMO of 2.48 volts at the FDA’s output. The 1st order filter corner frequency is 1/(2pR x C) hertz (Hz) or ~78 megahertz (MHz). The signal input range to the ADC is ±2.048 volts, with a common-mode voltage of +2.048 volts.
The ADAQ23875’s has an LVDS digital interface with one-lane or two-lane output modes, allowing the user to optimize each application’s interface data rate. The digital power supply for the interface is VIO.
The ADAQ23875 has four power supplies: an internal ADC core supply (VDD), digital input/output interface supply (VIO), FDA positive supply (VS+), and negative supply (VS−). To alleviate pc board layout problems, all the supply pins have 0.1mF or 0.2 mF on-chip decoupling capacitors. It is necessary to place good quality 2.2 μF (0402, X5R) ceramic decouple capacitors on the pc board at the output of the LDO regulators. These regulators generate the μModule supply rails (VDD, VIO, VS+, and VS−) to minimize electromagnetic interference (EMI) susceptibility and reduce the effect on power supply line glitches. All of the other required decoupling capacitors are within the ADAQ23875, improving overall subsystem power supply rejection ratio (PSRR), and saving extra board space and cost. To use the internal reference and internal reference buffer, decouple the REFIN pin to GND with a 0.1 μF ceramic capacitor.
The ADAQ23875 module eliminates the headaches of selecting the appropriate FDA and resistive network for the ADC, while still ensuring high performance and tight specifications for SNR, THD, SINAD and SFDR (89.5 dB, -115.8 dB, 89 dB, and 114.3 dB, respectively) (Figure 5). Usually, the collection of the system specifications is up to the designer to execute. The ADAQ23875’s system approach helps designers achieve these specifications more efficiently.
Figure 5: The ADAQ23875 module creates SNR, THD, SINAD, SFDR specifications that pass through the on-chip FDA, 1st-order filter, and SAR-ADC. (Image Source: Analog Devices)
Figure 5 shows the SNR, THD, SINAD, and SFDR test results for a differential, 1 kHz input signal into the ADAQ23875. For a specific application, the EVAL-ADAQ23875FMCZ board for the ADAQ23875 has software to assist in device evaluations, including device programming, waveform, histogram, and FFT capture. Designers can connect the evaluation board to ADI’s EVAL-SDP-CH1Z system demonstration platform for power, and to allow control of the evaluation board by a PC through the SDP-CH1Z’s USB port (Figure 6).
Figure 6: The ADAQ23875FMCZ evaluation board (left) connected to the system demonstration platform (EVAL-SDP-CH1Z) board (right), allowing control of the evaluation board through the USB port of a PC. (Image source: Analog Devices)
The evaluation board’s software, ACE plugin for Board ADAQ23875 1.2021.8300 [Feb 18 21] and ACE Installer Software 1.21.2994.1347 [Feb 08 21], allows the user to configure each channel’s oversample value, input range, number of samples, and active channel selection. Additionally, this software also makes it possible to save and open test data files.
To overcome the challenges of high-speed analog design and deliver the best overall data acquisition performance, designers can turn to the ADAQ23875 module. This is a complete high-speed conversion system that includes an FDA, 1st order low-pass filter, SAR-ADC, and an array of decoupling capacitors that amplify the excitation signals and provide the appropriate drive signals, as well as the filtering and feeding back of secondary signals. A highly integrated module, the ADAQ23875 data acquisition system module rids the design of analog “black magic” with a complete FDA to SAR-ADC solution for high-speed data acquisition, hardware in the loop (HiL), and power analyzers.
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