Use an Advanced MOSFET Process for Greater Power Density and Reliability

Designers of power supplies for applications such as DC/DC converters, motor controls, load switching, data centers, and communications equipment are continually challenged to reduce the footprint of their designs to increase power density. However, higher power density requires devices with minimal heat dissipation to keep the operating temperature within bounds and support reliability. Achieving this requires active switching devices that are not only smaller but also have lower losses, allowing them to operate at higher efficiencies.

When selecting suitable switching devices, designers must carefully consider characteristics such as size, on-state resistance, breakdown voltage, switching speed, and reverse recovery charge.

This article provides a brief overview of the design requirements for power supplies used in relevant applications. It then introduces an advanced MOSFET process technology from Toshiba and shows how devices based on this technology can be used to meet these requirements.

How design requirements for power supplies are evolving

Electronic devices are becoming smaller across various applications, including communications, automotive, the Internet of Things (IoT), the Industrial IoT (IIoT), and wearables. Designers of these systems require switched-mode power supplies (SMPSs) in smaller sizes with higher power density. Achieving this higher power density requires components that are smaller and more efficient, allowing for a lower internal operating temperature and supporting high design reliability.

The most common active components in an SMPS are MOSFET switches, which are found in both the primary or high-voltage side, and the low-voltage secondary circuits (Figure 1).

Figure 1: Shown is an SMPS using low-voltage MOSFETs as a synchronous rectifier in the secondary side circuit; high-voltage MOSFETs form a full-bridge switch stage on the primary side. (Image source: Toshiba Semiconductor and Storage)

The primary side of the SMPS typically operates at a high voltage. For example, in supplies operating off the power line, the primary MOSFETs rectify the line voltage. The secondary side typically operates at a lower voltage; this is the intended application area for low-voltage MOSFETs.

High efficiency and low losses

High efficiency in a power supply is achieved by minimizing power losses. Losses associated with active semiconductor devices include conduction, switching, and body diode losses. These losses occur at various times within the device’s operating cycle (Figure 2).

Figure 2: The operating cycle of a MOSFET switch (left) includes the ON, OFF, and transition intervals (right), each with its own associated source of power loss. (Image source: Toshiba Semiconductor and Storage)

MOSFETs in an SMPS operate in either of two states, ON or OFF. The device state changes depending on the gate-to-source voltage (V_GS). When the device is on, the drain-to-source voltage (V_DS) is at a low level. In the ON state, the drain-to-source current (I_DS) through the device is determined by the load impedance and the ON-state drain-to-source resistance (R_DS(ON)). For an inductive load, the current increases linearly while it charges the magnetic field of the inductor. During the ON time, the current through the channel resistance generates conduction losses that are proportional to the square of I_DS and R_DS(ON). When the device is off, the V_DS is high, and the I_DS represents the device's leakage current, which determines the OFF-state conduction losses.

During the transitions between states, both voltage and current are simultaneously non-zero, and power is dissipated in the device in proportion to voltage, current, and switching frequency. These are the switching losses.

The recovery losses are caused by the reverse recovery of the MOSFET’s body diode when it is switched from a conducting to a nonconducting state. The remnant charge in the PN junction must be removed during this time, resulting in a reverse recovery current spike and its associated power loss. The loss is proportional to the device's reverse recovery charge (Q_rr), which determines the reverse recovery time.

The device’s total power loss is the sum of all these components.

How a trench structure enables more compact devices

The physical structure of a MOSFET affects the device’s size and dimensions. The trench MOSFET structure (Figure 3) is the most compact construction, offering the highest channel density while reducing R_DS(ON).

Figure 3: The trench MOSFET structure has a vertical current flow, resulting in a smaller footprint. (Image source: Toshiba Semiconductor and Storage)

Conventional planar MOSFETs use horizontal current flow; the trench-gate process forms a vertical gate channel in the shape of a U. This vertical flow reduces the device footprint, allowing more devices to be created on each wafer. The structure also decreases the R_DS(ON). Additionally, the higher layout density allows parallel connection of multiple devices, further reducing the ON-state resistance. The smaller size also decreases interelectrode capacitance, enabling faster switching and higher-frequency operation.

Switching losses are also a function of the duration of the transition region. The duration is governed by the parasitic capacitances of the device, which require a transfer of charge before the state of the MOSFET can be changed. The total gate charge (Q_g) is the amount of charge necessary to change the gate potential to its designated voltage. Lowering the switching losses requires shortening the switching time by decreasing Q_g. The product of R_DS(ON) and Q_g is a common figure of merit for a MOSFET, indicating a device's efficiency by combining conduction losses, which are proportional to R_DS(ON), and switching losses, which are inversely proportional to Q_g. Better performance is indicated by a lower value for the R_DS(ON) * Q_g product.

Since switching losses include a term for the reverse recovery loss of the body diode, the product of R_DS(ON) and Q_rr contributes to understanding the individual impact of conduction and switching losses. Although the product of R_DS(ON) and Q_rr are not a customary figure of merit, it provides another window into a MOSFET's total power loss.

Toshiba’s U-MOS 11-H MOSFETS

The Toshiba U-MOS11-H process, based on an improved trench structure, delivers MOSFET products with lower R_DS(ON) for reduced conduction losses and improved overall switching characteristics due to lower Q_g and Q_rr, making it a solid fit for low-voltage and high-efficiency applications, such as SMPSs, motor drives, and server power supplies.

The Toshiba TPH2R70AR5-LQ MOSFET is rated at 100 V and exemplifies the improvements in the U-MOS11-H process. Compared to an equivalent device from an earlier process, the TPH2R70AR5 offers an R_DS(ON) that is approximately 8% lower and a Q_g that is 37% lower. The resulting R_DS(ON) * Q_g figure of merit is 42% lower.

The reverse recovery losses are minimized by using lifetime control technology, which introduces ion-beam-induced defects in the semiconductor to increase switching speed and reduce Q_rr. Q_rr is enhanced by 38%, and the resulting R_DS(ON) * Q_rr product is reduced by 43%. These lower figures of merit indicate lower power loss, higher efficiency, and higher power density.

The TPH2R70AR5-LQ can handle a maximum drain-to-source voltage of 100 V, and drain currents up to 22 A in an ambient environment and up to 190 A with cooling (a case temperature of +25°C).

The R_DS(ON) is 2.7 mΩ, worst case, for a drain current of 50 A and a gate drive of 10 V; the R_DS(ON) is 3.6 mΩ, worst case, for an 8 V gate drive signal. Q_g is typically 52 nC with a gate drive of 10 V, and the typical Q_rr is 55 nC.

The TPH2R70AR5-LQ comes in a 5.15 mm × 6.1 mm × 1 mm surface-mount SOP Advance(N) package (Figure 4), providing excellent mounting compatibility with industry standards.

Figure 4: Shown are a view of the SOP Advance(N) package (left) and the internal circuit connections for the TPH2R70AR5-LQ (right). (Image source: Toshiba Semiconductor and Storage)

This package size is matched to the MOSFET’s 100 V maximum V_DS ratings. Lower-voltage devices have smaller package dimensions due to the decreased spacing requirements.

Toshiba’s support for this product includes a fast G0 SPICE grade model to aid designers in quickly verifying circuit function. They also make available a more precise G2 SPICE grade model that includes transient analysis.

Conclusion

The Toshiba TPH2R70AR5-LQ low-voltage MOSFET is specifically designed for use on the secondary side of an SMPS. It uses a novel cell structure that reduces power losses and improves the switching characteristics of the transistor, enabling the design of power devices with high power density and reliability for modern applications.