LTC2607, 2617, 2627 Datasheet by Analog Devices Inc.

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l ’ LI” LTC2607 LTC2617 LTC2627 TECHNOLOGY um may L7 LJUW
LTC2607/LTC2617/LTC2627
1
26071727fa
Block Diagram
Features Description
16-/14-/12-Bit Dual Rail-to-Rail
DACs with I2C Interface
The LTC
®
2607/LTC2617/LTC2627 are dual 16-, 14- and
12-bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a
12-lead DFN package. They have built-in high performance
output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.
The parts use a 2-wire, I2C compatible serial interface. The
LTC2607/LTC2617/LTC2627 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.
The LTC2607/LTC2617/LTC2627 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2607-1/LTC2617-1/
LTC2627-1 to mid-scale. The voltage outputs stay at mid-
scale until a valid write and update takes place.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245 and 6891433. Patent Pending.
applications
n Smallest Pin-Compatible Dual DACs:
LTC2607: 16 Bits
LTC2617: 14 Bits
LTC2627: 12 Bits
n Guaranteed Monotonic Over Temperature
n 27 Selectable Addresses
n 400kHz I2C Interface
n Wide 2.7V to 5.5V Supply Range
n Low Power Operation: 260µA per DAC at 3V
n Power Down to 1µA, Max
n High Rail-to-Rail Output Drive (±15mA, Min)
n Ultralow Crosstalk (30µV)
n Double-Buffered Data Latches
n Asynchronous DAC Update Pin
n LTC2607/LTC2617/LTC2627: Power-On Reset to
Zero Scale
n LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset
to Mid-Scale
n Tiny (3mm × 4mm) 12-Lead DFN Package
n Mobile Communications
n Process Control and Industrial Automation
n Instrumentation
n Automatic Test Equipment
Differential Nonlinearity
(LTC2607)
9811 10
5 6
21 43
2-WIRE INTERFACE
CA0 CA1 LDAC SCL SDA
REFLO GND REF VCC
CA2
32-BIT SHIFT REGISTER
INPUT REGISTER INPUT REGISTER
DAC REGISTER DAC REGISTER
7
12-/14-/16-BIT DAC
VOUTB
12 12-/14-/16-BIT DAC
VOUTA
2607 BD01a
CODE
0 16384 32768 49152 65535
DNL (LSB)
2607 BD01b
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
LTC2607/LTC2617/LTC2627 L7LJCUEN2
LTC2607/LTC2617/LTC2627
2
26071727fa
pin conFigurationaBsolute maximum ratings
Any Pin to GND ............................................ 0.3V to 6V
Any Pin to VCC ............................................. 6V to 0.3V
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range .................. 65°C to 125°C
Lead Temperature (Soldering, 10 sec)...................300°C
Operating Temperature Range:
LTC2607C/LTC2617C/LTC2627C
LTC2607C-1/LTC2617C-1/LTC2627C-1 .... 0°C to 70°C
LTC2607I/LTC2617I/LTC2627I
LTC2607I-1/LTC2617I-1/LTC2627I-1 ....40°C to 85°C
(Note 1)
TOP VIEW
13
DE12 PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
12
11
8
9
10
4
5
3
2
1VOUTA
REFLO
GND
REF
VCC
VOUTB
CA0
CA1
LDAC
SCL
SDA
CA2 7
6
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
orDer inFormation
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2607CDE#PBF LTC2607CDE#TRPBF 2607 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2607IDE#PBF LTC2607IDE#TRPBF 2607 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC2607CDE-1#PBF LTC2607CDE-1#TRPBF 26071 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2607IDE-1#PBF LTC2607IDE-1#TRPBF 26071 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC2617CDE#PBF LTC2617CDE#TRPBF 2617 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2617IDE#PBF LTC2617IDE#TRPBF 2617 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC2617CDE-1#PBF LTC2617CDE-1#TRPBF 26171 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2617IDE-1#PBF LTC2617IDE-1#TRPBF 26171 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC2627CDE#PBF LTC2627CDE#TRPBF 2627 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2627IDE#PBF LTC2627IDE#TRPBF 2627 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC2627CDE-1#PBF LTC2627CDE-1#TRPBF 26271 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2627IDE-1#PBF LTC2627IDE-1#TRPBF 26271 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC2607/LTC2617/LTC2627 L7 LJUW 3
LTC2607/LTC2617/LTC2627
3
26071727fa
electrical characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,
VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
DC Performance
Resolution l12 14 16 Bits
Monotonicity (Note 2) l12 14 16 Bits
DNL Differential Nonlinearity (Note 2) l±0.5 ±1 ±1 LSB
INL Integral Nonlinearity (Note 2) l±1.5 ±4 ±5 ±16 ±19 ±64 LSB
Load Regulation VREF = VCC = 5V, Mid-Scale
IOUT = 0mA to 15mA Sourcing
IOUT = 0mA to 15mA Sinking
l
l
0.02
0.03
0.125
0.125
0.1
0.1
0.5
0.5
0.35
0.42
2
2
LSB/mA
LSB/mA
VREF = VCC = 2.7V, Mid-Scale
IOUT = 0mA to 7.5mA Sourcing
IOUT = 0mA to 7.5mA Sinking
l
l
0.04
0.05
0.25
0.25
0.2
0.2
1
1
0.7
0.8
4
4
LSB/mA
LSB/mA
ZSE Zero-Scale Error Code = 0 l1 9 1 9 1 9 mV
VOS Offset Error (Note 6) l±1 ±9 ±1 ±9 ±1 ±9 mV
VOS Temperature
Coefficient
±7 ±7 ±7 µV/°C
GE Gain Error l±0.15 ±0.7 ±0.15 ±0.7 ±0.15 ±0.7 %FSR
Gain Temperature
Coefficient
±4 ±4 ±4 ppm/°C
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSR Power Supply Rejection VCC ±10% –80 dB
ROUT DC Output Impedance VREF = VCC = 5V, Mid-Scale;
–15mA ≤ IOUT ≤ 15mA
VREF = VCC = 2.7V, Mid-Scale;
–7.5mA ≤ IOUT ≤ 7.5mA
l
l
0.032
0.035
0.15
0.15
Ω
Ω
DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5)
Due to Load Current Change
Due to Powering Down (Per Channel)
±4
±3
±30
µV
µV/mA
µV
ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
l
l
15
15
36
37
60
60
mA
mA
VCC = 2.7V, VREF = 2.7V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
l
l
7.5
7.5
22
30
50
50
mA
mA
Reference Input
Input Voltage Range l0 VCC V
Resistance Normal Mode l44 64 80
Capacitance 30 pF
IREF Reference Current, Power Down Mode DAC Powered Down l0.001 1 µA
LTC2607/LTC2617/LTC2627
LTC2607/LTC2617/LTC2627
4
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electrical characteristics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VCC Positive Supply Voltage For Specified Performance l2.7 5.5 V
ICC Supply Current VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
l
l
l
l
0.66
0.52
0.4
0.10
1.3
1
1
1
mA
mA
µA
µA
Digital I/O (Note 11)
VIL Low Level Input Voltage (SDA and SCL) l0.3VCC V
VIH High Level Input Voltage (SDA and SCL) l0.7VCC V
VIL(LDAC)Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
l
l
0.8
0.6
V
V
VIH(LDAC)High Level Input Voltage (LDAC) VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
l
l
2.4
2.0
V
V
VIL(CAn)Low Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1 l0.15VCC V
VIH(CAn)High Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 l0.85VCC V
RINH Resistance from CAn (n = 0, 1, 2)
to VCC to Set CAn = VCC
See Test Circuit 2 l10 kΩ
RINL Resistance from CAn (n = 0, 1, 2)
to GND to Set CAn = GND
See Test Circuit 2 l10 kΩ
RINF Resistance from CAn (n = 0, 1, 2)
to VCC or GND to Set CAn = Float
See Test Circuit 2 l2 MΩ
VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V
tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 9)
l20 + 0.1CB250 ns
tSP Pulse Width of Spikes Suppressed by Input Filter l0 50 ns
IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1 µA
CIN I/O Pin Capacitance Note 12 l10 pF
CBCapacitive Load for Each Bus Line l400 pF
CCAX External Capacitive Load on Address
Pins CAn (n = 0, 1, 2)
l10 pF
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,
VOUT unloaded, unless otherwise noted.
LTC2607/LTC2617/LTC2627 L7 LJUW 5
LTC2607/LTC2617/LTC2627
5
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electrical characteristics
timing characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL and LDAC at 0V or VCC, CA0, CA1 and CA2 Floating.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with
the measured DAC at mid-scale, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
fSCL SCL Clock Frequency l0 400 kHz
tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs
tLOW Low Period of the SCL Clock Pin l1.3 µs
tHIGH High Period of the SCL Clock Pin l0.6 µs
tSU(STA) Set-Up Time for a Repeated Start Condition l0.6 µs
tHD(DAT) Data Hold Time l0 0.9 µs
tSU(DAT) Data Set-Up Time l100 ns
trRise Time of Both SDA and SCL Signals (Note 9) l20 + 0.1CB300 ns
tfFall Time of Both SDA and SCL Signals (Note 9) l20 + 0.1CB300 ns
tSU(STO) Set-Up Time for Stop Condition l0.6 µs
tBUF Bus Free Time Between a Stop and Start Condition l1.3 µs
t1Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
l400 ns
t2LDAC Low Pulse Width l20 ns
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,
VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
AC Performance
tSSettling Time (Note 7) ±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7 7
9
7
9
10
µs
µs
µs
Settling Time for 1LSB Step
(Note 8)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7 2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate 0.8 0.8 0.8 V/µs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Mid-Scale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
enOutput Voltage Noise Density At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µVP-P
Note 5: RL = 2kΩ to GND or VCC.
Note 6: Inferred from measurement at code kL (Note 2) and at full scale.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifications apply to LTC2607/LTC2607-1,
LTC2617/LTC2617-1, LTC2627/LTC2627-1.
Note 12: Guaranteed by design and not production tested.
LTC2607/LTC2617/LTC2627 muss) amass) DNL (LSB) INL (LSB) muss) amass) s THJNGT msa vcc = 5v. vREp 4 new DUDE mm 55535 STEP AVERAGE orzuAa EVENTS
LTC2607/LTC2617/LTC2627
6
26071727fa
typical perFormance characteristics
DNL vs Temperature INL vs VREF DNL vs VREF
Settling to ±1LSB Settling of Full-Scale Step
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
LTC2607
CODE
016384 32768 49152 65535
INL (LSB)
2607 G01
32
24
16
8
0
–8
–16
–24
–32
VCC = 5V
VREF = 4.096V
CODE
0 16384 32768 49152 65535
DNL (LSB)
2607 G02
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
VREF (V)
012345
INL (LSB)
2607 G05
32
24
16
8
0
–8
–16
–24
–32
VCC = 5.5V
INL (POS)
INL (NEG)
VREF (V)
012345
DNL (LSB)
2607 G06
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5.5V
DNL (POS)
DNL (NEG)
2µs/DIV 2607 G07
VOUT
100µV/DIV
SCL
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
9TH CLOCK
OF 3RD DATA
BYTE
9.7µs
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
SCL
2V/DIV
VOUT
100µV/DIV
9TH CLOCK OF
3RD DATA BYTE
12.3µs
5µs/DIV 2607 G08
muss) |NL(LSB) L7 LJUW DNL (LSB) DNL (LSB) LTC2607/LTC2617/LTC2627 “f4 f
LTC2607/LTC2617/LTC2627
7
26071727fa
typical perFormance characteristics
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
LTC2617
LTC2627
CODE
04096 8192 12288 16383
INL (LSB)
2607 G09
8
6
4
2
0
–2
–4
–6
–8
VCC = 5V
VREF = 4.096V
CODE
0 4096 8192 12288 16383
DNL (LSB)
2607 G10
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
2µs/DIV 2607 G11
VOUT
100µV/DIV
SCL
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
8.9µs
9TH CLOCK
OF 3RD DATA
BYTE
CODE
01024 2048 3072 4095
INL (LSB)
2607 G12
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
VCC = 5V
VREF = 4.096V
CODE
0 1024 2048 3072 4095
DNL (LSB)
2607 G13
VCC = 5V
VREF = 4.096V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
2µs/DIV 2607 G14
VOUT
1mV/DIV
SCL
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
6.8µs
9TH CLOCK
OF 3RD DATA
BYTE
LTC2607/LTC2617/LTC2627 35 SEE Emma vac : 3v VREF z vac : 5v VREF $5 3 >4 SE 55b Emma é {SE 2.3 :5 Est flém‘omw 450 Ems: SEW 2.45
LTC2607/LTC2617/LTC2627
8
26071727fa
Zero-Scale Error vs Temperature Gain Error vs Temperature Offset Error vs VCC
Gain Error vs VCC ICC Shutdown vs VCC
Current Limiting Load Regulation Offset Error vs Temperature
LTC2607/LTC2617/LTC2627
IOUT (mA)
–40 –30 –20 –10 0 10 20 30 40
∆VOUT (V)
2607 G15
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
VREF = VCC = 5V
VREF = VCC = 3V
VREF = VCC = 5V
VREF = VCC = 3V
CODE = MID-SCALE
IOUT (mA)
–35 –25 –15 –5 5 15 25 35
∆VOUT (mV)
2607 G16
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VREF = VCC = 5V
CODE = MID-SCALE
VREF = VCC = 3V
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
OFFSET ERROR (mV)
2607 G20
3
2
1
0
–1
–2
–3
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
GAIN ERROR (%FSR)
2607 G21
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
ICC (nA)
2607 G22
450
400
350
300
250
200
150
100
50
0
typical perFormance characteristics
LTC2607/LTC2617/LTC2627 J L L z£ 25us/DN %0 V rM law“ Iann WM L7 LJUW 9
LTC2607/LTC2617/LTC2627
9
26071727fa
typical perFormance characteristics
Headroom at Rails
vs Output Current Power-On Reset to Midscale
Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset to Zeroscale
LTC2607/LTC2617/LTC2627
Supply Current vs Logic Voltage
Supply Current vs Logic Voltage
LOGIC VOLTAGE (V)
0
500
ICC (µA)
550
650
700
750
3 3.5 4 4.5
950
2607 G28
600
0.5 1 1.5 2 2.5 5
800
850
900 VCC = 5V
SWEEP LDAC
OV TO VCC
LOGIC VOLTAGE (V)
0
ICC (µA)
800
900
1000
35
2607 G029
700
600
500 1 2 4
1100
1200
1300
HYSTERSIS
370mV
VCC = 5V
SWEEP SCL AND
SDA OV TO VCC
AND VCC TO OV
2.5µs/DIV
VOUT
0.5V/DIV
2607 G23
VREF = VCC = 5V
1/4-SCALE TO 3/4-SCALE
IOUT (mA)
012345678910
VOUT (V)
2607 G26
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
3V SOURCING
3V SINKING
5V SINKING
VOUT
10mV/DIV
250µs/DIV 2607 G25
VCC
1V/DIV
4mV PEAK
1V/DIV
500µs/DIV 2607 G27
VCC
VOUT
VREF = VCC
VOUT
10mV/DIV
SCL
2V/DIV
2.5µs/DIV 2607 G24
TRANSITION FROM
MS-1 TO MS
TRANSITION FROM
MS TO MS-1
9TH CLOCK
OF 3RD DATA
BYTE
Multiplying Bandwidth
Output Voltage Noise,
0.1Hz to 10Hz
FREQUENCY (Hz)
1k
dB
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36 1M
2607 G30
10k 100k
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
VOUT
10µV/DIV
SECONDS
012345678910
2607 G31
LTC2607/LTC2617/LTC2627
LTC2607/LTC2617/LTC2627
10
26071727fa
pin Functions
CA0 (Pin 1): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (Table 1).
CA1 (Pin 2): Chip Address Bit 1. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (Table 1).
LDAC (Pin 3): Asynchronous DAC Update. A falling edge
of this input after four bytes have been written into the part
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part wakes up sleeping DACs without up-
dating the DAC output. Software power-down is disabled
when LDAC is low. LDAC is disabled when tied high.
SCL (Pin 4): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to VCC.
SDA (Pin 5): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in and an open-
drain N-channel output during acknowledgment. Requires
a pull-up resistor or current source to VCC.
CA2 (Pin 6): Chip Address Bit 2. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (Table 1).
VOUTB (Pin 7): DAC Analog Voltage Output. The output
range is VREFLO to VREF.
VCC (Pin 8): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
REF (Pin 9): Reference Voltage Input. The input range
is VREFLO ≤ VREF ≤ VCC.
GND (Pin 10): Analog Ground.
REFLO (Pin 11): Reference Low. The voltage at this pin
sets the zero scale (ZS) voltage of all DACs. The VREFLO pin
can be used at voltages up to 1V for VCC = 5V, or 100mV
for VCC = 3V.
VOUTA (Pin 12): DAC Analog Voltage Output. The output
range is VREFLO to VREF.
Exposed Pad (Pin 13): Ground. Must be soldered to
PCB ground.
Short-Circuit Output Current vs
VOUT (Sinking)
Short-Circuit Output Current vs
VOUT (Sourcing)
1V/DIV
0
0
10mA/DIV
10
20
30
40
50
12 3 4
2607 G32
5 6
VCC = 5.5V
VREF = 5.6V
CODE = 0
VOUT SWEPT 0V TO VCC
1V/DIV
0
–50
10mA/DIV
–40
–30
–20
–10
0
12 3 4
2607 G33
5 6
VCC = 5.5V
VREF = 5.6V
CODE = FULL SCALE
VOUT SWEPT VCC TO 0V
LTC2607/LTC2617/LTC2627
typical perFormance characteristics
LTC2607/LTC2617/LTC2627 EJ—< (jr‘="" t=""> >—EJ 4} 4} fl 4} E 4} —EE E fi fi E ________________ .+ i, ________________ i L7 LJUW 1 1
LTC2607/LTC2617/LTC2627
11
26071727fa
Block Diagram
test circuits
9811 10
5 6
21 43
2-WIRE INTERFACE
CA0 CA1 LDAC SCL SDA
REFLO GND REF VCC
CA2
32-BIT SHIFT REGISTER
INPUT REGISTER INPUT REGISTER
DAC REGISTER DAC REGISTER
7
12-/14-/16-BIT DAC
VOUTB
12 12-/14-/16-BIT DAC
VOUTA
2607 BD
100Ω RINH/RINL/RINF
VIH(CAn)/VIL(CAn)
CAn
GND
2607 TC
VDD
Test Circuit 2Test Circuit 1
CAn
LTC2607/LTCZé17/LTC2627 333$ L7LJCUEN2 12
LTC2607/LTC2617/LTC2627
12
26071727fa
timing Diagrams
Figure 2a
Figure 2b
Figure 1
SDA
tf
S
tr
tLOW
tHD(STA)
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
tHD(DAT)
tSU(DAT)
tSU(STA)
tHD(STA)
tSU(STO)
tSP tBUF
tr
tf
tHIGH
SCL
S P S 2607 F01
ACK ACK
123456789123456789123456789123456789
2607 F02A
ACK
t1
START
SDA SA6 SA5 SA4 SA3
SLAVE ADDRESS
SA2 SA1 SA0
SCL
LDAC
C2C3 C1 C0 A3 A2 A1 A0 ACK
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
t2
9TH CLOCK
OF 3RD
DATA BYTE
t1
SCL
LDAC
2607 F02b
LTC2607/LTC2617/LTC2627 L7HEJN§4R 1 3
LTC2607/LTC2617/LTC2627
13
26071727fa
operation
specifications. For an I2C bus operating in the fast mode,
an active pull-up will be necessary if the bus capacitance is
greater than 200pF. The VCC power should not be removed
from the LTC2607/LTC2617/LTC2627 when the I2C bus
is active to avoid loading the I2C bus lines through the
internal ESD protection diodes.
The LTC2607/LTC2617/LTC2627 are receive-only (slave)
devices. The master can write to the LTC2607/LTC2617/
LTC2627. The LTC2607/LTC2617/LTC2627 do not respond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the lat-
est byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge clock
pulse. The slave-receiver must pull down the SDA bus line
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2607/LTC2617/LTC2627 respond to a write by a
master in this manner. The LTC2607/LTC2617/LTC2627
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: VCC, GND or float. This results
Power-On Reset
The LTC2607/LTC2617/LTC2627 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2607-1/
LTC2617-1/LTC2627-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2607/
LTC2617/LTC2627 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 9) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 8) is in transition.
Transfer Function
The digital-to-analog transfer function is:
VkV V V
OUT IDEAL NREF REFLO REFLO( ) =
( )
+
2
where k is the decimal equivalent of the binary DAC
input code, N is the resolution and VREF is the voltage at
REF (Pin 6).
Serial Digital Interface
The LTC2607/LTC2617/LTC2627 communicate with a
host using the standard 2-wire I2C interface. The Timing
Diagrams (Figures 1 and 2) show the timing relationship
of the signals on the bus. The two bus lines, SDA and
SCL, must be high when the bus is not in use. External
pull-up resistors or current sources are required on these
lines. The value of these pull-up resistors is dependent
on the power supply and can be obtained from the I2C
LTC2607/LTC2617/LTC2627
LTC2607/LTC2617/LTC2627
14
26071727fa
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
Table 1. Slave Address Map
CA2 CA1 CA0 SA6 SA5 SA4 SA3 SA2 SA1 SA0
GND GND GND 0 0 1 0 0 0 0
GND GND FLOAT 0 0 1 0 0 0 1
GND GND VCC 0010010
GND FLOAT GND 0 0 1 0 0 1 1
GND FLOAT FLOAT 0 1 0 0 0 0 0
GND FLOAT VCC 0100001
GND VCC GND0100010
GND VCC FLOAT 0 1 0 0 0 1 1
GND VCC VCC 0110000
FLOAT GND GND 0 1 1 0 0 0 1
FLOAT GND FLOAT 0 1 1 0 0 1 0
FLOAT GND VCC 0110011
FLOAT FLOAT GND 1 0 0 0 0 0 0
FLOAT FLOAT FLOAT 1 0 0 0 0 0 1
FLOAT FLOAT VCC 1000010
FLOAT VCC GND1000011
FLOAT VCC FLOAT 1 0 1 0 0 0 0
FLOAT VCC VCC 1010001
VCC GND GND 1 0 1 0 0 1 0
VCC GND FLOAT 1 0 1 0 0 1 1
VCC GND VCC 1100000
VCC FLOAT GND 1 1 0 0 0 0 1
VCC FLOAT FLOAT 1 1 0 0 0 1 0
VCC FLOAT VCC 1100011
VCC VCC GND1110000
VCC VCC FLOAT 1 1 1 0 0 0 1
VCC VCC VCC 1110010
GLOBAL ADDRESS 1 1 1 0 0 1 1
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2607, LTC2617 and
LTC2627 parts to be accomplished with one 3-byte write
transaction on the I2C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
operation
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven during
address detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2607/
LTC2617/LTC2627 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2607/
LTC2617/LTC2627 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the
global address. The master then transmits three bytes of
data. The LTC2607/LTC2617/LTC2627 acknowledges each
byte of data by pulling the SDA line low at the 9th clock of
each data byte transmission. After receiving three complete
bytes of data, the LTC2607/LTC2617/LTC2627 executes the
command specified in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2607/LTC2617/LTC2627 do not
acknowledge the extra bytes of data (SDA is high during
the 9th clock).
The format of the three data bytes is shown in Figure 3.
The first byte of the input word consists of the 4-bit com-
mand word C3-C0, and 4-bit DAC address A3-A0. The next
two bytes consist of the 16-bit data word. The 16-bit data
word consists of the 16-, 14- or 12-bit input code, MSB
to LSB, followed by 0, 2 or 4 don’t care bits (LTC2607,
LTC2617 and LTC2627 respectively). A typical LTC2607
write transaction is shown in Figure 4.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
LTC2607/LTC2617/LTC2627 Write Wnrfl Plnlnnnl lnr LTCZfifl7/LTCZG17/LTC1627 SLAVE ADDRESS “V ST DATA aw: m 2ND DATA an: m 3m) DATA EWE L7HEJN§4R 1 5
LTC2607/LTC2617/LTC2627
15
26071727fa
operation
Table 2
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power Up) DAC Register
0 0 1 1 Write to and Update (Power Up)
0 1 0 0 Power Down
1 1 1 1 No Operation
ADDRESS*
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 0 1 DAC B
1 1 1 1 All DACs
*Command and address codes not shown are reserved and should not be used.
Power-Down Mode
For power-constrained applications, the power-down mode
can be used to reduce the supply current whenever one or
both of the DAC outputs are not needed. When in power-
down, the buffer amplifiers, bias circuits and reference input
are disabled and draw essentially zero current. The DAC
outputs are put into a high impedance state, and the output
pins are passively pulled to VREFLO through 90k resistors.
Input-register and DAC-register contents are not disturbed
during power-down.
Either or both DAC channels can be put into power-down
mode by using command 0100b in combination with the
Figure 3
C3
1ST DATA BYTE
Input Word (LTC2607)
Write Word Protocol for LTC2607/LTC2617/LTC1627
C2 C1 C0 A3 A2 A1 A0 D13D14D15
SW A
SLAVE ADDRESS 1ST DATA BYTE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A 2ND DATA BYTE A 3RD DATA BYTE A P
2607 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2617)
C2 C1 C0 A3 A2 A1 A0 D11D12D13 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
2ND DATA BYTE 3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2627)
C2 C1 C0 A3 A2 A1 A0 D9D10D11 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
2ND DATA BYTE 3RD DATA BYTE
appropriate DAC address. The 16-bit data word is ignored.
The supply and reference currents are reduced by approxi-
mately 50% for each DAC powered down; the effective
resistance at REF (Pin 9) rises accordingly, becoming a
high-impedance input (typically > 1GΩ) when both DACs
are powered down.
Normal operation can be resumed by executing any
command which includes a DAC update, as shown in
Table 2 or performing an asychronous update (LDAC) as
described in the next section. The selected DAC is powered
up as its voltage output is updated. When a DAC in powered-
down state is powered up and updated, normal settling
is delayed. If one of the two DACs is in a powered- down
state prior to the update command, the power up delay is
5µs. If on the other hand, both DACs are powered down,
the main bias generation circuit has been automatically
shut down in addition to the DAC amplifiers and reference
input and so the power up delay time is
12µs (for VCC = 5V) or 30µs (for VCC = 3V)
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC registers with
the contents of the input registers. Asynchronous update
is disabled when the input word is being clocked into
the part.
LTC2607/LTC2617/LTC2627
LTC2607/LTC2617/LTC2627
16
26071727fa
operation
If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC registers to be updated
with the contents of the input registers.
If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DACs but does not cause the outputs
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recognized,
the command specified in the 24-bit word just transferred
is executed and the DAC outputs updated.
The DACs are powered up when LDAC is taken low, inde-
pendent of any activity on the I2C bus.
If LDAC is low at the falling edge of the 9th clock of the
3rd byte of data, it inhibits any software power-down
command that was specified in the input word. LDAC is
disabled when tied high.
Voltage Output
Both of the two rail-to-rail amplifiers have guaranteed
load regulation when sourcing or sinking up to 15mA at
5V (7.5mA at 3V).
Load regulation is a measure of the amplifiers’ ability to
maintain the rated voltage accuracy over a wide range
of load conditions. The measured change in output volt-
age per milliampere of forced load current change is
expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.035Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited
by the 30Ω typical channel resistance of the output
devices; e.g., when sinking 1mA, the minimum output
voltage = 30Ω 1mA = 30mV. See the graph Headroom
at Rails vs Output Current in the Typical Performance
Characteristics section.
The amplifiers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation performance is achieved in
part by separating the signal and power grounds as REFLO
and GND pins, respectively.
The PC Board should have separate areas for the analog
and digital sections of the circuit. This keeps the digital
signals away from the sensitive analog signals and facili-
tates the use of separate digital and analog ground planes
that have minimal interaction with each other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground. Ideally, the
analog ground plane should be located on the component
side of the board, and should be allowed to run under the
part to shield it from noise. Analog ground should be a
continuous and uninterrupted plane, except for necessary
lead pads and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to the analog power
supply return should be as low as possible. Resistance
here will add directly to the channel resistance of the output
device when sinking load current. When a zero scale DAC
output voltage of zero is required, the REFLO pin should
be connected to system star ground. Any shared trace
resistance between REFLO and GND pins is undesirable
since it adds to the effective DC output impedance (typi-
cally 0.035
Ω
) of the part.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in Figure
5b. Similarly, limiting can occur near full scale when the
REF pin is tied to VCC. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 5c. No full-scale limiting
will occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
LTC2607/LTC2617/LTC2627 LS um Msum comm“; sum RDDRESS |||\||||1l||||l|||l|l||||||||||l|||| L7HEJN§4R 1 7
LTC2607/LTC2617/LTC2627
17
26071727fa
operation
Figure 4. Typical LTC2607 Input Waveform—Programming DAC Output for Full Scale
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
ACK ACK
123456789123456789123456789123456789
2607 F04
ACK
START
X = DON’T CARE
STOP
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
SDA SA6 SA5 SA4 SA3 SA2 SA1 SA0
SCL
VOUT
C2C3
C3 C2 C1 C0 A3 A2 A1 A0
C1 C0 A3 A2 A1 A0 ACK
COMMAND
D15 D14 D13 D12 D11 D10 D9 D8
MS DATA
D7 D6 D5 D4 D3 D2 D1 D0
LS DATA
SA6 SA5 SA4 SA3 SA2 SA1 SA0 WR
SLAVE ADDRESS
2607 F05
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32, 7680 65, 535
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
LTC2607/LTC2617/LTC2627 L L anfifimn: M-,,,_,,,i Q I L L *le 1* x i \O 1 LWL; A + +
LTC2607/LTC2617/LTC2627
18
26071727fa
package Description
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
4.00 p0.10
(2 SIDES)
3.00 p0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 p 0.10
0.75 p0.05
R = 0.115
TYP
R = 0.05
TYP
2.50 REF
16
127
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0806 REV D
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 p0.05
0.70 p0.05
3.60 p0.05
PACKAGE OUTLINE
3.30 p0.10
0.25 p 0.05
0.50 BSC
1.70 p 0.05
3.30 p0.05
0.50 BSC
0.25 p 0.05
LTC2607/LTC2617/LTC2627 L7HEJN§4R 1 9
LTC2607/LTC2617/LTC2627
19
26071727fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision history
REV DATE DESCRIPTION PAGE NUMBER
A 1/10 Revised Features
Added Pin Configuration and Updated Order Information
Added Text to Serial Digital Interface Section
1
2
13
LTC2607/LTC2617/LTC2627 20 L7ELUEN2
LTC2607/LTC2617/LTC2627
20
26071727fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2005
LT 0110 REV A • PRINTED IN USA
relateD parts
typical application
PART NUMBER DESCRIPTION COMMENTS
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654 Dual 14-Bit Rail-to-Rail VOUT DAC Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
LTC1655/LTC1655L Single 16-Bit VOUT DACs with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L Parallel 5V/3V 16-Bit VOUT DACs Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1664 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610/
LTC2620
Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2601/LTC2611/
LTC2621
Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2602/LTC2612/
LTC2622
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2604/LTC2614/
LTC2624
Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2605/LTC2615/
LTC2625
Octal 16-/14-/12-Bit VOUT DACs with I2C Interface 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output, I2C Interface
LTC2606/LTC2616/
LTC2626
16-/14-/12-Bit VOUT DACs with I2C Interface 270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output, I2C Interface
LTC2609/LTC2619/
LTC2629
Quad 16-/14-/12-Bit VOUT DACs with I2C Interface 250µA Range per DAC, 2.7V to 5.5V Supply Range,
Rail-to-Rail Output with Separate VREF Pins for Each DAC
Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters
9
8
7
10
3
1
2
6
4
5
5 6
28 6 1
2607 TA01
10, 13
I2C BUS
VREF
1V TO 5V 0.1µF
SPI BUS
5V5V
7 3
100Ω 7.5k
DAC
OUTPUT B
12 4
100Ω 7.5k
DAC
OUTPUT A
FO
SCK
SDO
CS
VCC
FSSET
GND
ZSSET
LTC2422
VCC REF
GND REFLO
LTC2607
LDAC
CA0
CA1
CA2
SCL
SDA
VOUTB
VOUTA
CH 1
CH 0

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