LTC3112 Datasheet by Analog Devices Inc.

View All Related Products | Download PDF Datasheet
L7L|nt “I2 LTC3112 TECHNOLOGY BURST PWM err ON I _ . L7 LJUW
LTC3112
1
3112fd
For more information www.linear.com/LTC3112
TYPICAL APPLICATION
DESCRIPTION
15V, 2.5A Synchronous
Buck-Boost DC/DC
Converter
The LT C
®
3112 is a fixed frequency synchronous buck-boost
DC/DC converter with an extended input and output range.
The unique 4-switch, single inductor architecture provides
low noise and seamless operation from input voltages
above, below or equal to the output voltage.
With an input range of 2.7V to 15V, the LTC3112 is well-
suited for a wide variety of single or multiple cell battery,
backup capacitor or wall adapter source applications. Low
RDS(ON) internal N-Channel MOSFET switches provide
highly efficient operation in applications with higher load
current requirements.
The LTC3112 features selectable PWM or Burst Mode
operation, an easily synchronized oscillator and output
disconnect in shutdown. An output current monitor circuit
allows the load current to be controlled or measured. Other
features include <1µA shutdown current, short circuit
protection, soft-start, current limit and thermal shutdown.
The LTC3112 is offered in both a 16-pin (4mm × 5mm ×
0.75mm) DFN and 20-pin TSSOP packages.
Efficiency at 5VOUT
FEATURES
APPLICATIONS
n Regulated Output with VIN Above, Below or Equal to VOUT
n 2.7V to 15V Input Voltage Range
n 2.5V to 14V Output Voltage Range
n 2.5A Continuous Output Current: VIN ≥ 5V,
VOUT = 5V, PWM Mode
n Output Current Monitor
n Up to 95% Efficiency
n 750kHz Switching Frequency, Synchronizable
Between 300kHz and 1.5MHz
n Internal N-Channel MOSFETs
n Selectable Burst Mode
®
Operation, IQ = 50µA
n Shutdown Current < 1µA
n Overvoltage Protection
n Output Disconnect in Shutdown
n Internal Soft-Start
n Small, Thermally Enhanced 16-Lead (4mm × 5mm ×
0.75mm) DFN and 20-Lead TSSOP Package
n 3.3V or 5V from 1, 2 or 3 Li-Ion, Backup Capacitor Stack
n Hand Held Inventory Terminals
n RF Transmitters
n 12V Synchronous Boost Converter
n Multiple Power Input Systems
n LED Lighting with Current Regulation
n 12V Lead Acid Battery to 12V
L, LT , LT C , LT M , Linear Technology Burst Mode, LTSpice and the Linear logo are registered
trademarks and No RSENSE and PowerPath are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178.
VIN
4.7µH
0.1µF 0.1µF
680pF
22pF
33k
845k
158k
47pF
47µF
F
10µF
10k
42.2k100pF
TO ADC
1V PER AMP
5V/2.5A, VIN > 5V
ONOFF
PWMBURST
2.7V TO 15V
SW1
BST1
VIN
VCC
RUN
GND
PWM/SYNC
SW2
BST2
VOUT
COMP
IOUT
OVP
FB
LTC3112
VOUT
3112 TA01 LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
100
70
80
50
60
90
30
40
0.01 10.1
3112 TA02
0.001
2.7VIN
5.0VIN
12VIN
PWM
BURST
5V, 750kHz Wide Input Voltage Range Buck-Boost Regulator
LTC31 12 3333333333 EEEEEEEEEE
LTC3112
2
3112fd
For more information www.linear.com/LTC3112
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN Voltage ................................................. 0.3V to 16V
VOUT Voltage .............................................. 0.3V to 15V
SW1 Voltage (Note 4) ................... 0.3V to (VIN + 0.3V)
SW2 Voltage (Note 4) ................ 0.3V to (VOUT + 0.3V)
VBST1 Voltage ...................(VSW1 – 0.3V) to (VSW1 + 6V)
VBST2 Voltage ...................(VSW2 0.3V) to (VSW2 + 6V)
(Notes 1, 3)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
PWM/SYNC
VCC
BST1
SW1
SW1
BST2
SW2
SW2
COMP
FB
OVP
VIN
VIN
RUN
IOUT
VOUT
TOP VIEW
DHD16 PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
TJMAX=150 °C, qJA = 43°C/W, qJC = 4°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
GND
COMP
FB
OVP
VIN
VIN
RUN
IOUT
VOUT
GND
GND
PWM/SYNC
VCC
BST1
SW1
SW1
BST2
SW2
SW2
GND
21
GND
TJMAX = 150°C, qJA = 38°C/W, qJC = 4°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3112EDHD#PBF LTC3112EDHD#TRPBF 3112 16-Lead (5mm × 4mm) Plastic DFN 40°C to 125°C
LTC3112IDHD#PBF LTC3112IDHD#TRPBF 3112 16-Lead (5mm × 4mm) Plastic DFN 40°C to 125°C
LTC3112HDHD#PBF LTC3112HDHD#TRPBF 3112 16-Lead (5mm × 4mm) Plastic DFN 40°C to 150°C
LTC3112MPDHD#PBF LTC3112MPDHD#TRPBF 3112 16-Lead (5mm × 4mm) Plastic DFN 55°C to 150°C
LTC3112EFE#PBF LTC3112EFE#TRPBF 3112FE 20-Lead Plastic TSSOP 40°C to 125°C
LTC3112IFE#PBF LTC3112IFE#TRPBF 3112FE 20-Lead Plastic TSSOP 40°C to 125°C
LTC3112HFE#PBF LTC3112HFE#TRPBF 3112FE 20-Lead Plastic TSSOP 40°C to 150°C
LTC3112MPFE#PBF LTC3112MPFE#TRPBF 3112FE 20-Lead Plastic TSSOP 55°C to 150°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LT C Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
RUN Voltage............................................... 0.3V to 16V
PWM/SYNC, VCC, IOUT Voltage ....................0.3V to 6V
FB, COMP, OVP Voltage ...............................0.3V to 6V
Operating Junction Temperature Range (Notes 2, 6)
............................................................... 55°C to 150°C
Storage Temperature Range ..................65°C to 150°C
Lead Temperature (Soldering, 10sec) TSSOP ....... 300°C
http://www.linear.com/product/LTC3112#orderinfo
LTC3112
LTC3112
3
3112fd
For more information www.linear.com/LTC3112
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = PWM/SYNC = RUN = 5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Operating Range 0°C to 150°C
–55°C to 0°C
2.7
2.85
15
15
V
V
VIN UVLO Threshold Rising 1.75 2.3 2.7 V
VIN UVLO Hysteresis 300 mV
VCC UVLO Threshold Rising l2.2 2.35 2.5 V
VCC UVLO Hysteresis 150 mV
Output Voltage Adjust Range l2.5 14 V
INTVCC Clamp Voltage VIN = 5V or 15V l3.8 4.2 4.6 V
VCC Voltage in Dropout VIN = 2.7V, IVCC = 10mA 2.6 V
Quiescent Current – Burst Mode Operation VFB = 1V, VPWM/SYNC = 0V 50 75 µA
Quiescent Current – Shutdown RUN = VOUT = VCC = 0V, Not Including Switch Leakage 0 1 µA
Feedback Voltage = PWM Mode Operation l0.778 0.8 0.818 V
Feedback Leakage VFB = 0.8V 0 50 nA
OVP Threshold Rising Threshold 0.78 0.83 0.88 V
OVP Hysteresis Measured at OVP Pin 20 mV
OVP Leakage OVP = 0.8V 0 100 nA
NMOS Switch Leakage Switch A, B, C, D, VIN = VOUT = 12V 1 10 µA
NMOS Switch On Resistance Switch A 40
NMOS Switch On Resistance Switch B, C 50
NMOS Switch On Resistance Switch D 60
Input Current Limit L = 4.7µH l4.5 6 8.5 A
Peak Current Limit L = 4.7µH 7 10 12 A
Burst Current Limit L = 4.7µH 0.7 1.3 2 A
Burst Zero Current Threshold L = 4.7µH 0.3 A
Reverse Current Limit L = 4.7µH –0.5 –1 –1.5 A
IOUT Accuracy (Note 5) SW2 to VOUT Current = 1.5A
SW2 to VOUT Current = 1.0A
SW2 to VOUT Current = 0.5A
32
20
8
36
24
12
40
28
16
µA
µA
µA
Maximum Duty Cycle Buck (Switch A On) l80 87 %
Boost (Switch C On) l75 82 %
Minimum Duty Cycle Buck (Switch A On) l0 %
Boost (Switch C On) l5 12 %
Frequency PWM/SYNC = 5V, VIN = VOUT = 12V l675 750 825 kHz
SYNC Frequency Range (Note 7) l300 1500 kHz
PWM/SYNC Threshold VCC = 2.7V or 5V l0.5 0.9 1.5 V
RUN Threshold VIN = 2.7V or 15V l0.35 0.75 1.5 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The LTC3112 is tested under pulsed load conditions such that TJTA.
The LTC3112E is guaranteed to meet specifications from 0°C to 85°C junction
temperature. Specifications over the 40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation with
statistical process controls. The LTC3112I is guaranteed to meet specifications
over the 40°C to 125°C operating junction temperature, the LTC3112H is
guaranteed to meet specifications over the 40°C to 150°C operating junction
temperature range and the LTC3112MP is guaranteed and tested to meet
specifications over the full 55°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes; operating
lifetime is derated for temperature greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
LTC3112 4N / __ L7HCU§QB
LTC3112
4
3112fd
For more information www.linear.com/LTC3112
TYPICAL PERFORMANCE CHARACTERISTICS
Wide VIN to 3.3VOUT Power Loss Wide VIN to 12VOUT Efficiency Wide VIN to 12VOUT Power Loss
Wide VIN to 5VOUT Efficiency Wide VIN to 5VOUT Power Loss Wide VIN to 3.3VOUT Efficiency
TA = 25°C, VIN = 5.0V, VOUT = 5.0V unless otherwise specified
ELECTRICAL CHARACTERISTICS
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
100
70
80
50
60
90
30
40
0.01 10.1
3112 G01a
0.001
PWM
BURST
2.7VIN
5.0VIN
12VIN
LOAD CURRENT (A)
0.0001
POWER LOSS (W)
1
0.01
0.1
0.0001
0.001
0.01 10.1
3112 G01b
0.001
2.7VIN LOSS
5.0VIN LOSS
12VIN LOSS
PWM
BURST
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
100
70
80
50
60
90
30
40
0.01 10.1
3112 G02a
0.001
PWM
BURST
2.7VIN
5.0VIN
12VIN
LOAD CURRENT (A)
0.0001
POWER LOSS (W)
1
0.01
0.1
0.0001
0.001
0.01 10.1
3112 G02b
0.001
2.7VIN LOSS
5.0VIN LOSS
12VIN LOSS
PWM
BURST
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
100
70
80
50
60
90
30
40
0.01 10.1
3112 G03a
0.001
PWM
BURST
3.6VIN
5.0VIN
12VIN
LOAD CURRENT (A)
0.0001
POWER LOSS (W)
1
0.01
0.1
0.0001
0.001
0.01 10.1
3112 G03b
0.001
3.6VIN LOSS
5.0VIN LOSS
12VIN LOSS
PWM
BURST
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: Voltage transients on the switch pins beyond the DC limit specified
in the Absolute Maximum Ratings, are non disruptive to normal operation
when using good layout practices, as shown on the demo board or
described in the data sheet and application notes.
Note 5: IOUT current is tested in a non-switching DC state. In a switching
environment IOUT accuracy may exhibit variation with factors such as
switching frequency, load current, input/output voltage, and temperature.
See typical performance characteristic curves for predicted variation.
Note 6: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PDqJA), where qJA (in °C/W) is the package thermal
impedance.
Note 7: SYNC frequency range is tested with a square wave. Operation
with 100ns minimum high or low times is assured by design.
LTC3112 // / ’ / / / ,I / // z / , // , .— / z x" ,’ " / , / “.— / r ,— L7LJDWEAB 5
LTC3112
5
3112fd
For more information www.linear.com/LTC3112
Maximum Output Current
PWM Mode
Maximum Output Current
Burst Mode Operation
12VIN to 12VOUT Efficiency
vs Frequency with 4.7µH
VIN (V)
2
MAXIMUM OUTPUT CURRENT (A)
3.2
4.0
4.8
1.6
2.4
0
0.8
4 6 7 8 9 10 11 12 13 14 155
3112 G04
3
3.3VOUT
5.0VOUT
12VOUT
VIN (V)
2
MAXIMUM OUTPUT CURRENT (mA)
320
400
480
560
160
240
0
80
4 6 7 8 9 10 11 12 13 14 155
3112 G05
3
3.3VOUT
5.0VOUT
12VOUT
LOAD CURRENT (mA)
0.01
EFFICIENCY (%)
70
80
90
100
50
60
30
40
0.1 1 10
3112 G06
500kHz
750KHz
1000kHz
1500kHz
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5.0V, VOUT = 5.0V unless otherwise specified
VCC Voltage vs VCC Current
Boost Mode Minimum SW1
Low Time vs VCC Voltage
Normalized N-Channel MOSFET
Resistance vs VCC
750kHz PWM Mode No-Load Input
Current
Burst Mode No-Load Input Current
with VCC from VIN or Back-Fed
from VOUT with Optional Diode
VCC Voltage vs VIN
PWM Mode No Load
VIN (V)
2
VIN CURRENT (mA)
20
25
10
15
0
5
4 6 7 8 9 10 11 12 13 14 155
3112 G07
3
VOUT = 5V
VIN (V)
3
CURRENT FROM VIN (µA)
250
300
350
150
200
0
50
100
5 7 9 11 13 15
3112 G08
VOUT = 5V VCC FROM VIN
VCC FROM VOUT
VIN (V)
2
VCC (V)
4.0
4.5
3.0
3.5
2.0
2.5
4 6 7 8 9 10 11 12 13 14 155
3112 G09
3
CURRENT FROM VCC (mA)
0
VCC (V)
4.3
4.4
4.1
4.2
3.9
4.0
20 40 60 80 100 120 140
3112 G10
VIN = 5V
VCC VOLTAGE (V)
2.5
MINIMUM SW1 LOW TIME (ns)
250
275
200
225
125
175
150
3.5 44.5 53
3112 G11 VCC (V)
2.5
NORMALIZED N-CHANNEL MOSFET RESISTANCE
1.2
1.3
0.9
1.0
1.1
0.7
0.8
3.5 3.75 44.25 4.5 4.75 52.75 33.25
3112 G12
LTC31 12 W— ""TTT " ' W" L7HCU§QB
LTC3112
6
3112fd
For more information www.linear.com/LTC3112
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5.0V, VOUT = 5.0V unless otherwise specified
IOUT Pin Current vs Temperature
1.5A Load Current IOUT Voltage vs VOUT Current
RUN and PWM/SYNC Threshold
Voltage vs Temperature
PWM Mode
ILIMIT, IPEAK, IREV vs Temperature
Burst Mode Operation
IPEAK, IZERO vs Temperature
IOUT Voltage vs VIN
Normalized N-Channel MOSFET
Resistance vs Temperature
Feedback Pin Program Voltage
vs Temperature VCC and VIN UVLO vs Temperature
TEMPERATURE (°C)
–60
NORMALIZED N-CHANNEL MOSFET RESISTANCE
1.2
1.3
1.4
0.9
1.0
1.1
0.7
0.8
20 40 60 80 100 120 140 160–40 –20 0
3112 G13 TEMPERATURE (°C)
FEEDBACK PROGRAMMED VOLTAGE (V)
0.800
0.805
0.810
0.815
0.820
0.825
0.785
0.790
0.795
0.775
0.780
3112 G14
–60 20 40 60 80 100 120 140 160–40 –20 0
TEMPERATURE (°C)
UNDERVOLTAGE LOCKOUT (V)
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
1.7
1.8
1.9
1.5
1.6
3112 G15
VIN FALLING
VIN RISING
VCC FALLING
VCC RISING
–60 20 40 60 80 100 120 140 160–40 –20 0
TEMPERATURE (°C)
THRESHOLD VOLTAGE (V)
0.9
1.0
1.1
1.2
0.6
0.7
0.8
0.4
0.5
3112 G16
RUN FALLING
RUN RISING
PWM/SYNC FALLING
PWM/SYNC RISING
–60 20 40 60 80 100 120 140 160–40 –20 0
TEMPERATURE (°C)
L = 4.7µH
CURRENT (A)
8
10
12
2
4
6
–2
0
3112 G17
IPEAK
ILIMIT
IREV
–60 20 40 60 80 100 120 140 160–40 –20 0
TEMPERATURE (°C)
CURRENT (A)
1.5
2.0
0.5
1.0
0
3112 G18
IZERO
IPEAK
L = 4.7µH
–60 20 40 60 80 100 120 140 160–40 –20 0
TEMPERATURE (°C)
IOUT PIN CURRENT (µA)
38
39
40
34
35
36
37
32
33
3112 G19
–60 20 40 60 80 100 120 140 160–40 –20 0
VOUT CURRENT (A)
0
IOUT VOLTAGE (mV)
2500
3000
3500
1000
1500
2000
0
500
1.5 22.5 33.50.5 1
3112 G20
VIN = 12V
VIN = 8V
VIN = 5V
VIN = 3V
RIOUT = 42.2k, CIOUT = 100pF,
VOUT = 5V, 750kHz
VIN (V)
2 3
IOUT VOLTAGE (mV)
1500
2000
2500
500
1000
08 97 10 11 12 13 14 154 5 6
3112 G21
IOUT = 2A
IOUT = 1.5A
IOUT = 1A
IOUT = 500mA
RIOUT = 42.2k, CIOUT = 100pF,
VOUT = 5V, 750kHz
LTC3112 m \\_ / . -_ _ _ _ _ // _ / __ _ _ _- 7.: / ’ \ \ \ . 4’ __--__--_ a .V . _ / 1’ ‘ ‘ ‘ .'..'.t.'..' / // — , 4, ’ __— \ ‘ \ m __ ,_ mm: m L7 HEW 7
LTC3112
7
3112fd
For more information www.linear.com/LTC3112
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5.0V, VOUT = 5.0V unless otherwise specified
IOUT Voltage vs VOUT
IOUT Voltage
vs VIN and Switching Frequency
3.3VOUT Die Temperature Rise
vs Continuous Load Current
4 Layer Demo Board at 25°C
VOUT (V)
2 3
IOUT VOLTAGE (mV)
1500
2000
2500
500
1000
08 97 10 11 12 13 144 5 6
3112 G22
IOUT = 2A
IOUT = 1.5A
IOUT = 1A
IOUT = 500mA
RIOUT = 42.2k, CIOUT = 100pF,
VIN = 7.5V, 750kHz
VIN (V)
2 3
IOUT VOLTAGE (mV)
1500
2000
2500
500
1000
08 97 10 11 12 13 14 154 5 6
3112 G23
2A, 1500kHz
2A, 750kHz
2A, 300kHz
1A, 1500kHz
1A, 750kHz
1A, 300kHz
RIOUT = 42.2k, CIOUT = 100pF,
VOUT = 5V, 750kHz
LOAD CURRENT (A)
0
TEMPERATURE RISE (°C)
30
40
50
60
10
20
00.5 11.5 42 2.5 33.5
3112 G24
VIN = 2.7V
VIN = 5V
VIN = 12V
5VOUT Die Temperature Rise
vs Continuous Load Current
4 Layer Demo Board at 25°C
12VOUT Die Temperature Rise
vs Continuous Load Current
4 Layer Demo Board at 25°C
LOAD CURRENT (A)
0
TEMPERATURE RISE (°C)
30
40
50
60
10
20
00.5 11.5 42 2.5 33.5
3112 G25
VIN = 2.7V
VIN = 5V
VIN = 12V
LOAD CURRENT (A)
0
TEMPERATURE RISE (°C)
30
40
50
60
10
20
00.5 11.5 42 2.5 33.5
3112 G26
VIN = 5V
VIN = 12V
3112 G27
VOUT
200mV/DIV
500µs/DIV
FRONT PAGE APPLICATION
INDUCTOR
CURRENT
1A/DIV
3112 G28
VOUT
200mV/DIV
500µs/DIV
FRONT PAGE APPLICATION
INDUCTOR
CURRENT
1A/DIV
3112 G29
VOUT
200mV/DIV
INDUCTOR
CURRENT
1A/DIV
500µs/DIV
FRONT PAGE APPLICATION
3VIN to 5VOUT
0.1A to 0.6A Load Step
5VIN to 5VOUT
0.1A to 1.0A Load Step
12VIN to 5VOUT
0.1A to 1.0A Load Step
5VIN to 5.0VOUT
Burst to PWM Waveforms,
3112 G30
VOUT
500mV/DIV
INDUCTOR
CURRENT
500mA/DIV
PWM/SYNC
5V/DIV
100µs/DIV
100mA LOAD
COUT = 47µF
LTC3112 WI” ff’ w" WWW \NNN H4" * H r] r ‘ ‘u w; My AVA/V AAA , _ 1 ‘H ~11 m ‘ “I'm ' ; \ mm:mmwunmm L7LJCUEN2
LTC3112
8
3112fd
For more information www.linear.com/LTC3112
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5.0V, VOUT = 5.0V unless otherwise specified
3112 G31
VOUT
100mV/DIV
INDUCTOR
CURRENT
500mA/DIV
20µs/DIV
100mA LOAD
COUT = 47µF
3112 G32
VOUT
50mV/DIV
INDUCTOR
CURRENT
1A/DIV
1µs/DIV
12.0VIN TO 5.0VOUT
1A LOAD COUT = 47µF
3112 G33
VIN
2V/DIV
VOUT
2V/DIV
INDUCTOR
CURRENT
1A/DIV
1ms/DIV
IL 1A/DIV
3112 G34
PWM/SYNC
5V/DIV
INDUCTOR
CURRENT
500mA/DIV
10µs/DIV
3112 G36
SW2
5V/DIV
SW1
5V/DIV
INDUCTOR
CURRENT
1A/DIV
500ns/DIV
ILOAD = 2A
750kHz
3112 G37
VOUT
2V/DIV
VOUT
SHORTED
INDUCTOR
CURRENT
5A/DIV
200µs/DIV
VIN = 5V
3112 G38
VCC
5V/DIV
VOUT
2V/DIV
INDUCTOR
CURRENT
1A/DIV
500µs/DIV
VCC
SHORTED
VOUT
SOFT-STARTS
12VIN to 5VOUT
Burst Mode Operation Waveforms PWM VOUT Ripple
7.5VIN to 5.0VOUT Soft-Start
Waveforms
1500kHz SYNC Signal Capture
and Release
12VIN to 5.0VOUT SW1
and SW2 Waveforms
VOUT Short Circuit Response VCC Short Circuit Recovery
LTC3112
LTC3112
9
3112fd
For more information www.linear.com/LTC3112
PIN FUNCTIONS
COMP (Pin 1/Pin 2): Error Amp Output. An R-C network
connected from this pin to FB sets the loop compensation
for the voltage converter.
FB (Pin 2/Pin 3): Feedback Voltage Input. Connect VOUT
resistor divider tap to this pin. The output voltage can
be adjusted from 2.5V to 14V by the following equation:
VOUT =0.8V 1+
R1
R2
where R1 is the resistor between VOUT and FB and R2 is
the resistor between FB and GND.
OVP (Pin 3/Pin 4): Overvoltage Protection Input. The
common point of a resistor divider between VOUT and GND
can also be used to program the overvoltage protection
to a lower voltage by the following equation:
VOVP =0.83V 1+R3
R4
where R3 is the resistor between VOUT and OVP and R4
is the resistor between OVP and GND.
VIN (Pins 4, 5/Pins 5, 6): Input Supply Voltage. This pin
should be bypassed to the ground plane with at least
10µF of low ESR, low ESL ceramic capacitance. Place this
capacitor as close to the pin as possible and have as short
a return path to the ground plane as possible.
RUN (Pin 6/Pin 7): Shutdown Control Input. Operation
will be disabled when the voltage is forced below 0.75V
(typical) and less thanA of quiescent current will be
consumed.
IOUT (Pin 7/Pin 8): A Current approximately 24µA/A of
the D Switch Output Current is Sourced from this Pin.
An R-C circuit can be used to control the average output
current or provide an analog output current monitor (see
Applications Information section).
VOUT (Pin 8/Pin 9): Regulated Output Voltage. This pin
should be connected to a low ESR ceramic capacitor of at
least 47µF. The capacitor should be placed as close to the
pin as possible and have a short return to the ground plane.
SW2 (Pins 9, 10/Pins 12, 13): Internal switches C and D
and the external inductor are connected here.
BST2 (Pin 11/Pin 14): Boosted Floating Driver Supply
for D-Switch Driver. Connect a 0.1µF capacitor from this
pin to SW2.
SW1 (Pins 12, 13/Pins 15, 16): Internal switches A and
B and the external inductor are connected here.
BST1 (Pin 14/Pin 17): Boosted Floating Driver Supply
for A-Switch Driver. Connect a 0.1µF capacitor from this
pin to SW1.
VCC (Pin 15/Pin 18): External Capacitor Connection for
the Regulated VCC Supply. This supply is used to operate
internal circuitry and switch drivers. VCC will track VIN up
to 4.2V, but will maintain this voltage when VIN > 4.2V.
Connect a 1µF ceramic capacitor from this pin to GND.
PWM/SYNC (Pin 16/Pin 19): Burst Mode Control and Syn-
chronization Input. A DC voltage <0.5V commands Burst
Mode operation, >1.5V commands 750kHz fixed frequency
mode. A digital pulse train between 300kHz and 1500kHz
applied to this pin will override the internal oscillator and
set the operating frequency. The pulse train should have
minimum high or low times greater than 100ns (Note 7).
Note the LTC3112 has reduced power capability when
operating in Burst Mode operation. Refer to the Operation
section of this data sheet for details.
GND (Exposed Pad Pin 17/Pins 1, 10, 11, 20, Exposed
Pad Pin 21): Ground. Small-Signal and Power Ground
for the IC. The exposed pad must be soldered to the PCB
and electrically connected to ground through the shortest
and lowest impedance connection possible. The bulk of
the heat flow is through this pad, so printed circuit board
design has an impact on the thermal performance of the
IC. See PCB Layout and Thermal Considerations sections
for more details.
(DFN/TSSOP)
LTC31 12 L7LJCUEN2 7 HH + _ 1.. . / m Hr : K % flulfiLc: HWHI. W 1.. I... .. alfalfa l_l E+% mmw. ‘IO
LTC3112
10
3112fd
For more information www.linear.com/LTC3112
BLOCK DIAGRAM
VCC VCC
VCC VCC
VCC
VCC
VCC
2.7V TO 15V
VIN
5V
VOUT
BST1
4.7µH
BST2
GND
FB
COMP
PWM/
SYNC
IOUT
SW1 SW2VIN VOUT
24µA/A
ADRV BDRV CDRV DDRV
DRIVERS
+
+
+
+
300mA
10A
6A
LOGIC
+
REVERSE ILIM
–1A
+
+
+
ONOFF
2.3V
A
B
D
C
+
+
ADRV
BDRV
DDRV
CDRV
0.9V
Burst Mode OPERATION
PLL 750kHz
OSCILLATOR
0.8V
SOFT-START
RAMP
IZERO
IPEAK
ILIMIT
GND
RUN
OVP
VCC VCC
VIN
OVERVOLTAGE
PROTECTION
4.2V
REGULATOR
/CLAMP
REFERENCE 1.2V
UVLO
LTC3112 L7 LJUW 1 1
LTC3112
11
3112fd
For more information www.linear.com/LTC3112
OPERATION
INTRODUCTION
The LTC3112 is an extended input and output range,
high current synchronous buck-boost DC/DC converter
optimized for a variety of demanding applications. The
LTC3112 utilizes a proprietary switching algorithm, which
allows its output voltage to be regulated above, below or
equal to the input voltage. The error amplifier output on
COMP determines the output duty cycle of the switches.
The low RDS(ON), low gate charge synchronous switches
provide high efficiency pulse width modulation control.
High efficiency is achieved at light loads when Burst Mode
operation is commanded.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator, Phase-Locked Loop
An internal oscillator circuit sets the normal frequency of
operation to 750kHz. A pulse train applied to the PWM/
SYNC pin allows the operating frequency to be programmed
between 300kHz to 1.5MHz via an internal phase-locked
loop circuit. The pulse train must have a minimum high or
low state of at least 100ns to guarantee operation (Note 7).
Error Amplifier
The error amplifier is a high gain voltage mode ampli-
fier. The loop compensation components are configured
around the amplifier (from FB to COMP and VOUT to FB)
to obtain stability of the converter and rapid response
to load transients. Refer to the Applications Information
section of this data sheet under Closing the Feedback
Loop for information on selecting compensation type
and components.
Current Limit Operation
The buck-boost converter has two current limit circuits.
The primary current limit is an average current limit circuit
which sources current into the feedback divider network
proportional to the extent that switch A current exceeds
6A typical. Due to the high gain of the feedback loop, the
injected current forces the error amplifier output to decrease
until the average current through switch A decreases ap-
proximately to the current limit value. The average cur-
rent limit utilizes the error amplifier in an active state and
thereby provides a smooth recovery with little overshoot
once the current limit fault condition is removed. Since
the current limit is based on the average current through
switch A, the peak inductor current in current limit will
have a dependency on the duty cycle (i.e. on the input
and output voltages) in the overcurrent condition. For this
current limit feature to be most effective, the Thevenin
resistance from the FB to ground should exceed 100kΩ.
The speed of the average current limit circuit is limited by
the dynamics of the error amplifier. On a hard output short,
it would be possible for the inductor current to increase
substantially beyond current limit before the average cur-
rent limit circuit would react. For this reason, there is a
second current limit circuit which turns off switch A if the
current ever exceeds approximately 160% of the average
current limit value. This provides additional protection in
the case of an instantaneous hard output short.
Should the output become shorted, the average current
limit is reduced to approximately one half of the normal
operating current limit.
Reverse Current Limit
During fixed frequency operation, a reverse current com-
parator on switch D monitors the current entering the
VOUT pin. When this reverse current exceeds 1A (typical)
switch D will be turned off for the remainder of the switch-
ing cycle. This feature protects the buck-boost converter
from excessive reverse current if the buck-boost output
is above the regulation voltage.
Internal Soft-Start
The LTC3112 buck-boost converter has an independent
internal soft-start circuit with a nominal duration of 2ms.
The converter remains in regulation during soft-start and
will therefore respond to output load transients which
occur during this time. In addition, the output voltage rise
time has minimal dependency on the size of the output
capacitor or load current during start-up.
LTC3112
LTC3112
12
3112fd
For more information www.linear.com/LTC3112
OPERATION
THERMAL CONSIDERATIONS
For the LTC3112 to provide maximum output power, it is
imperative that a good thermal path be provided to dis-
sipate the heat generated within the package. This can be
accomplished by taking advantage of the large thermal
pad on the underside of the IC. It is recommended that
multiple vias in the printed circuit board be used to conduct
the heat away from the IC and into a copper plane with as
much area as possible.
The efficiency and maximum output current capability of
the LTC3112 will be reduced if the converter is required to
continuously deliver large amounts of power or operate at
high ambient temperatures. The amount of output current
derating is dependent upon factors such as board ground
plane or heat sink area, ambient operating temperature,
and the input/output voltages of the application. A poor
thermal design can cause excessive heating, resulting in
impaired performance or reliability.
The temperature rise curves given in the Typical Perfor-
mance Characteristics section can be used as a general
guide to predict junction temperature rise from ambient.
These curves were generated by mounting the LTC3112
to the 4-layer FR4 Demo Board printed circuit board layout
shown in Figure 3. The curves were taken with the board
at room temperature, elevated ambient temperatures will
result in greater thermal rise rates due to increased initial
RDS(ON) of the N-Channel MOSFETs. The die temperature
of the LTC3112 should be kept below the maximum junc-
tion rating of 150°C.
In the event that the junction temperature gets too high
(approximately 150ºC), the current limit will be linearly
decreased from its typical value. If the junction temperature
continues to rise and exceeds approximately 170°C the
LTC3112 will be disabled. All power devices are turned off
and all switch nodes put to a high impedance state. The
soft-start circuit for the converter is reset during thermal
shutdown to provide a smooth recovery once the overtem-
perature condition is eliminated. When the die temperature
drops to approximately 160°C the LTC3112 will re-start.
UNDERVOLTAGE LOCKOUTS
The LTC3112 buck-boost converter is disabled and all
power devices are turned off until the VCC supply reaches
2.35V (typical). The soft-start circuit is reset during under-
voltage lockout to provide a smooth restart once the input
voltage rises above the undervoltage lockout threshold. A
second UVLO circuit disables all power devices if VIN is
below 2.3V rising, 2.0V falling (typical). This can provide
a lower VIN operating range in applications where VCC is
powered from an alternate source or VOUT after start-up.
INDUCTOR DAMPING
When the LTC3112 is disabled (RUN = 0V) or sleeping
during Burst Mode operation (PWM/SYNC = 0V), active
circuitsdamp” the inductor voltage through a 250Ω (typi-
cal) impedance from SW1 and SW2 to GND to minimize
ringing and reduce EMI.
PWM MODE OPERATION
When the PWM/SYNC pin is held high, the LTC3112 buck-
boost converter operates in a fixed frequency pulse width
modulation (PWM) mode using voltage mode control. Full
output current capability is only available in PWM mode. A
proprietary switching algorithm allows the converter to tran-
sition between buck, buck-boost, and boost modes without
discontinuity in inductor current. The switch topology for
the buck-boost converter is shown in Figure 1.
VIN VOUT
A
L
B
D
C
3112 F01
Figure 1. Buck-Boost Switch Topology
When the input voltage is significantly greater than the
output voltage, the buck-boost converter operates in buck
mode. Switch D turns on at maximum duty cycle and switch
C turns on just long enough to refresh the voltage on the
BST2 capacitor used to drive switch D. Switches A and B
LTC3112 0.5 vIN L7HEJWEGR 1 3
LTC3112
13
3112fd
For more information www.linear.com/LTC3112
are pulse width modulated to produce the required duty
cycle to support the output regulation voltage.
As the input voltage nears the output voltage, switches
A and D are on for a greater portion of the switching
period, providing a direct current path from VIN to VOUT.
Switches B and C are turned on only enough to ensure
proper regulation and/or provide charging of the BST1
and BST2 capacitors. The internal control circuitry will
determine the proper duty cycle in all modes of operation,
which will vary with load current.
As the input voltage drops well below the output voltage,
the converter operates solely in boost mode. Switch A turns
on at maximum duty cycle and switch B turns on just long
enough to refresh the voltage on the BST1 capacitor used
to drive A. Switches C and D are pulse width modulated to
produce the required duty cycle to regulate the output voltage.
This switching algorithm provides a seamless transition
between operating modes and eliminates discontinuities
in average inductor current, inductor current ripple, and
loop transfer function throughout the operational modes.
These advantages result in increased efficiency and stab-
ility in comparison to the traditional 4-switch buck-boost
converter.
Powering VCC from an External Source
The LTC3112’s VCC regulator can be powered or back-fed
from an external source up to 5.5V. Advantages of back-
feeding VCC from a voltage above 4.2V include higher
efficiency and improved maximum duty cycle at lower
input voltages. These advantages are shown in the Typical
Performance Characteristics curvesMOSFET Resistance
vs VCC” andMinimum SW1 Low Times.” For 5VOUT ap-
plications, VCC can be easily powered from VOUT using an
external low current Schottky diode as shown in several
applications circuits in the Typical Applications section.
Back-feeding VCC also improves a light load PWM mode
output voltage ripple that occurs when the inductor passes
through zero current. Back-feeding VCC reduces the switch
pin anti-cross conduction times, minimizing the VOUT
ripple during this light-load condition. One disadvantage
of powering VCC from VOUT is that no-load quiescent
current increases at low VIN in Burst Mode operation as
OPERATION
shown in the Typical Performance Characteristics curves
(compared to VCC powered from VIN).
Considerations for Boost Applications
In boost mode, the maximum output current that can be
supported at higher VOUT/VIN ratios is reduced. This ef-
fect is illustrated in the Maximum Output Current PWM
Mode curves in the Typical Performance Characteristics
section. For example at 12VOUT, the LTC3112 needs VIN >
4V to support 1A. As described previously, powering VCC
from a 5V source (if available) can improve output current
capabilities at low input voltages.
At even lower input voltages (below 3.6V for 12VOUT), the
LTC3112 can run into duty cycle limitations. This occurs
since SW1 and SW2 maximum duty cycles are multiplied,
giving an approximate 70% maximum duty cycle at the
nominal 750kHz switching frequency. Reducing the switch-
ing frequency with the PWM/SYNC pin will increase the
maximum duty cycle, allowing a higher boost ratio to be
achieved. Do not attempt operating the LTC3112 beyond
the duty cycle limitations described as this may result in
unstable operation.
Burst Mode OPERATION
When the PWM/SYNC pin is held low, the buck-boost
converter operates utilizing a variable frequency switch-
ing algorithm designed to improve efficiency at light load
and reduce the standby current at zero load. In Burst
Mode operation, the inductor is charged with fixed peak
amplitude current pulses and as a result only a fraction
of the maximum output current can be delivered when in
Burst Mode operation.
These current pulses are repeated as often as necessary
to maintain the output regulation voltage. The maximum
output current, IMAX, which can be supplied in Burst Mode
operation is dependent upon the input and output voltage
as approximated by the following formula:
IMAX =
IN
V
+V
(A)
If the buck-boost load exceeds the maximum Burst Mode
current capability, the output rail will lose regulation. In
LTC3112 mm “NM
LTC3112
14
3112fd
For more information www.linear.com/LTC3112
The basic LTC3112 application circuit is shown on the front
page of this data sheet. The external component selection
is dependent upon the required performance of the IC in
each particular application given trade-offs such as PCB
area, output voltages, output currents, ripple voltages
and efficiency. This section of the data sheet provides
some basic guidelines and considerations to aid in the
selection of external components and the design of the
application circuit.
VOUT AND OVP PROGRAMMING
The buck-boost output voltage is set with an external resis-
tor divider connected to the FB pin as shown in Figure 2.
The resistor divider values determine the buck-boost output
voltage according to the following formula:
APPLICATIONS INFORMATION
VOUT
2.5V < VOUT < 14V
R3
R4
R1
R2
C1 LTC3112
GND
OVP FB
3112 F02
Figure 2. Setting the Output Voltage
VOUT =0.8V 1+
R1
R2
If accurate overvoltage protection is required, a second
resistor divider (R3 and R4) may be connected to the OVP
pin to program the overvoltage protection threshold where
the LTC3112 will stop switching.
VOVP =0.83V 1+R3
R4
A small capacitor, C1, in parallel with R4 may be needed
to provide filtering to prevent nuisance trips during a load
step. A soft-start cycle will be initiated if an overvoltage
event occurs.
INDUCTOR SELECTION
To achieve high efficiency, a low ESR inductor should be
utilized for the buck-boost converter. In addition, the buck-
boost inductor must have a saturation current rating that
is greater than the worst case average inductor current
plus half the ripple current. The peak-to-peak inductor
current ripple for buck or boost mode operation can be
calculated from the following formulas:
IL,PP, BUCK =VOUT
fL
V
IN VOUT
V
IN
A
IL,PP, BOOST=V
IN
fL
VOUT V
IN
VOUT
A
OPERATION
Burst Mode operation, the error amplifier is configured for
low power operation and used to hold the compensation
pin COMP, to reduce transients that may occur during
transitions from and to burst and PWM mode.
OUTPUT CURRENT MONITOR
The LTC3112 includes a circuit that sources an approximate
24µA/A current replica of the VOUT (or SWD) current. This
current is typically passed through a resistor from IOUT
to GND and filtered to produce a DC voltage proportional
to average load current. This voltage can be monitored
by an A/D converter to track load conditions. The IOUT
pin voltage can also control LTC3112’s feedback loop to
regulate IOUT current instead of VOUT voltage. The accuracy
of the IOUT replica depends on factors such as duty cycle,
VIN and VOUT voltages, operating frequency etc. The IOUT
pin’s DC voltage must be less than VCC - 1V to provide an
accurate representation of output current.
LTC3112 L7Hߤ0g 1 5
LTC3112
15
3112fd
For more information www.linear.com/LTC3112
APPLICATIONS INFORMATION
Where f is the switching frequency in Hz and L is the
inductor value in Henries.
In addition to affecting output current ripple, the size of the
inductor can also impact the stability of the feedback loop.
In boost mode, the converter transfer function has a right
half plane zero at a frequency that is inversely proportional
to the value of the inductor. As a result, a large inductor
can move this zero to a frequency that is low enough to
degrade the phase margin of the feedback loop. It is rec-
ommended that the inductor value be chosen less than
15μH if the converter is to be used in the boost region.
For 750kHz operation, a 4.7µH inductor is recommended
for 5VOUT and a 10µH inductor for 12VOUT.
The inductor DC resistance can impact the efficiency of
the buck-boost converter as well as the maximum output
current capability at low input voltage. In buck mode,
the output current is limited only by the inductor current
reaching the current limit value. However, in boost mode,
especially at large step-up ratios, the output current capa-
bility can also be limited by the total resistive losses in the
power stage. These include switch resistances, inductor
resistance, and PCB trace resistance. Use of an inductor
with high DC resistance can degrade the output current
capability from that shown in the graph in the Typical
Performance Characteristics section of this data sheet.
Different inductor core materials and styles have an impact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizes the chances of interference with other circuitry.
The choice of inductor style depends upon the price, sizing,
and EMI requirements of a particular application. Table 1
provides a small sampling of inductors that are well suited
to many LTC3112 buck-boost converter applications. All
inductor specifications are listed at an inductance value
of 4.7µH for comparison purposes but other values within
these inductor families are generally well suited to this
application. Within each family (i.e. at a fixed size), the DC
resistance generally increases and the maximum current
generally decreases with increased inductance.
Table 1. Representative Buck-Boost Surface Mount Inductors
PART NUMBER
VALUE
(µH)
DCR
(mΩ)
MAX I
(A)
SIZE (mm)
W × L × H
Coilcraft XPL7030-472ML 4.7 40.1 6.8 7 × 7 × 3
Coilcraft MSS1048-472NLB 4.7 12.3 6.46 10 × 10 × 4.8
Würth 744 311 470 4.7 24 6 7 × 6.9 × 3.8
Cooper Bussmann HC8-4R5-R 4.5 18.6 7.7 10.9 × 10.4 × 4
OUTPUT CAPACITOR SELECTION
A low-ESR output capacitor should be utilized at the buck-
boost converter output in order to minimize output volt-
age ripple. Multilayer ceramic capacitors are an excellent
choice as they have low ESR and are available in small
footprints. The capacitor should be chosen large enough
to reduce the output voltage ripple to acceptable levels.
The minimum output capacitor needed for a given output
voltage ripple (neglecting ESR and ESL) can be calculated
by the following formulas:
COUT =1
∆ V
PP, BUCK 8Lf2
V
IN
V
OUT
( )
V
OUT
V
IN
COUT =ILOAD VOUT V
IN
( )
∆ V
PP, BOOST VOUT f
where f is the frequency in MHz, COUT is the capacitance
in μF, L is the inductance in μH, and ILOAD is the output
current in Amps.
Given that the output current is discontinuous in boost
mode, the ripple in this mode will generally be much
larger than the magnitude of the ripple in buck mode. For
most applications a 47µF or greater output capacitor is
recommended.
INPUT CAPACITOR SELECTION
It is recommended that a low ESR ceramic capacitor with
a value of at least 10μF be located as close to the VIN and
GND pins as possible. In addition, the return trace from
each pin to the ground plane should be made as short
as possible. For instances where the input source, such
as a bench supply, is far away from the converter, a bulk
capacitor of 100µF or greater is suggested to provide a
low ripple input voltage especially in buck mode.
LTC31 12 16
LTC3112
16
3112fd
For more information www.linear.com/LTC3112
CAPACITOR VENDOR INFORMATION
Both the input bypass capacitors and output capacitors
used with the LTC3112 must be low ESR and designed
to handle the large AC currents generated by switching
converters. This is important to maintain proper functioning
of the IC and to reduce ripple on both the input and output.
Many modern low voltage ceramic capacitors experience
significant loss in capacitance from their rated value with
increased DC bias voltages. For example, it is not uncom-
mon for a small surface mount ceramic capacitor to lose
50% or more of its rated capacitance when operated near
its rated voltage. As a result, it is sometimes necessary to
use a larger value capacitance or a capacitor with a higher
voltage rating then required in order to actually realize
the intended capacitance at the full operating voltage. For
details, consult the capacitor vendor’s curve of capacitance
versus DC bias voltage.
The capacitors listed in Table 2 provide a sampling of small
surface mount ceramic capacitors that are well suited to
LTC3112 application circuits. All listed capacitors are either
X5R or X7R dielectric in order to ensure that capacitance
loss overtemperature is minimized.
Table 2. Representative Bypass and Output Capacitors
PART NUMBER
VALUE
(µF)
VOLTAGE
(V)
SIZE (mm)
L × W × H
AVX LD103D226MAB2A 22 25 3.2 × 2.5 × 2.79
Kemet C1210C476M4PAC7025 47 16 3.2 × 2.5 × 2.5
Murata GRM32ER61E226KE15L 22 25 3.6 × 2.5 × 2.5
Taiyo Yuden EMK325BJ476MM-T 47 16 3.2 × 2.5 × 2.5
TDK C5750X5RIC476M 47 16 5.7 × 5 × 2.3
PCB LAYOUT CONSIDERATIONS
The LTC3112 switches large currents at high frequencies.
Special attention should be paid to the PCB layout to ensure
a stable, noise-free and efficient application circuit. Figure 3
presents a representative 4-layer PCB layout to outline
some of the primary considerations. A few key guidelines
are outlined below:
1. A 4-layer board is highly recommended for the LTC3112
to ensure stable performance over the full operating
voltage and current range. A dedicated/solid ground
APPLICATIONS INFORMATION
plane should be placed directly under the VIN, VOUT,
SW1 and SW2 traces to provide a mirror plane to
minimize noise loops from high dI/dt and dV/dt edges
(see Figure 3, 2nd layer).
2. All circulating high current paths should be kept as
short as possible. Capacitor ground connections
should via down to the ground plane in the shortest
route possible. The bypass capacitors on VIN should be
placed as close to the IC as possible and should have
the shortest possible paths to ground (see Figure 3,
top layer).
3. The exposed pad is the power ground connection for
the LTC3112. Multiple vias should connect the back
pad directly to the ground plane. In addition maximi-
zation of the metallization connected to the back pad
will improve the thermal environment and improve
the power handling capabilities of the IC.
4. The high current components and their connections
should all be placed over a complete ground plane to
minimize loop cross-sectional areas. This minimizes
EMI and reduces inductive drops.
5. Connections to all of the high current components
should be made as wide as possible to reduce the
series resistance. This will improve efficiency and
maximize the output current capability of the buck-
boost converter.
6. To prevent large circulating currents from disrupting
the output voltage sensing, the ground for each resistor
divider should be returned to the ground plane using
a via placed close to the IC and away from the power
connections.
7. Keep the connection from the resistor dividers to the
feedback pins FB as short as possible and away from
the switch pin connections.
8. Crossover connections should be made on inner cop-
per layers if available. If it is necessary to place these
on the ground plane, make the trace on the ground
plane as short as possible to minimize the disruption
to the ground plane (see Figure 3, 3rd layer).
LTC3112
17
3112fd
For more information www.linear.com/LTC3112
APPLICATIONS INFORMATION
CIN
COUT
L
Figure 3. Example PCB Layout
Top Layer 2nd Layer
3rd Layer Bottom Layer (Top View)
18 LTC31 12 2V\NR _ R+ RS _ L LC0(R+Rc) Lc0 E R L7LJCUEN2
LTC3112
18
3112fd
For more information www.linear.com/LTC3112
APPLICATIONS INFORMATION
Buck Mode Small Signal Model
The LTC3112 uses a voltage mode control loop to main-
tain regulation of the output voltage. An externally com-
pensated error amplifier drives the COMP pin to generate
the appropriate duty cycle of the power switches. Use of
an external compensation network provides the flexibility
for optimization of closed loop performance over the wide
variety of output voltages, switching frequencies, and
external component values supported by the LTC3112.
The small signal transfer function of the buck-boost con-
verter is different in the buck and boost modes of opera-
tion and care must be taken to ensure stability in both
operating regions. When stepping down from a higher
input voltage to a lower output voltage, the converter
will operate in buck mode and the small signal transfer
function from the error amplifier output, VCOMP, to the
converter output voltage is given by the following equation.
VO
VCOMP BUCK MODE
=GBUCK
1+s
2πfZ
1+s
2πfOQ+s
2πfO
2
The gain term, GBUCK, is comprised of two different com-
ponents: the gain of the pulse width modulator and the gain
of the power stage as given by the following expressions
where VIN is the input voltage to the converter in volts, f
is the switching frequency in Hz, R is the load resistance
in ohms, and tLOW is the switch pin minimum low time.
A curve showing the switch pin minimum low time can
be found in the Typical Performance Characteristics sec-
tion of this data sheet. The parameter RS represents the
average series resistance of the power stage and can be
approximated as twice the average power switch resistance
plus the DC resistance of the inductor.
G
BUCK =
G
PWM
G
POWER
GPWM =2 1– tLOWf
( )
GPOWER =V
INR
1– tLOWf
( )
R+RS
( )
The buck mode gain is well approximated by the follow-
ing equation.
GBUCK =
2
V
IN
R
R+RS
2V
IN
The buck mode transfer function has a single zero which
is generated by the ESR of the output capacitor. The zero
frequency, fZ, is given by the following expression where
RC and CO are the ESR (in ohms) and value (in farads) of
the output filter capacitor respectively.
fZ=
1
2πR
C
C
O
In most applications, an output capacitor with a very low
ESR is utilized in order to reduce the output voltage rip-
ple to acceptable levels. Such low values of capacitor ESR
result in a very high frequency zero and as a result the
zero is commonly too high in frequency to significantly
impact compensation of the feedback loop.
The denominator of the buck mode transfer function ex-
hibits a pair of resonant poles generated by the LC filtering
of the power stage. The resonant frequency of the power
stage, fO, is given by the following expression where L is
the value of the inductor in henries.
fO=1
2π
R+RS
LCOR+RC
( )
1
2π
1
LCO
The quality factor, Q, has a significant impact on com-
pensation of the voltage loop since a higher Q factor
produces a sharper loss of phase near the resonant
frequency. The quality factor is inversely related to the
amount of damping in the power stage and is substantially
influenced by the average series resistance of the power
stage, RS. Lower values of RS will increase the Q and result
in a sharper loss of phase near the resonant frequency
and will require more phase boost or lower bandwidth to
maintain an adequate phase margin.
Q=LCOR+RC
( )
R+RS
( )
RRCCO+L+CORSR+RC
( )
LCO
L
R
+CORS
LTC3112 V0 K f2M fRHPZ) \Z LCOR(RS+ RV'N ] VOUT VOUT Z'Vom (1 tLow ) Vw L7HEJWEGR 1 9
LTC3112
19
3112fd
For more information www.linear.com/LTC3112
APPLICATIONS INFORMATION
Boost Mode Small Signal Model
When stepping up from a lower input voltage to a higher
output voltage, the buck-boost converter will operate in
boost mode where the small signal transfer function from
control voltage, VCOMP, to the output voltage is given by
the following expression.
VO
VCOMP BOOST MODE
=GBOOST
1+s
2πfZ
1s
2πfRHPZ
1+s
2πf
OQ+s
2πf
O
2
In boost mode operation, the transfer function is character-
ized by a pair of resonant poles and a zero generated by
the ESR of the output capacitor as in buck mode. However,
in addition there is a right half plane zero which generates
increasing gain and decreasing phase at higher frequen-
cies. As a result, the crossover frequency in boost mode
operation generally must be set lower than in buck mode
in order to maintain sufficient phase margin.
The boost mode gain, GBOOST, is comprised of two com-
ponents: the pulse width modulator and the power stage.
The gain of the power stage in boost mode is given by the
following equation.
GPOWER
V
OUT
2
1– tLOW f
( )
V
IN
By combining the individual terms, the total gain in boost
mode can be reduced to the following expression. Notice
that unlike in buck mode, the gain in boost mode is a
function of both the input and output voltage.
GBOOST
2
V
OUT2
V
IN
In boost mode operation, the frequency of the right half
plane zero, fZ, is given by the following expression. The
frequency of the right half plane zero decreases at higher
loads and with larger inductors.
fRHPZ =R 1tLOW f
( )
2V
IN2
2πL VOUT2
In boost mode, the resonant frequency of the power stage
has a dependence on the input and output voltage as shown
by the following equation.
fO=1
2π
RS+RV
IN2
VOUT2
LCOR+RC
( )
1
2πV
IN
VOUT
1
LC
Finally, the magnitude of the quality factor of the power
stage in boost mode operation is given by the following
expression.
Q=
LCOR RS+RVIN2
VOUT2
L+C
O
R
S
R
Compensation of the Voltage Loop
The small signal models of the LTC3112 reveal that the
transfer function from the error amplifier output, VCOMP,
to the output voltage is characterized by a set of resonant
poles and a possible zero generated by the ESR of the
output capacitor as shown in the Bode plot of Figure 4.
In boost mode operation, there is an additional right half
plane zero that produces phase lag and increasing gain at
higher freq uencies. Typically, the compensation network is
designed to ensure that the loop crossover frequency is low
enough that the phase loss from the right half plane zero
is minimized. The low frequency gain in buck mode is a
constant, but varies with both VIN and VOUT in boost mode.
Figure 4. Buck-Boost Converter Bode Plot
GAIN
PHASE
BOOST MODE
BUCK MODE
–20dB/DEC
–40dB/DEC
fO
f
3112 F06
fRHPZ
–90°
–180°
–270°
LTC31 12 Gm N F2] 7 7 72m A, T Mow __ _‘ VCOMP \ fZERm/K fZERoz/ "I I‘M 7 7 Cm 20 L7ELUEN2
LTC3112
20
3112fd
For more information www.linear.com/LTC3112
For charging, LED lighting, or other applications that do not
require an optimized output voltage transient re-sponse, a
simple Type I compensation network as shown in Figure
5 can be used to stabilize the voltage loop. To ensure suf-
ficient phase margin, the gain of the error am-plifier must
be low enough that the resultant crossover frequency of
the control loop is well below the resonant frequency.
+
C1
GND
LTC3112
VCOMP
3112 F05
FB
VOUT
RBOT
RTOP 0.8V
In most applications, the low bandwidth of the Type I com-
pensated loop will not provide sufficient transient response
performance. To obtain a wider bandwidth feedback loop,
optimize the transient response, and minimize the size of
the output capacitor, a Type III com-pensation network
as shown in Figure 6 is required.
Figure 5. Error Amplifier with Type I Compensation
CFB RFB
GND
LTC3112
VCOMP
3112 F06
FB
VOUT
RBOT
RTOP
RFF
CFF 0.8V
CPOLE
+
Figure 6. Error Amplifier with Type III Compensation
A Bode plot of the typical Type III compensation network
is shown in Figure 7. The Type III compensation network
provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady state error in the
regulation voltage. Tw o zeros located at fZERO1 and fZERO2
provide sufficient phase boost to allow the loop crossover
frequency to be set above the resonant frequency, fO, of
the power stage. The Type III compensation network also
introduces a second and third pole. The second pole, at
frequency fPOLE2, reduces the error amplifier gain to a
zero slope to prevent the loop crossover from extending
too high in frequency. The third pole at frequency fPOLE3
provides attenuation of high frequency switching noise.
APPLICATIONS INFORMATION
fZERO1
PHASE
90°
–90°
GAIN
–20dB/DEC
–20dB/DEC
fZERO2
3112 F07
f
fPOLE2 fPOLE3
Figure 7. Type III Compensation Bode Plot.
The transfer function of the compensated Type III error
amplifier from the input of the resistor divider to the output
of the error amplifier, VCOMP, is:
VCOMP(s)
VOUT(s) =GEA
1+s
2πfZERO1
1+s
2πfZERO2
s 1+s
2πfPOLE1
1+s
2πfPOLE2
The error amplifier gain is given by the following equation.
The simpler approximate value is sufficiently accurate in
most cases since CFB is typically much larger in value
than CPOLE.
GEA =
1
RTOP CFB +CPOLE
( )
1
RTOPCFB
The pole and zero frequencies of the Type III compensation
network can be calculated from the following equations
where all frequencies are in Hz, resistances are in ohms,
and capacitances are in farads.
LTC3112 CFB CPOLE _:[>r~n_—> __L_ 21
LTC3112
21
3112fd
For more information www.linear.com/LTC3112
fZERO1 =
1
2πRFBCFB
fZERO2 =1
2πRTOP +RFF
( )
CFF
1
2πRTOPCFF
fPOLE2 =CFB +CPOLE
2πCFBCPOLERFB
1
2πCPOLERFB
fPOLE3 =1
2πCFF RFF
In most applications the compensation network is de-
signed so that the loop crossover frequency is above the
resonant frequency of the power stage, but sufficiently
below the boost mode right half plane zero to minimize
the additional phase loss. Once the crossover frequency
is decided upon, the phase boost provided by the com-
pensation network is centered at that point in order
to maximize the phase margin. A larger separation in
frequency between the zeros and higher order poles will
provide a higher peak phase boost but may also increase
the gain of the error amplifier which can push out the loop
crossover to a higher frequency.
The Q of the power stage can have a significant influence
on the design of the compensation network because it
determines how rapidly the 180° of phase loss in the power
stage occurs. For very low values of series resistance, RS,
the Q will be higher and the phase loss will occur sharply.
In such cases, the phase of the power stage will fall rapidly
to –180° above the resonant frequency and the total phase
margin must be provided by the compensation network.
However, with higher losses in the power stage (larger
RS) the Q factor will be lower and the phase loss will occur
more gradually. As a result, the power stage phase will
not be as close to –180° at the crossover frequency and
less phase boost is required of the compensation network.
The LTC3112 error amplifier is designed to have a fixed
maximum bandwidth in order to provide rejection of
switching noise to prevent it from interfering with the
control loop. From a frequency domain perspective, this
can be viewed as an additional single pole as illustrated
in Figure 8. The nominal frequency of this pole is 400kHz.
For typical loop crossover frequencies below about 60kHz
APPLICATIONS INFORMATION
the phase contributed by this additional pole is negligible.
However, for loops with higher crossover frequencies this
additional phase loss should be taken into account when
designing the compensation network.
Figure 8. Internal Loop Filter.
+
0.8V
FB
LTC3112
VCOMP
RFILT
CFILT
3112 F08
INTERNAL
VCOMP
Loop Compensation Example
This section provides an example illustrating the design
of a compensation network for a typical LTC3112 applica-
tion circuit. In this example a 5V regulated output voltage
is generated with the ability to supply a 1A load from an
input power source ranging from 3.5V to 15V. The nominal
750kHz switching frequency has been chosen. In this ap-
plication the maximum inductor current ripple will occur
at the highest input voltage. An inductor value of 4.7µH
has been chosen to limit the worst case inductor current
ripple to approximately 1A. A low ESR output capacitor
with a value of 47µF is specified to yield a worst case
output voltage ripple (occurring at the worst case step-up
ratio and maximum load current) of approximately 10mV.
In summary, the key power stage specifications for this
LTC3112 example application are given below.
f = 0.75MHz, tLOW = 0.2µs
VIN = 3.5V to 15V
VOUT = 5V at 1A
COUT = 47µF, RC = 5mΩ
L = 4.7µH, RL = 50mΩ
With the power stage parameters specified, the compen-
sation network can be designed. In most applications,
the most challenging compensation corner is boost
mode operation at the greatest step-up ratio and highest
load current since this generates the lowest frequency
right half plane zero and results in the greatest phase
loss. Therefore, a reasonable approach is to design the
compensation network at this worst case corner and
LTC31 12 I {GAIN I PHASE : I I L7LJCUEN2
LTC3112
22
3112fd
For more information www.linear.com/LTC3112
then verify that sufficient phase margin exists across all
other operating conditions. In this example application, at
VIN = 3.5V and the full 1A load current, the right half plane
zero will be located at 60kHz and this will be a dominant
factor in determining the bandwidth of the control loop.
The first step in designing the compensation network is
to determine the target crossover frequency for the com-
pensated loop. A reasonable starting point is to assume
that the compensation network will generate a peak phase
boost of approximately 60°. Therefore, in order to obtain
a phase margin of 60°, the loop crossover frequency, fC,
should be selected as the frequency at which the phase
of the buck-boost converter reaches −180°. As a result,
at the loop crossover frequency the total phase will be
simply the 60° of phase provided by the error amplifier
as shown below.
Phase Margin = fBUCK-BOOST + fERRORAMPLIFIER + 180°
= –180° + 60° + 180° = 60°
Similarly, if a phase margin of 45° is required, the target
crossover frequency should be picked as the frequency
at which the buck-boost converter phase reaches −195°
so that the combined phase at the crossover frequency
yields the desired 45° of phase margin.
This example will be designed for a 60° phase margin to
ensure adequate performance over parametric variations
and varying operating conditions. As a result, the target
crossover frequency, fC, will be the point at which the phase
of the buck-boost converter reaches −180°. It is generally
difficult to determine this frequency analytically given that
it is significantly impacted by the Q factor of the resonance
in the power stage. As a result, it is best determined from a
Bode plot of the buck-boost converter as shown in Figure 9.
This Bode plot is for the LTC3112 buck-boost converter
using the previously specified power stage parameters
and was generated from the small signal model equations
using LTSpice
®
. In this case, the phase reaches −180° at
35kHz making fC = 35kHz the target crossover frequency
for the compensated loop.
From the Bode plot of Figure 9 the gain of the power stage
at the target crossover frequency is 7dB. Therefore, in
order to make this frequency the crossover frequency
in the compensated loop, the total loop gain at fC must
be adjusted to 0dB. To achieve this, the gain of the com-
pensation network must be designed to be –7dB at the
crossover frequency.
At this point in the design process, there are three con-
straints that have been established for the compensation
network. It must have −7dB gain at fC
= 35kHz, a peak phase
boost of 60° and the phase boost must be centered at
fC = 35kHz. One way to design a compensation network to
meet these targets is to simulate the compensated error
amplifier Bode plot in LTSpice for the typical compensation
network shown on the front page of this data sheet. Then,
the gain, pole frequencies and zero frequencies can be
iteratively adjusted until the required constraints are met.
Alternatively, an analytical approach can be used to design
a compensation network with the desired phase boost,
center frequency and gain. In general, this procedure can
be cumbersome due to the large number of degrees of
freedom in a Type III compensation network. However the
design process can be simplified by assuming that both
compensation zeros occur at the same frequency, fZ, and
Figure 9. Converter Bode Plot, VIN = 3.5V, ILOAD = 1A
FREQUENCY (Hz)
10
GAIN (dB)
PHASE (DEG)
–150
–100
–50
0
10k 1M
3112 F09
–200
–250 100 1k 100k
50
–150
–100
–50
0
–200
–250
50
PHASE
fC
GAIN
APPLICATIONS INFORMATION
LTC3112 fr: 3 Z fP E M m ( )( 9) *7 L7HEJWEGR 23
LTC3112
23
3112fd
For more information www.linear.com/LTC3112
both higher order poles (fPOLE2 and fPOLE3) occur at the
common frequency, fP. In most cases this is a reasonable
assumption since the zeros are typically located between
1kHz and 10kHz and the poles are typically located near
each other at much higher frequencies. Given this as-
sumption, the maximum phase boost, fMAX, provided by
the compensated error amplifier is determined simply by
the amount of separation between the poles and zeros as
shown by the following equation.
fMAX =4tan1 fP
fZ
– 270°
A reasonable choice is to pick the frequency of the poles,
fP, to be about 50 times higher than the frequency of the
zeros, fZ, which provides a peak phase boost of approxi-
mately fMAX = 60° as was assumed previously. Next, the
phase boost must be centered so that the peak phase
occurs at the target crossover frequency. The frequency
of the maximum phase boost, fCENTER, is the geometric
mean of the pole and zero frequencies as shown below.
fCENTER =fPfZ=50 fZ7fZ
Therefore, in order to center the phase boost given a factor
of 50 separation between the pole and zero frequencies,
the zeros should be located at one seventh of the cross-
over frequency and the poles should be located at seven
times the crossover frequency as given by the fol lowing
equations.
fZ=
1
7fC=
1
735kHz
( )
=5kHz
fP=7fC=7 35kHz
( )
=250kHz
This placement of the poles and zeros will yield a peak phase
boost of 60° that is centered at the cross over frequency,
fC. Next, in order to produce the desired target crossover
frequency, the gain of the compensation network at the
point of maximum phase boost, GCENTER, must be set to
−7dB. The gain of the compensated error amplifier at the
point of maximum phase gain is given by the following
equation.
GCENTER =10log 2πfP
2πfZ
( )
3RTOPCFB
( )
2
dB
Assuming a multiple of 50 separation between the pole
frequencies and zero frequencies this can be simplified
to the following expression.
GCENTER =20log 50
2πf
CRTOPCFB
dB
This equation completes the set of constraints needed to
determine the compensation component values. Specifi-
cally, the two zeros, fZERO1 and fZERO2, should be located
near 5kHz. The two poles, fPOLE2 and fPOLE3, should be
located near 250kHz and the gain should be set to provide
a gain at the crossover frequency of GCENTER = –7dB.
The first step in defining the compensation component
values is to pick a value for RTOP that provides an accept-
ably low quiescent current through the resistor divider. A
value of RTOP = 845kΩ is a reasonable choice and is used
in several applications circuits. Next, the value of CFB can
be found in order to set the error amplifier gain at the
crossover frequency to −7dB as follows.
GCENTER =–7dB =20log 50
2π35kHz
( )
845kΩ
( )
CFB
CFB =50
0.1851012 antilog –7
20
680pF
The compensation poles can be set at 250kHz and the
zeros at 5kHz by using the expressions for the pole and
zero frequencies given in the previous section. Setting the
frequency of the first zero fZERO1, to 5kHz results in the
following value for RFB.
RFB =
1
2π680pF
( )
5kHz
( )
45kΩ
A 33kΩ was selected to split the two zeros slightly apart,
giving a higher zero frequency of 7kHz. This leaves the
free parameter, CPOLE, to set the frequency fPOLE1 to the
common pole frequency of 250kHz.
APPLICATIONS INFORMATION
LTC31 12 1 1 1 \ 4 \L __________A \ //K \ / \ __\ GAIN V‘ L7LJCUEN2
LTC3112
24
3112fd
For more information www.linear.com/LTC3112
CPOLE =
1
2π33kΩ
( )
250kHz
( )
22pF
Next, CFF can be chosen to set the second zero, fZERO2, to
the common zero frequency of 5kHz.
CFF =
1
2π845kΩ
( )
5kHz
( )
40pF
In this case CFF was selected at 47pF giving a lower fre-
quency of 4kHz for the second zero. Finally, the resistor
value RFF can be chosen to place the second pole.
RFF =
1
2π47pF
( )
250kHz
( )
13kΩ
A 10kΩ is chosen giving a 325kHz pole frequency. Now
that the pole frequencies, zero frequencies and gain of the
compensation network have been established, the next
step is to generate a Bode plot for the compensated error
amplifier to confirm its gain and phase properties. A Bode
plot of the error amplifier with the designed compensation
component values is shown in Figure 10. The Bode plot
confirms that the peak phase occurs near 30kHz and the
phase boost at that point is around 60°. In addition, the
gain at the peak phase frequency is –10db, close to the
design target.
APPLICATIONS INFORMATION
fC
FREQUENCY (Hz)
10
–200
GAIN (dB)
PHASE (DEG)
0
–50
100 1k 10k 100k
3112 F10
1M
–100
–150
50
100
–200
–150
0
–50
–100
50
100
GAIN
PHASE
Figure 10. Compensated Error Amplifier Bode Plot.
The final step in the design process is to compute the Bode
plot for the entire loop using the designed compensation
network and confirm its phase margin and crossover
frequency. The complete loop Bode plot for this example
is shown in Figure 11. The resulting loop crossover fre-
quency is 25kHz and the phase margin is approximately
60°. The crossover frequency is a bit lower than the design
target of 35kHz, but farther away from the troublesome
right half plane zero.
FREQUENCY (Hz)
10
–60
GAIN (dB)
PHASE (DEG)
–40
–20
0
20
40
60
–180
fC
–120
–60
0
60
GAIN
120
180
100 1k 10k 100k
3112 F11
1M
PHASE
Figure 11. Complete Loop Bode Plot.
This feedback design example was done at 3.5VIN, 5VOUT,
and a 1A load current. The phase margin in boost mode
will decrease at lower VINs, higher VOUTs, load currents,
or inductor values due to the right half plane zero shifting
to a lower frequency.
As a reminder, the amount of power stage Q at the L-C
resonant frequency is highly dependent on the RS term
(series resistance) which includes the ESR of the inductor
and the LTC3112’s low RON MOSFETs. Lower total series
resistances give a higher Q, making the feedback design
more difficult. Higher series resistances lower the Q,
resulting in a lower loop cross over frequency.
The Bode plot for the complete loop should be checked over
all operating conditions and for variations in component
values to ensure that sufficient phase margin exists in all
cases. The stability of the loop should also be confirmed
via time domain simulation and by evaluating the transient
response of the converter in the actual circuit.
LTC3112 —H'I'|'|— _| .3 I § 3% L'w—LI— II .||—< (m:="" ut:="" l?”—="" d="" j="" l="" 4”?="" f74”?="" l7hejwegr="" 25="">
LTC3112
25
3112fd
For more information www.linear.com/LTC3112
TYPICAL APPLICATIONS
1,2 or 3 Li-Ion to 5V
0.1µF
680pF
VIN 2.7V
TO 15V
VOUT
2.2µH
0.1µF
33k
845k
158k
47pF
47µF
F
10k
42.2k100pF
TO ADC
1V PER AMP
ONOFF
SW1
BST1
VIN
VCC
RUN
GND
PWM/SYNC
SW2
BST2
VOUT
COMP
IOUT
OVP
FB
LTC3112
VOUT
5V/2A
VIN > 5V
22µF
3112 TA04
1.5MHz CLOCK
OPTIONAL 22pF
LTC3112 Synchronized to 1.5MHz Clock, 5V/2A Output
3112 TA04a
SW1
5V/DIV
SW2
5V/DIV
PWM/SYNC
5VDIV
INDUCTOR
CURRENT
1A/DIV
200ns/DIV
0.1µF
680pF
22pF
VIN 3V
TO 12.6V
4.7µH
0.1µF
33k
845k
158k
47pF
47µF
F
10k
42.2k
100pF
TO ADC 1V PER AMP
ONOFF
PWMBURST
SW1
BST1
VIN
VCC
RUN
GND
PWM/SYNC
SW2
BST2
VOUT
COMP
IOUT
OVP
FB
LTC3112
VOUT
5V/1.5A
VIN > 4V
10µF
+
1-3 CELL
Li-ION
3112 TA03
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
100
70
80
50
60
90
30
40
0.01 10.1
3112 TA03a
0.001
PWM
BURST
3.6VIN
7.2VIN
10.8VIN
LTC31 12 26 L7 LINE/“2
LTC3112
26
3112fd
For more information www.linear.com/LTC3112
TYPICAL APPLICATIONS
0.1µF
680pF
VIN
15V TO 2V
VOUT
4.7µH
0.1µF
220µF
TANT
22mF
SUPERCAP
33k
845k
158k
47pF
47µF
10k
42.2k100pF
TO ADC
1V PER AMP
SW1
BST1
VIN
VCC
RUN
GND
PWM/SYNC
SW2
BST2
VOUT
COMP
IOUT
OVP
FB
LTC3112
VOUT
5V/250mA
F
3112 TA05
22pF
499k
1M
499k
+
5V Backup Supply from Supercap Runs Down to VIN = 2V with 250mA Load
3112 TA05a
VIN
5V/DIV
VOUT
5V/DIV
ILOAD
500mA/DIV
RUN
5V/DIV
500ms/DIV
LTC3112 27 L7 LJUW
LTC3112
27
3112fd
For more information www.linear.com/LTC3112
0.1µF
680pF
VIN
4.7µH
0.1µF
33k
845k
158k
47pF 100µF
10k
42.2k100pF
TO ADC
1V PER AMP
33pF
158k
1000k
ONOFF
SW1
BST1
VIN
VCC
RUN
GND
PWM/SYNC
SW2
BST2
VOUT
COMP
IOUT
OVP
FB
LTC3112
VOUT
5V/2.5A,
VIN > 5V
100µF F
3112 TA06
PWMBURST
1050k
100pF
LTC4352
IDEAL
DIODE
12V ADAPTER
1-OR 2-SERIES
Li-ION CELLS
MBR735
22pF
VOUT
OPTIONAL
Stepped Response from 1 or 2 Li-Ion to 12V Adapter Source with VIN Feedforward Network
TYPICAL APPLICATIONS
3112 TA06a
VIN
5V/DIV
VOUT
2V/DIV
INPUT CURRENT
10A/DIV
COMP
500mVDIV
100µs/DIV
3112 TA06b
VIN
5V/DIV
VOUT
2V/DIV
INPUT CURRENT
1A/DIV
COMP
500mVDIV
1ms/DIV
Adapter Plug-In Adapter Disconnect
LTC31 12 W h 4 fl +- , I :j M j % i :1. g; —— OFF ON l\ "B u 28 L7ELUEN2
LTC3112
28
3112fd
For more information www.linear.com/LTC3112
0.1µF
820pF
VIN
4.5V TO 15V
10µH
0.1µF
33k
2210k
158k
47pF
47µF
F
10k
42.2k100pF
TO ADC
1V PER AMP
ONOFF
PWMBURST
SW1
BST1
VIN
VCC
RUN
GND
PWM/SYNC
SW2
BST2
VOUT
COMP
IOUT
OVP
FB
LTC3112
VOUT
12V
1A VIN > 5V
2A VIN > 9V
22µF
3112 TA07
22pF
Regulated 12V Output from Wide Input Supply Range
TYPICAL APPLICATIONS
PWM
3112 TA07a
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
100
70
80
50
60
90
30
40
0.01 10.10.001
BURST
5.0VIN
12VIN
LTC3112 ’ , Ffifiafiififiafi"; a 1 a T """ T ””” ji’ 1 ‘ 1 aflugufigmuu J“ \L % ‘ a 1 w J i uuuuiuuwu 1 1 1 , ,,,,, ‘ ,,,,, , , ,,,,,, T ,,,,, , \ \ \ E, ‘0 1 mm 1 mm JL 1,, 7 .7fi «fl. +H+ L7HEJWEGR 29
LTC3112
29
3112fd
For more information www.linear.com/LTC3112
PACKAGE DESCRIPTION
4.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
2.44 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
4.34 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHD16) DFN REV A 1113
0.25 ±0.05
PIN 1
NOTCH
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.44 ±0.05
(2 SIDES)
3.10 ±0.05
0.50 BSC
0.70 ±0.05
4.50 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707 Rev A)
Please refer to http://www.linear.com/product/LTC3112#packaging for the most recent package drawings.
[IC3112 495 (‘95; AA’DJDDDDDDED :\ \1 L 44:flflflflflflmmflfl < m="" ‘="" (‘59’="" v77]="" ‘="" w="" a4="" ;="" *‘="" ,="" 7,7="" (0213:1329)="" 7»="" l="" 5="" 40="" 7="" 6="" 50‘="" (2527="" 250)="" 4="" as="" (was)="" hjwhhhhhh="" ‘hii'="" \="" \="" \="" w="" owssiuao="" m="" ‘="" ‘e="" h="" 00510‘5="" (00777="" mus)="">
LTC3112
30
3112fd
For more information www.linear.com/LTC3112
PACKAGE DESCRIPTION
FE20 (CA) TSSOP REV J 1012
0.09 – 0.20
(.0035 – .0079)
0° 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.95
(.195)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation CA
Please refer to http://www.linear.com/product/LTC3112#packaging for the most recent package drawings.
LTC3112 L7 LJUW 3 1
LTC3112
31
3112fd
For more information www.linear.com/LTC3112
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 06/13 Clarified Absolute Maximum Rating: IOUT voltage spec.
Clarified RUN threshold specification.
Clarified thermal considerations last paragraph.
Clarified LTC4352 part designator.
Clarified Related Parts list.
2
3
12
28
32
B 10/13 Clarified Buck Mode Small Signal Model Text
Clarified CFB Formula
18
23
C 06/14 Clarified Title of Typical Application
Clarified Absolute Maximum Temperature Range and Ordering Information
Clarified Note 2, 3 Temperature Range on Input Operating Range
Clarified Graphs Temperature Range
Clarified Maximum Junction Temperature
1
2
3, 4
6
12
D 09/16 Changed Minimum VIN UVLO Threshold spec
Fixed Block Diagram node error
3
10
LTC31 12 L7LJCUEN2 32
LTC3112
32
3112fd
For more information www.linear.com/LTC3112
LINEAR TECHNOLOGY CORPORATION 2010
LT 0916 REV D • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC3112
RELATED PARTS
PART
NUMBER DESCRIPTION COMMENTS
LTC3531 200mA Buck-Boost Synchronous DC/DC Converter VIN = 1.8V to 5.5V, VOUT = 3.3V, IQ = 16μA, ISD < 1μA , SOT23, DFN Package
LTC3129 15V, 200mA Synchronous Buck-Boost Converter VIN = 2.42V to 15V, VOUT = 1.4V to 15.75V, IQ = 1.3μA, ISD < 10nA , QFN and
MSOP Packages
LTC3533 2A (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter VIN = 1.8V to 5.5V, VOUT = 1.8V to 5.25V, IQ = 40μA, ISD < 1μA , DFN Package
LTC3113 3A Low Noise Synchronous Buck-Boost DC/DC Converter VIN or VOUT = 1.8V to 5.5V, IQ = 40µA, ISD < 1µA, DFN and TSSOP Packages
LTC3534 7V, 500mA Synchronous Buck-Boost DC/DC Converter VIN = 2.4V to 7V, VOUT = 1.8V to 7V, IQ = 25μA, ISD < 1μA , DFN, GN Package
LTC3538 800mA Synchronous Buck-Boost DC/DC Converter VIN = 2.4V to 5.5V, VOUT = 1.8V to 5.25V, IQ = 35μA, ISD < 5μA , DFN Package
LTC3440 600mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC
Converter
VIN = 2.5V to 5.5V, VOUT = 2.5V to 5.25V, IQ = 25μA, ISD < 1μA , MSOP and
DFN Packages
LTC3441 1.2A (IOUT), 1MHz Synchronous Buck-Boost DC/DC
Converter
VIN = 2.4V to 5.5V, VOUT = 2.4V to 5.25V, IQ = 25μA, ISD < 1μA , DFN Package
LTC3442 1.2A (IOUT), 2MHz Synchronous Buck-Boost DC/DC
Converter with Programmable Burst Mode Operation
VIN = 2.4V to 5.5V, VOUT = 2.4V to 5.25V, IQ = 35μA, ISD < 1μA , DFN Package
LTC3443 High Current Micropower 600kHz Synchronous Buck-Boost
DC/DC Converter
VIN = 2.4V to 5.5V, VOUT = 1.5V to 5.25V, IQ = 28μA, ISD < 1μA , DFN Package
LTC3115-1 2A (IOUT), 40V Synchronous Buck-Boost DC/DC Converter VIN = 2.7V to 40V, VOUT = 2.7V to 40V, IQ = 30µA, ISD < 3μA , DFN and TSSOP
Packages
LTC3780 High Efficiency, Synchronous, 4-Switch Buck-Boost
Converter
VIN = 4V to 36V, VOUT = 0.8V to 30V, IQ = 1500μA, ISD < 55μA , QFN Package
LTC3785 10V, High Efficiency, Synchronous, No RSENSE
Buck-Boost Controller
VIN = 2.7V to 10V, VOUT = 2.7V to 10V, IQ = 86μA, ISD < 15μA , QFN Package
LTC3101 Wide VIN, Multi-Output DC/DC Converter and PowerPath™
Controller
VIN = 1.8V to 5.5V, VOUT = 1.5V to 5.25V, IQ = 38μA, ISD < 15μA , QFN Package
LTC3522 Synchronous 400mA Buck-Boost and 200mA Buck VIN = 2.4V to 5.5V, VOUT = 2.2V to 5.25V, IQ = 25μA, ISD < 1μA , QFN Package
LTC3530 Wide Input Voltage Synchronous Buck-Boost DC/DC
Converter
VIN = 1.8V to 5.5V, VOUT = 1.8V to 5.25V, IQ = 40μA, ISD < 1μA , DFN Package
TYPICAL APPLICATION
0.1µF
3300pF
VIN
5V TO 15V
6.8µH
0.1µF
200k
2210k
158k
22µF
68.1k
3300pF
68.1k
VDAC
SW1
BST1
VIN
VCC
RUN
GND
PWMSYNC
SW2
BST2
VOUT
COMP
IOUT
OVP
FB
LTC3112 VOUT
22µF
F
3112 TA07
47pF
DAC PROGRAMS LED CURRENT
1.0A AT 0V, 500mA AT 0.8V
IOUT = (1-0.625 • VDAC)A
OPEN LAMP AT 12V
VF = 3.6V
PER LED
AT 1A
10W, 10V High Intensity LED Driver with Programmable Current and Low-Loss Sensing
3112 TA08a
VIN (V)
4
LED CURRENT (mA)
1500
1000
1250
500
750
0
250
8 12 14106
VDAC = 0V
VDAC = 0.8V
LED Current vs VIN and DAC Voltage

Products related to this Datasheet

IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 20TSSOP
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 20TSSOP
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 20TSSOP
IC REG BCK BST ADJ 2.5A 20TSSOP
BOARD DEMO FOR LTC3112EDHD
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 20TSSOP
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 20TSSOP
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 20TSSOP
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 20TSSOP
IC REG BCK BST ADJ 2.5A 16DFN
IC REG BCK BST ADJ 2.5A 16DFN