LTC3589(-1, -2) Datasheet by Analog Devices Inc.

View All Related Products | Download PDF Datasheet
LTC3589/LTC3589-1 / LTC3589-2 TECHNOLOGY —| E E T W : 1-" E 1' «1—3 = E?“ L“! _|_—' —>I u”— L7 LJUW 1
LTC3589/LTC3589-1/
LTC3589-2
1
3589fh
For more information www.linear.com/LTC3589
Typical applicaTion
FeaTures DescripTion
applicaTions
The LT C
®
3589 is a complete power management solu-
tion for ARM and ARM-based processors and advanced
portable microprocessor systems. The device contains
three step-down DC/DC converters for core, memory and
SoC rails, a buck-boost regulator for I/O at 1.8V to 5V and
three 250mA LDO regulators for low noise analog sup-
plies. An I2C serial port is used to control enables, output
voltage levels, dynamic voltage scaling, operating modes
and status reporting. Differences between the LTC3589,
LTC3589-1, and LTC3589-2 are summarized in Table 1.
Regulator start-up is sequenced by connecting outputs to
enable pins in the desired order or programmed via the
I2C port. System power-on, power-off, and reset functions
are controlled by pushbutton interface, pin inputs, or I2C
interface.
The LTC3589 supports i.MX53/51, PXA and OMAP pro-
cessors with eight independent rails at appropriate power
levels. Other features include interface signals such as
the VSTB pin that simultaneously toggle up to four rails
between programmed run and standby output voltages.
The device is available in a low profile 40-pin 6mm × 6mm
exposed pad QFN package.
Start-Up Sequence
n Triple I2C Adjustable High Efficiency Step-Down DC/
DC Converters: 1.6A, 1A/1.2A, 1A/1.2A
n High Efficiency 1.2A Buck-Boost DC/DC Converter
n Triple 250mA LDO Regulators
n Pushbutton ON/OFF Control with System Reset
n Flexible Pin-Strap Sequencing Operation
n I2C and Independent Enable Control Pins
n Power Good and Reset Outputs
n Dynamic Voltage Scaling and Slew Rate Control
n Selectable 2.25MHz or 1.12MHz Switching Frequency
n Always-Alive 25mA LDO Regulator
n 8µA Standby Current
n 40-Pin 6mm × 6mm × 0.75mm QFN
n Handheld Instruments and Scanners
n Portable Industrial Devices
n Automotive Infotainment
n Medical Devices
n High End Consumer Devices
n Multirail Systems
n Supports Freescale i.MX53/51, Marvell PXA and
Other Application Processors L, LT , LT C, LTM , Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
8-Output Regulator with
Sequencing and I2C
500µs/DIV
0.5V/DIV
3589 TA01b
BB_OUT
WAKE
(1V/DIV)
LDO2
SW3
SW1
SW2
LDO3
LDO1_STBY
VIN 2.7V TO 5.5V
H
F
F
F
F
1.5µH
1.5µH
2.7µH
SW1
SW2
SW3
SW4CD
BB_OUT
SW4AB
LTC3589
0.8V TO VIN
AT 25mA
0.5V TO VIN
AT 1.6A
22µF
22µF
22µF
22µF
0.5V TO VIN
AT 1A
0.5V TO VIN
AT 1A
0.36V TO VIN
AT 250mA
1.8V
AT 250mA
2.8V
AT 250mA
3589 TA01a
VIN
LDO2
LDO3
LDO4
GND
I2C
ENABLES
PWR_ON
ON
3
4
7
STATUS
WAKE
1.8V TO 5V
LTC3589/ LT LTC3589—2 2 L7LJ1‘JW
LTC3589/LTC3589-1/
LTC3589-2
2
3589fh
For more information www.linear.com/LTC3589
Table oF conTenTs
Features ............................................................................................................................ 1
Applications ....................................................................................................................... 1
Typical Application ............................................................................................................... 1
Description......................................................................................................................... 1
Absolute Maximum Ratings ..................................................................................................... 3
Pin Configuration ................................................................................................................. 3
Order Information ................................................................................................................. 3
Electrical Characteristics ........................................................................................................ 4
Typical Performance Characteristics .......................................................................................... 9
Pin Functions .....................................................................................................................13
Block Diagram ....................................................................................................................15
Operation..........................................................................................................................16
Introduction .......................................................................................................................................................... 16
LTC3589, LTC3589-1, and LTC3589-2 Functional Comparison ............................................................................. 17
Always-On LDO ..................................................................................................................................................... 17
Step-Down Switching Regulators ......................................................................................................................... 20
Buck-Boost Switching Regulator .......................................................................................................................... 24
Slewing DAC Reference Operation ........................................................................................................................ 28
Pushbutton Operation ........................................................................................................................................... 29
Enable and Power-On Sequencing ........................................................................................................................ 31
Fault Detection, Shutdown, and Reporting ............................................................................................................ 32
I2C Operation ........................................................................................................................................................ 36
Thermal Considerations and Board Layout ........................................................................................................... 42
Typical Application ..............................................................................................................46
Package Description ............................................................................................................48
Revision History .................................................................................................................49
Typical Application ..............................................................................................................50
Related Parts .....................................................................................................................50
LTC3589— 1 / LTC3589—2 mp vwa wwwflwwwwww mama nzmimmm fli‘fli‘fim L7 LJUW 3
LTC3589/LTC3589-1/
LTC3589-2
3
3589fh
For more information www.linear.com/LTC3589
absoluTe MaxiMuM raTings
(Notes 1, 3)
orDer inForMaTion
pin conFiguraTion
VIN, DVDD, SW1, SW2, SW3, SW4AB, SW4CD .... 0.3V to 6V
SW1, SW2, SW3, SW4AB, SW4CD
(Transients <s, Duty Cycle < 5%) ............... –2V to 7V
PVIN1, PVIN2, PVIN3, PVIN4 ............... 0.3V to VIN + 0.3V
VIN_LDO2, VIN_LDO34 ......................... 0.3V to VIN + 0.3V
LDO1_STBY, LDO1_FB, BUCK1_FB, BUCK2_FB,
BUCK3_FB, BB_FB, BB_OUT, LDO2, LDO2_FB, LDO3,
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3589EUJ#PBF LTC3589EUJ#TRPBF LTC3589UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3589IUJ#PBF LTC3589IUJ#TRPBF LTC3589UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3589HUJ#PBF LTC3589HUJ#TRPBF LTC3589UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 150°C
LTC3589EUJ-1#PBF LTC3589EUJ-1#TRPBF LTC3589UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3589IUJ-1#PBF LTC3589IUJ-1#TRPBF LTC3589UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3589HUJ-1#PBF LTC3589HUJ-1#TRPBF LTC3589UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 150°C
LTC3589EUJ-2#PBF LTC3589EUJ-2#TRPBF LTC3589UJ-2 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3589IUJ-2#PBF LTC3589IUJ-2#TRPBF LTC3589UJ-2 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3589HUJ-2#PBF LTC3589HUJ-2#TRPBF LTC3589UJ-2 40-Lead (6mm × 6mm) Plastic QFN –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
LDO4, PGOOD, VSTB, EN1, EN2, EN3, EN4, EN_LDO2,
EN_LDO34, EN_LDO3, ON, PBSTAT, WAKE, RSTO,
PWR_ON, IRQ, ........................................... 0.3V to 6V
SDA, SCL ......................................0.3V to DVDD + 0.3V
Operating Junction Temperature Range
(Note 2) .................................................. 40°C to 150°C
Storage Temperature Range .................. 6C to 150°C
LTC3589 LTC3589-1/LTC3589-2
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
VIN_LDO2
LDO2
LDO3
LDO4
VIN_LDO34
PVIN1
SW1
RSTO
EN_LDO2
EN1
SCL
PGOOD
VSTB
PVIN3
SW3
SW2
PVIN2
WAKE
PBSTAT
ON
BB_FB
BUCK1_FB
LDO2_FB
VIN
LDO1_STBY
LDO1_FB
BUCK3_FB
BUCK2_FB
DVDD
SDA
EN2
SW4AB
EN3
EN4
PVIN4
BB_OUT
IRQ
EN_LDO34
SW4CD
PWR_ON
21
30
10
1
TJMAX = 150°C, θJA = 33°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
VIN_LDO2
LDO2
LDO3
LDO4
V
IN_LDO34
PVIN1
SW1
RSTO
EN_LDO2
EN1
SCL
PGOOD
VSTB
PVIN3
SW3
SW2
PVIN2
WAKE
PBSTAT
ON
BB_FB
BUCK1_FB
LDO2_FB
VIN
LDO1_STBY
LDO1_FB
BUCK3_FB
BUCK2_FB
DVDD
SDA
EN2
SW4AB
EN3
EN4
PVIN4
BB_OUT
IRQ
EN_LDO3
SW4CD
PWR_ON
21
30
10
1
TJMAX = 150°C, θJA = 33°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC3589#orderinfo
LTC3589/ LT LTC3589—2
LTC3589/LTC3589-1/
LTC3589-2
4
3589fh
For more information www.linear.com/LTC3589
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Input Supply Voltage, VIN l2.7 5.5 V
ISTANDBY VIN Standby Current All Enables = 0V, PWR_ON = 0V, ILDO1 = 0mA l8 18 µA
fOSC Oscillator Frequency l1.8 2.25 2.6 MHz
Step-Down Switching Regulators 1, 2, and 3
IVIN Pulse-Skipping Mode VIN Quiescent Current
per Buck
Burst Mode
®
VIN Quiescent Current per Buck
VFB = 0.85V (Note 5) l
l
120
23
200
40
µA
µA
IFB Feedback Pin Input Current VFB = 0.8V –50 50 nA
DXMaximum Duty Cycle VFB = 0V 100 %
RSW SW Pull-Down Resistance Regulators Disabled 2.5
tSS Soft-Start Rate (Note 6) 0.8 V/ms
VFB(MAX) Maximum Feedback Voltage BxDTV1 = BxDTV2 = 11111,
VIN = 2.7V to 5.5V
l0.735 0.75 0.765 V
VFB(LSB) Feedback LSB Step Size 12.5 mV
VFB(MIN) Minimum Feedback Voltage BxDTV1 = BxDTV2 = 00000,
VIN = 2.7V to 5.5V
l0.351 0.3625 0.374 V
1.6A Step-Down Switching Regulator 1
ILIM1 Peak PMOS Current Limit SW1 l2.0 2.7 A
RP1 RDS(ON) of PMOS1 ISW1 = –100mA 180
RN1 RDS(ON) of NMOS1 ISW1 = 100mA 110
1.0A/1.2A Step-Down Switching Regulators 2 and 3
ILIM2, 3 Peak PMOS Current Limit SW2 and SW3 (LTC3589)
Peak PMOS Current Limit SW2 and SW3 (LTC3589-1/
LTC3589-2)
l
l
1.5
1.8
1.9
2.3
A
A
RP2, 3 RDS(ON) of PMOS2 and PMOS3 ISW1 = –100mA 250
RN2, 3 RDS(ON) of NMOS2 and NMOS3 ISW1 = 100mA 130
1.2A Buck-Boost Switching Regulator 4 (Buck-Boost)
IVIN PWM Mode VIN Quiescent Current
Burst Mode VIN Quiescent Current
VBB_FB = 0.85V (Note 5) l
l
115
19
170
35
µA
µA
VBB_FB Feedback Voltage VIN = 2.7V to 5.5V l0.776 0.8 0.824 V
VOUTBB Output Voltage Range 1.8 5.0 V
ILIM4 Peak PMOS Current Limit SW4AB l2.3 2.9 A
IPEAK4 Forward Burst Current Limit (Switch A) Burst Mode Operation 600 mA
ILIMR4 Reverse Current Limit (Switch D) 1 A
IZERO4 Reverse Burst Current Limit (Switch D) Burst Mode Operation 0 mA
RP4 RDS(ON) of Switch A and Switch D ISW4AB = ISW4CD = 100mA 160
RN4 RDS(ON) of Switch B and Switch C ISW4AB = ISW4CD = –100mA 110
ROUT4 BB_OUT Pull-Down Resistance Regulator Disabled 2.5
tSS Soft-Start Rate (Note 6) 2 V/ms
IFB Feedback Pin Input Current VFB = 0.85V –50 50 nA
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34
= DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589— 1 / LTC3589—2
LTC3589/LTC3589-1/
LTC3589-2
5
3589fh
For more information www.linear.com/LTC3589
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LDO Regulators
tLDO_SS Soft-Start Time LDO2, LDO3, LDO4 100 µs
RLDO_PD Output Pull-Down Resistance LDO2, LDO3, LDO4 LDO Disabled 2.5
Always-On Regulator (LDO1_STBY)
VLDO1_FB LDO1 Feedback Voltage l0.76 0.8 0.84 V
VLDO1 LDO1 Line Regulation ILDO1_STBY = 1mA, LDO1_STBY = 1.2V,
VIN = 2.7V to 5.5V
0.15 %/V
LDO1 Load Regulation ILDO1 = 0.1mA to 25mA,
LDO1_STBY = 1.2V
0.1 %
ILDO1 Available Output Current l25 mA
ILDO1_SC Short-Circuit Output Current Limit 65 100 mA
VDROP1 Dropout Voltage (Note 4) ILDO1 = 25mA, LDO1_STBY = 3.3V 200 mV
ILDO1_FB LDO1_FB Input Current VLDO1_FB = 0.85V –50 50 nA
LDO Regulator 2 (LDO2)
VIN_LDO2 VIN_LDO2 Input Voltage Range l1.7 VIN V
IVIN_LDO2 VIN_LDO2 Quiescent Current
VIN_LDO2 Shutdown Current
Regulator Enabled
Regulator Disabled
l
l
12
0
20
1
µA
µA
IVIN VIN Quiescent Current EN_LDO2 = High l50 85 µA
VFB2(MAX) LDO2 Maximum Feedback Voltage L2DTV1 = L2DTV2 = 11111 l0.735 0.75 0.765 V
VFB2(LSB) LDO2 Feedback LSB Step Size 12.5 mV
VFB2(MIN) LDO2 Minimum Feedback Voltage L2DTV1 = L2DTV2 = 00000
VIN_LDO2 = VIN = 2.7V to 5.5V,
ILDO2 = 1mA
l0.351 0.3625 0.374 V
LDO2 Line Regulation ILDO2 =1mA, VIN_LDO2 = 2.7V to 5.5V 0.01 %/V
LDO2 Load Regulation ILDO2 = 1mA to 250mA 0.01 %
ILDO2 LDO2 Available Output Current l250 mA
ILDO2_SC LDO2 Short-Circuit Current Limit 300 450 600 mA
VDROP2 Dropout Voltage (Note 4) ILDO2 = 200mA, VLDO2 = 2.5V
ILDO2 = 200mA, VLDO2 = 1.2V
140
350
180
500
mV
mV
ILDO2_FB LDO2_FB Input Current VLDO2_FB = 0.8V –50 50 nA
LDO Regulator 3 (LDO3)
VIN_LDO34 VIN_LDO34 Input Range (LTC3589)
VIN_LDO34 Input Range (LTC3589-1/LTC3589-2)
l
l
2.35
3.0
VIN
VIN
V
V
IVIN_LDO34 VIN_LDO34 Quiescent Current
VIN_LDO34 Shutdown Current
Regulator Enabled
Regulator Disabled
l
l
15
0
29
1
µA
µA
IVIN VIN Quiescent Current EN_LDO3 = High l50 85 µA
VLDO3 LDO3 Output Voltage (LTC3589)
LDO3 Output Voltage (LTC3589-1/LTC3589-2)
VIN_LDO34 = VIN = 2.7V to 5V,
ILDO3 = 1mA
l
l
1.746
2.716
1.8
2.8
1.854
2.884
V
V
LD03 Line Regulation ILDO3 =1mA, VIN_LDO34 = 2.7V to 5.5V 0.01 %/V
LDO3 Load Regulation ILDO3 = 1mA to 250mA 0.05 %
ILDO3 LDO3 Available Output Current l250 mA
ILDO3_SC LDO3 Short-Circuit Current Limit 300 450 600 mA
VDROP3 LDO3 Dropout Voltage (LTC3589) (Note 4)
LDO3 Dropout Voltage (LTC3589-1/LTC3589-2)
(Note 4)
ILDO3 = 200mA, VLDO3 = 1.8V
ILDO3 = 200mA, VLDO3 = 2.8V
190
140
250
180
mV
mV
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34
= DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589/ LT LTC3589—2
LTC3589/LTC3589-1/
LTC3589-2
6
3589fh
For more information www.linear.com/LTC3589
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LDO Regulator 4 (LDO4)
VIN_LDO34 VIN_LDO34 Input Range (LTC3589)
VIN_LDO34 Input Range (LTC3589-1/LTC3589-2)
l
l
2.35
1.7
VIN
VIN
V
V
IVIN_LDO34 VIN_LDO34 Quiescent Current
VIN_LDO34 Shutdown Current
Regulator Enabled
Regulator Disabled
l
l
14
0
24
1
µA
µA
IVIN VIN Quiescent Current EN_LDO4 = High l50 85 µA
VLDO4
(LTC3589)
LDO 4 Output Voltage ILDO4 = 1mA, L2DTV2[6:5] = 00
L2DTV2[6:5] = 01
L2DTV2[6:5] = 10
L2DTV2[6:5] = 11
l
l
l
l
2.716
2.425
1.746
3.201
2.8
2.5
1.8
3.3
2.884
2.575
1.854
3.399
V
V
V
V
VLDO4
(LTC3589-1)
(LTC3589-2)
LDO 4 Output Voltage ILDO4 = 1mA, L2DTV2[6:5] = 00
L2DTV2[6:5] = 01
L2DTV2[6:5] = 10
L2DTV2[6:5] = 11
l
l
l
l
1.164
1.746
2.425
3.104
1.2
1.8
2.5
3.2
1.236
1.854
2.575
3.296
V
V
V
V
LD04 Line Regulation ILDO4 =1mA, VIN_LDO34 = 2.7V to 5.5V,
VOUT = 1.8V
0.01 %/V
LDO4 Load Regulation ILDO4 = 1mA to 250mA 0.05 %
ILDO4 LDO4 Available Output Current l250 mA
ILDO4_SC LDO4 Short-Circuit Current Limit 300 450 600 mA
VDROP4 LDO4 Dropout Voltage (Note 4) ILDO4 = 200mA, VLDO4 = 3.3V
ILDO4 = 200mA, VLDO4 = 1.8V
ILDO4 = 200mA, VLDO4 = 3.2V (LTC3589-1/
LTC3589-2)
120
190
120
160
250
160
mV
mV
mV
Enable Inputs
VENx_THR Threshold Rising All Enables Low l0.8 1.2 V
VENx_THR2
VENx_THF2
Threshold Rising
Threshold Falling
Any Enable High
Any Enable High
l
l
0.420
0.5
0.45
0.530 V
V
RENX Input Pull-Down Resistance 4.5
VSTB, PWR_ON Inputs
VVSTB_THR
VVSTB_THF
VSTB Pin Threshold Rising
VSTB Pin Threshold Falling
l
l
0.4
0.8
0.7
1.2 V
V
RVSTB Pull-Down Resistance 4.5
VPWR_ONTHR
VPWR_ONTHF
PWR_ON Pin Threshold Rising
PWR_ON Pin Threshold Falling
l
l
0.4
0.8
0.7
1.2 V
V
RPWR_ON Pull-Down Resistance 4.5
I2C Port
DVDD DVDD Input Supply Voltage l1.6 5.5 V
IDVDD DVDD Quiescent Current SCL/SDA = 0kHz 0.5 µA
VDVDD_UVLO DVDD UVLO Level 0.8 V
ADDRESS Device Address – Write
Device Address – Read
01101000
01101001
VIH SDA, SCL
VIL SDA, SCL
SDA and SCL Input Threshold Rising
SDA and SCL Input Threshold Falling
70
30
%DVDD
%DVDD
IIHSCx IILSCx SDA and SCL Input Current SDA = SCL = 0V to 5.5V –250 250 nA
VOL SDA SDA Output Low Voltage ISDA = 3mA l0.4 V
fSCL SCL Clock Operating Frequency 400 kHz
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34
= DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589— 1 / LTC3589—2
LTC3589/LTC3589-1/
LTC3589-2
7
3589fh
For more information www.linear.com/LTC3589
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSU_STA Repeated Start Condition Set-Up Time 0.6 µs
tSU_STO Stop Condition Set-Up Time 0.6 µs
tHD_DAT(O) Data Hold Time Output 0 900 ns
tHD_DAT(I) Data Hold Time Input 0 ns
tSU_DAT Data Set-Up Time 100 ns
tLOW SCL Clock Low Period 1.3 µs
tHIGH SCL Clock High Period 0.6 µs
tfData Fall Time CB = Capacitance of One BUS Line (pF) 20 + 0.1CB300 ns
trData Rise Time CB = Capacitance of One BUS Line (pF) 20 + 0.1CB300 ns
tSP Input Spike Suppression Pulse Width 50 ns
Pushbutton Interface
VON_THR
VON_THF
ON Threshold Rising
ON Threshold Falling
l
l
0.4
0.8
0.7
1.2 V
V
ION ON Input Current ON = VIN
ON = 0V
–100
40
100 nA
µA
tON_PBSTAT1 ON Low Time to PBSTAT Low 50 ms
tON_PBSTAT2 ON High Time to PBSTAT High 0.2 µs
tON_WAKE ON Low Time to WAKE High 400 ms
tON_HR ON Low Time to Hard Reset 5 s
tPBSTAT_PW PBSTAT Minimum Pulse Width 50 ms
tPBSTAT_BK PBSTAT Blanking from WAKE Low 1 s
tWAKE_OFF Minimum WAKE Low Time 1 s
tWAKE_ON WAKE High Time with PWR_ON = 0V 5 s
tPWR_ON PWR_ON to WAKE High (LTC3589)
PWR_ON to WAKE High (LTC3589-1/LTC3589-2)
50
2
ms
ms
tPWR_OFF PWR_ON to WAKE Low (LTC3589)
PWR_ON to WAKE Low (LTC3589-1/LTC3589-2)
50
2
ms
ms
Status Output Pins (PBSTAT, WAKE, PGOOD, RSTO, IRQ)
VPBSTAT PBSTAT Output Low Voltage IPBSTAT = 3mA 0.1 0.4 V
IPBSTAT PBSTAT Output High Leakage Current VPBSTAT = 3.8V –0.1 0.1 µA
VWAKE WAKE Output Low Voltage IWAKE = 3mA 0.1 0.4 V
IWAKE WAKE Output High Leakage Current VWAKE = 3.8V –0.1 0.1 µA
VPGOOD PGOOD Output Low Voltage IPGOOD = 3mA 0.1 0.4 V
IPGOOD PGOOD Output High Leakage Current VPGOOD = 3.8V –0.1 0.1 µA
VPGOOD PGOOD Threshold Rising
PGOOD Threshold Falling
–6
–8
%
%
VNRSTO LDO1 Power Good Threshold Rising
LDO1 Power Good Threshold Falling
–6
–8
%
%
VUVLO Undervoltage Lockout Rising
Undervoltage Lockout Falling
2.65
2.55
2.7 V
V
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34
= DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589/ LT LTC3589—2 8 L7LJ1‘JW
LTC3589/LTC3589-1/
LTC3589-2
8
3589fh
For more information www.linear.com/LTC3589
Note 1: Stresses beyond those listed Under Absolute Maximum ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3589 are tested under pulsed load conditions such
that TJ ≈ TA. The LTC3589E are guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3589I are guaranteed over the –40°C to 125°C operating junction
temperature range and the LTC3589H are guaranteed over the full
–40°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated for
junction temperatures greater than 125°C. The junction temperature (TJ
in °C) is calculated from the ambient temperature (TA in °C) and power
dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD θJA), where the package junction to ambient thermal
impedance θJA = 33°C/W.
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
Note 3: The LTC3589 include overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating temperature
may impair device reliability.
Note 4: Dropout voltage is defined as (VIN – VLDO) for LDO1 or
(VIN_LDO – VLDO) for other LDOs when VLDO is 3% lower than VLDO
measured with VIN = VIN_LDO = 4.3V.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Soft-start measured in test mode with regulator error amplifier in
unity gain mode.
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VUVWARN Undervoltage Warning Rising
Undervoltage Warning Falling
3
2.9
VRSTO RSTO Output Low Voltage IRSTO = 3mA 0.1 0.4 V
IRSTO RSTO Output High Leakage Current VRSTO = 3.8V –0.1 0.1 µA
VIRQ IRQ Output Low Voltage IIRQ = 3mA 0.1 0.4 V
IIRQ IRQ Output High Leakage Current VIRQ = 3.8V –0.1 0.1 µA
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34
= DVDD = 3.8V. All regulators disabled unless otherwise noted.
LTC3589— 1 / LTC3589—2 ,, i 1 w // ,/ ‘ , ENABLE ULATORSENAB deOPERATIDN ’ \ \ \ L7 LJUW 9
LTC3589/LTC3589-1/
LTC3589-2
9
3589fh
For more information www.linear.com/LTC3589
Typical perForMance characTerisTics
Standby IVIN vs VIN LDO2 to LDO4 IVIN vs VIN
VIN = 3.8V, TA = 25°C, unless otherwise noted.
Step-Down Switching Regulator
IVIN vs VIN
Input Supply Current
vs Temperature Buck-Boost IVIN vs VIN
Step-Down Switching Regulator
IVIN vs VIN
VIN (V)
2.5
IVIN (µA)
14
4.0
3589 G01
8
4
3.0 3.5 4.5
2
0
12
10
6
5.0 5.5
VIN (V)
2.5
IVIN (µA)
4.0
3589 G02
150
50
3.0 3.5 4.5
0
250
200
100
5.0 5.5
ENABLE TWO LDOs
ENABLE ONE LDO
ENABLE THREE LDOs
VIN (V)
2.5
VIN
4.0
3589 G03
400
500
600
200
100
3.0 3.5 4.5
0
900
800
700
300
5.0 5.5
ENABLE TWO BUCKS
ENABLE ONE BUCK
ENABLE THREE BUCKS
PULSE-SKIPPING MODE
VIN (V)
2.5
IVIN (µA)
4.0
3589 G04
80
100
120
40
20
3.0 3.5 4.5
0
60
5.0 5.5
ENABLE TWO BUCKS
ENABLE ONE BUCK
ENABLE THREE BUCKS
Burst Mode OPERATION
TEMPERATURE (°C)
–50
I
VIN
(µA)
5025
3589 G05
800
1000
1200
400
200
–25 0 75
0
600
100 125 150
ALL REGULATORS ENABLED
Burst Mode OPERATION
STANDBY (ONLY LDO1 ON)
ALL REGULATORS ENABLED
PULSE-SKIPPING MODE
VIN (V)
2.5
I
VIN
(µA)
4.54.0
3589 G06
350
400
450
150
200
50
100
3.0 3.5 5.0
0
300
250
5.5
Burst Mode OPERATION
PWM MODE
Oscillator Frequency
vs Temperature Switching Frequency Change vs VIN Buck-Boost Efficiency vs IOUT
TEMPERATURE (°C)
–50
FREQUENCY (MHz)
70
3589 G07
2.20
2.25
2.30
2.10
2.15
2.00
2.05
–10 30 110
1.95 150
VIN (V)
2.5
PERCENT CHANGE (%)
4.0
3589 G08
0.6
0.8
1.0
–0.2
0
0.2
0.4
–0.6
–0.4
3.0 3.5 4.5
–0.8 5.55.0
LOAD CURRENT (mA)
0
EFFICIENCY (%)
50
40
30
60
70
100
0.01 0.1 1 10 100 1000
3589 G9
20
10
80
90 BURST
PWM MODE
VOUT = 5.0V
VOUT = 2.5V
VOUT = 3.3V
VIN = 3.8V
LTC3589/LT |_TC3589-2 mm mm CLAMP UM‘T
LTC3589/LTC3589-1/
LTC3589-2
10
3589fh
For more information www.linear.com/LTC3589
Typical perForMance characTerisTics
Buck-Boost Efficiency vs IOUT
Step-Down Switching Regulator 1
Efficiency vs IOUT
Step-Down Switching Regulator 2
Efficiency vs IOUT
Step-Down Switching Regulator 3
Efficiency vs IOUT
Buck-Boost RDS(ON)
vs Temperature
Step-Down Switching Regulator
RDS(ON) vs Temperature
LOAD CURRENT (mA)
0
EFFICIENCY (%)
50
40
30
60
70
100
0.01 0.1 1 10 100 1000
3589 G10
20
10
80
90
BURST
PWM MODE
VIN = 5.0V
VIN = 4.2V
VIN = 3.0V
VOUT = 3.3V
LOAD CURRENT (mA)
0
EFFICIENCY (%)
50
40
30
60
70
100
0.01 0.1 1 10 100 1000
3589 G12
20
10
80
90
FORCED
CONTINUOUS
PULSE-SKIPPING
BURST
VOUT = 1.8V
LOAD CURRENT (mA)
0
EFFICIENCY (%)
50
40
30
60
70
100
0.01 0.1 1 10 100 1000
3589 G13
20
10
80
90
FORCED
CONTINUOUS
PULSE-
SKIPPING
BURST
VOUT = 3.3V
TEMPERATURE (°C)
–50
R
DS(ON)
(Ω)
70
3589 G14
0.35
0.40
0.15
0.20
0.25
0.30
0.05
0.10
–10 30
0150110
BUCK2, 3 PMOS
BUCK1 PMOS
BUCK2, 3 NMOS
BUCK1 NMOS
TEMPERATURE (°C)
–50
R
DS(ON)
(Ω)
70
3589 G15
0.15
0.20
0.25
0.05
0.10
–10 30
0150110
PMOS
NMOS
LOAD CURRENT (mA)
0
EFFICIENCY (%)
50
40
30
60
70
100
0.01 0.1 1 10 100 1000
3589 G11
20
10
80
90
PULSE-SKIPPING
FORCED
CONTINUOUS
VOUT = 1.2V
BURST
VIN = 3.8V, TA = 25°C, unless otherwise noted.
Step-Down Switching
Regulator Current Limit
vs Temperature
Step-Down Switching Regulator
Soft-Start
Buck-Boost Current Limit
vs Temperature
TEMPERATURE (°C)
–50
CURRENT LIMIT (A)
75 100
3589 G17
2.5
3.0
3.5
0.5
2.0
1.5
1.0
–25 0 25 50
0150125
PEAK LIMIT
CLAMP LIMIT
3589 G18
200µs/DIV
500mV/DIV
200mA/DIV
VOUT
IL
TEMPERATURE (°C)
–50
CURRENT LIMIT (A)
75 100
3589 G16
2.5
3.0
3.5
0.5
2.0
1.5
1.0
–25 0 25 50
0150125
BUCK1
BUCK2, BUCK3
BUCK2, BUCK3
(LTC3589-1/LTC3589-2)
LTC3589—1 / LT03589—2 Jusfir—J r—m LOAD CAPACITANCE = 4M NW i¥ P... V f / . __f——\ ;— ~ ' ’ ” —\__ ‘ x , —ng=la\l \ \ W 31,,” ”I 3 r"; a: l ! -— ~_‘ > | l =33v // z I i // 5 | . ’ E i 5 Q | . . . I . ___ g I! :::' . . l I LII‘IENQ
LTC3589/LTC3589-1/
LTC3589-2
11
3589fh
For more information www.linear.com/LTC3589
Typical perForMance characTerisTics
Buck-Boost Switching Regulator
Soft-Start Dynamic Voltage Slew
Step-Down Switching Regulator 1
Load Step
Buck-Boost Switching Regulator 1
Load Step
Maximum Buck-Boost Load
Current vs VIN
Step-Down Switching Regulator 1
Load Step
3589 G19
100µs/DIV
1V/DIV
500mA/DIV
VOUT
IL
3589 G20
200µs/DIV
1V/DIV
5V/DIV
5V/DIV
VOUT
VSTB
PGOOD
VRRCR = 1.75mV/µs
3589 G21
40µs/DIV
VOUT
ILOAD
LOAD CAPACITANCE = 44µF
50mV/DIV
1A/DIV
PULSE-SKIPPING MODE
3589 G22
40µs/DIV
VOUT
ILOAD
LOAD CAPACITANCE = 44µF
50mV/DIV
1A/DIV
Burst Mode OPERATION
VIN (V)
2.5
LOAD CURRENT (A)
4.0
3589 G24
1.5
0.5
3.0 3.5 4.5
0
2.5
2.0
1.0
5.0 5.5
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
3589 G23
40µs/DIV
VOUT
ILOAD
200mV/DIV
1A/DIV
LOAD CAPACITANCE = 22µF
VIN = 3.8V, TA = 25°C, unless otherwise noted.
LDO1 Dropout Voltage
vs Temperature LDO1 Output Change vs VIN
LDO1 Short-Circuit Current
vs Temperature
TEMPERATURE (°C)
–50
SHORT-CIRCUIT CURRENT (mA)
75 100
3589 G27
60
70
80
30
50
40
–25 0 25 50
20 150125
VIN (V)
2
CHANGE IN V
LDO1
(%)
3589 G26
0.0
0.5
–1.5
–0.5
–1.0
3 4
–2.0 5
VLDO1 = 25mA
VLDO1 = 1.2V
VLDO1 = 1.8V
VLDO1 = 2.8V
VLDO1 = 3.3V
TEMPERATURE (°C)
–50
DROPOUT VOLTAGE (mV)
75 100
3589 G25
400
500
100
300
200
–25 0 25 50
0150125
VLDO1 = 1.8V
VLDO1 = 3.3V
LTC3589/LT LTC3589-2 // f T k V N— I F fl
LTC3589/LTC3589-1/
LTC3589-2
12
3589fh
For more information www.linear.com/LTC3589
Typical perForMance characTerisTics
LDO2, LDO3, LDO4 Dropout
Voltage vs Temperature
LDO2, LDO3, LDO4 Dropout
Voltage vs Load Current
LDO2, LDO3, LDO4 Short-Circuit
Current vs Temperature
LDO2, LDO3, LDO4 Enable
Response
LDO2, LDO3, LDO4 Load Step
Response LDO1 Load Step Response
3589 G33
40µs/DIV
LOAD CAPACITANCE = 1µF
20mA
VLDO1
50mV/DIV
ILDO1
10mA/DIV
1mA
1.2V
3589 G32
10µs/DIV
220mA
10mA
VLDO
50mV/DIV
ILDO
100mA/DIV
1.8V
LOAD CAPACITANCE = 1µF
3589 G31
100µs/DIV
VEN_LDO2,VEN_LDO34
1V/DIV VLDO2 =1.2V
VLDO4 =2.8V
VLDO3 =1.8V
TEMPERATURE (°C)
–50
SHORT-CIRCUIT CURRENT (mA)
75 100
3589 G30
400
450
500
250
350
300
–25 0 25 50
200 150125
LOAD CURRENT (mA)
0
DROPOUT VOLTAGE (mV)
150 200
3589 G29
300
400
500
200
100
50 100
0250
VLDO = 1.2V
VLDO = 1.8V
VLDO = 3.3V
TEMPERATURE (°C)
–50
DROPOUT VOLTAGE (mV)
75 100
3589 G28
300
400
500
200
100
–25 0 25 50
0150125
VLDO = 1.2V
VLDO = 1.8V
VLDO = 3.3V
I
LOAD
= 200mA
VIN = 3.8V, TA = 25°C, unless otherwise noted.
LTC3589— 1 / LTC3589—2 L7HEJWEGR 1 3
LTC3589/LTC3589-1/
LTC3589-2
13
3589fh
For more information www.linear.com/LTC3589
pin FuncTions
VIN_LDO2 (Pin 1): Power Input for LDO2. This pin should
be bypassed to ground with a 1µF or greater ceramic
capacitor.
LDO2 (Pin 2): Output Voltage of LDO2. Nominal output
voltage is set with a resistor feedback divider that servos to
an I2C register controlled DAC reference. This pin must be
bypassed to ground with a 1µF or greater ceramic capacitor.
LDO3 (Pin 3): Output Voltage of LDO3. Nominal output
voltage is fixed at 1.8V or 2.8V (LTC3589-1/LTC3589-2).
This pin must be bypassed to ground with a 1µF or greater
ceramic capacitor.
LDO4 (Pin 4): Output Voltage of LDO4. Output voltage is
selected via the I2C port. This pin must be bypassed to
ground with a 1µF or greater ceramic capacitor.
VIN_LDO34 (Pin 5): Power Input for LDO3 and LDO4. This
pin should be bypassed to ground with a 1µF or greater
ceramic capacitor.
PVIN1 (Pin 6): Power Input for Step-Down Switching
Regulator 1. Tie this pin to VIN supply. This pin should
be bypassed to ground with a 4.7µF or greater ceramic
capacitor.
SW1 (Pin 7): Switch Pin for Step-Down Switching
Regulator 1. Connect one side of step-down switching
regulator 1 inductor to this pin.
RSTO (Pin 8): Reset Output. Open-drain output pulls low
when the always-on regulator LDO1 is below regulation
and during a hard reset initiated by a pushbutton input.
EN_LDO2 (Pin 9): Enable LDO2 Logic Input. Active high
input to enable LDO2. A weak pull-down forces EN_LDO2
low when left floating.
EN1 (Pin 10): Enable Step-Down Switching Regulator 1.
Active high input to enable step-down switching
regulator 1. A weak pull-down forces EN1 low when left
floating.
EN2 (Pin 11): Enable Step-Down Switching Regulator 2.
Active high input to enable step-down switching
regulator 2. A weak pull-down forces EN2 low when left
floating.
SW4AB (Pin 12): Switch Pin for Buck-Boost Switching
Regulator 4. Connected to the buck-boost internal power
switches A and B. Connect an inductor between this pin
and SW4CD (Pin 19).
EN3 (Pin 13): Enable Step-Down Switching Regulator 3.
Active high input to enable step-down switching
regulator 3. A weak pull-down forces EN3 low when left
floating.
EN4 (Pin 14): Enable Buck-Boost Switching Regulator 4.
Active high input to enable buck-boost switching
regulator 4. A weak pull-down forces EN4 low when left
floating.
PVIN4 (Pin 15): Power Input for Switching Regulator 4.
Tie this pin to VIN supply. This pin should be bypassed to
ground with a 4.7µF or greater ceramic capacitor.
BB_OUT (Pin 16): Output Voltage of Buck-Boost Switching
Regulator 4. This pin must be bypassed to ground with a
22µF or greater ceramic capacitor.
IRQ (Pin 17): Interrupt Request Output. Open-drain
driver is pulled low for power good, undervoltage, and
overtemperature warning and fault conditions. Clear IRQ
by writing to the I2C CLIRQ command register.
EN_LDO34 (Pin 18): LTC3589 Enable LDO3 and LDO4
Logic Input. Active high to enable LDO3 and LDO4. Disable
LDO4 via I2C software commands using I2C command
registers OVEN or L2DTV2. A weak pull-down forces
EN_LDO34 low when left floating.
EN_LDO3 (Pin 18): LTC3589-1/LTC3589-2 Enable LDO3
Logic Input. Active high to enable LDO3. A weak pull-down
forces EN_LDO3 low when left floating.
SW4CD (Pin 19): Switch Pin for Buck-Boost Switching
Regulator 4. Connected to the buck-boost internal power
switches C and D. Connect an inductor between this node
and SW4AB (Pin 12).
PWR_ON (Pin 20): External Power-On. Handshaking pin
to acknowledge successful power-on sequence. PWR_ON
must be driven high within five seconds of WAKE going
high to keep power on. It can be used to activate the WAKE
output by driving high. Drive low to shut down WAKE.
LTC3589/LT |_TC3589-2
LTC3589/LTC3589-1/
LTC3589-2
14
3589fh
For more information www.linear.com/LTC3589
pin FuncTions
ON (Pin 21): Pushbutton Input. A weak internal pull-
up forces ON high when left floating. A normally open
pushbutton is connected from ON to ground to force a
low state on this pin.
PBSTAT (Pin 22): Pushbutton Status. Open-drain output
to be used for processor interrupts. PBSTAT mirrors the
status of ON pushbutton pin. PBSTAT is delayed 50ms
from ON pin for debounce.
WAKE (Pin 23): System Wake Up. Open-drain driver output
releases high when signaled by pushbutton activation or
PWR_ON input. It may be used to initiate a pin-strapped
power-up sequence by connecting to a regulator enable pin.
PVIN2 (Pin 24): Power Input for Step-Down Switching
Regulator 2. Tie this pin to VIN supply. This pin should
be bypassed to ground with a 4.7µF or greater ceramic
capacitor.
SW2 (Pin 25): Switch Pin for Step-Down Switching
Regulator 2. Connect one side of step-down switching
regulator 2 inductor to this pin.
SW3 (Pin 26): Switch Pin for Step-Down Switching
Regulator 3. Connect one side of step-down switching
regulator 3 inductor to this pin.
PVIN3 (Pin 27): Power Input for Step-Down Switching
Regulator 3. Tie this pin to the VIN supply. This pin should
be bypassed to ground with a 4.7µF or greater ceramic
capacitor.
VSTB (Pin 28): Voltage Standby. When VSTB is low, DAC
reference registers are selected by bit values in command
register VCCR. When VSTB is high, the DAC registers are
forced xxDVT2 registers. Tie VSTB to ground if unused.
PGOOD (Pin 29): Power Good Output. Open-drain output
pulls down when any regulator falls below power good
threshold and during regulator dynamic voltage slew
unless disabled in I2C register. Pulls down when all
regulators are disabled.
SCL (Pin 30): Clock Input Pin for the I2C Serial Port. The
I2C logic levels are scaled with respect to DVDD.
SDA (Pin 31): Data Input Pin for the I2C Serial Port. The
I2C logic levels are scaled with respect to DVDD.
DVDD (Pin 32): Supply Voltage for I2C Serial Port. This
pin sets the logic reference level of SCL and SDA I2C pins.
DVDD resets I2C registers to power on state when driven to
<1V. SCL and SDA logic levels are scaled to DVDD. Connect
a 0.1µF decoupling capacitor from this pin to ground.
BUCK2_FB (Pin 33): Feedback Input for Step-Down
Switching Regulator 2. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 2 to this pin to ground.
BUCK3_FB (Pin 34): Feedback Input for Step-Down
Switching Regulator 3. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 3 to this pin to ground.
LDO1_FB (Pin 35): Feedback Input for LDO1. Set
output voltage using a resistor divider connected from
LDO1_STDBY to this pin to ground.
LDO1_STDBY (Pin 36): Always-On LDO1 Output. This pin
provides an always-on supply voltage useful for light loads
such as a watchdog microprocessor or a real-time clock.
Connect a 1µF capacitor from LDO1_STBY to ground.
VIN (Pin 37): Supply Voltage Input. This pin should
be bypassed to ground with a 1µF or greater ceramic
capacitor.
LDO2_FB (Pin 38): Feedback Input for LDO2. Set full-scale
output voltage using a resistor divider connected from
LDO2_OUT to this pin to ground.
BUCK1_FB (Pin 39): Feedback Input for Step-Down
Switching Regulator 1. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 1 to this pin to ground.
BB_FB (Pin 40): Feedback Input for Buck-Boost Switching
Regulator 4. Set the output voltage using resistor divider
connected from BB_OUT to this pin to ground.
GND (Exposed Pad Pin 41): Ground. The Exposed Pad must
be connected to a continuous ground plane on the second
layer of the printed circuit board by several interconnect
vias directly under the LTC3589 for maximum heat transfer.
LTC3589— 1 / LTC3589—2 L7HEJWEGR 1 5
LTC3589/LTC3589-1/
LTC3589-2
15
3589fh
For more information www.linear.com/LTC3589
block DiagraM
3589 BD
POWER
GOOD
1.8V, 2.5V, 2.8V, 3.3V (LTC3589)
1.2V, 1.8V, 2.5V, 3.2V (LTC3589-1/
LTC3589-2) AT 250mA
LDO1_STDBY
LDO1_FB
IRQ
ALWAYS ON LDO1
0.8V TO VIN
AT 25mA
VIN
VREF
OK
ON (PB)
PBSTAT
WAKE
PWR_ON
VSTB
EN1
EN2
EN3
EN4
EN_LDO2
CONTROL + SEQUENCE
EN_LDO34
EN_LDO3
(LTC3589-1/
LTC3589-2)
DVDD
SDA
SCL
I2C
PGOOD
n
RSTO
VIN_LDO34
LDO4
GND (EXPOSED PAD)
LDO4 VREF
OK
EN
VREF
BUCK-BOOST
PVIN4
BB_OUT
1.8V TO 5.0V
AT 1.2A
0.5V TO VIN
AT 1.6A
0.5V TO VIN
AT 1A/1.2A
0.5V TO VIN
AT 1A/1.2A
0.36V TO VIN
AT 250mA
1.8V (LTC3589)
2.8V (LTC3589-1/
LTC3589-2) AT 250mA
BB_FB
PVIN1
SW1
BUCK1_FB
PVIN2
SW2
SW3
BUCK2_FB
BUCK3_FB
PVIN3
VIN_LDO2
LDO2_FB
LDO2
LDO3
SW4AB
SW4CD
EN
OK
EN
OK
EN
OK
EN
OK
VREF
BUCK 1
VREF
BUCK 2
VREF
BUCK 3
LDO3
VREF
OK
EN
LDO2
DAC
DAC
DAC
DAC
EN-PINS
EN-I2C
VREF
OK
EN
7
LTC3589/LT |_TC3589-2
LTC3589/LTC3589-1/
LTC3589-2
16
3589fh
For more information www.linear.com/LTC3589
operaTion
INTRODUCTION
The LTC3589 is a complete power management solution
for portable microprocessors and peripheral devices. It
generates a total of eight voltage rails for supplying power
to the processor core, SDRAM, system memory, PC cards,
always-on real-time clock and HDD functions. Supplying the
voltage rails are an always-on low quiescent current 25mA
LDO, one 1.6A and two 1A (1.2A for LTC3589-1/LTC3589-
2) step-down regulators, a 1.2A buck-boost regulator,
and three 250mA low dropout regulators. Supporting
the multiple regulators is a highly configurable power-
on sequencing capability, dynamic voltage slewing DAC
output voltage control, a pushbutton interface controller,
regulator control via an I2C interface, and extensive status
and interrupt outputs.
The LTC3589 operates over an input supply range of 2.7V
to 5.5V. The input supplies for the 250mA LDO regulators
may operate as low as 1.7V to limit power loss at low
output voltages.
The always-on LDO1 provides a resistor programmable
output voltage as low as 0.8V and is capable of supplying
25mA. With only the always-on LDO active the LTC3589
draws just 8µA (typical). Always-on LDO1 will continue to
operate with VIN levels as low as 2.0V (typical) to maintain
memory and RTC function as long as possible.
Each of the 250mA LDO regulators has unique output
voltage configurations. LDO3 has a fixed 1.8V (2.8V for
LTC3589-1/LTC3589-2) output. LDO4 has four output
levels selectable via the I2C interface. Its possible outputs
are 1.8V, 2.5V, 2.8V, and 3.3V (1.2V, 1.8V, 2.5V, 3.2V for
LTC3589-1/ LTC3589-2). LDO2 has a dynamically slewing
DAC set point reference and an external feedback pin to
set the output voltage range with a resistive divider. Each
LDO draws 50µA (typical) quiescent current.
The LTC3589 includes three internally compensated
constant frequency current mode step-down switching
regulators two capable of supplying 1A of output current
and one capable of supplying 1.6A. The LTC3589-1/
LTC3589-2 step-down regulators can supply 1.2A, 1.2A,
and 1.6A. Step-down regulator switching frequencies of
2.25MHz or 1.125MHz are independently selected for each
step-down regulator using the I2C command registers.
The power-on default frequency is 2.25MHz. Each of the
step-down regulators have dynamically slewing DAC input
references and external feedback pins to set output voltage
range. The step-down regulators three operating modes,
pulse-skipping, burst, or forced continuous, are set using
the I2C interface. In pulse-skipping mode the regulator will
support 100% duty cycle. For best efficiency at low output
loads select Burst Mode operation. Forced continuous
mode minimizes output voltage ripple at light loads.
The 4-switch buck-boost DC/DC voltage mode converter
generates a user-programmable output voltage rail from
1.8V to 5V. Utilizing a proprietary switching algorithm,
the buck-boost converter maintains high efficiency and
low noise operation with input voltages that are above,
below or equal to the required output rail. The buck-boost
error amplifier uses a fixed 0.8V reference and the output
voltage is set by an external resistor divider. Burst Mode
operation is enabled through the I2C control registers. No
external compensation components are required for the
buck-boost converter.
The reference inputs for the three step-down regulators and
LDO2 are 5-bit D to A converters with up-down ramping
at selectable slew rates. The slew endpoint voltages and
select bits are stored in I2C registers for each DAC. A
select bit in the I2C command registers chooses which
register to use for each target voltage. Variable reference
slew rates from 0.88mV/µs to 7mV/µs are selectable in
the I2C register. Each of the four DACs has independent
voltage, voltage select, and slew rate control registers.
The LTC3589 is equipped with a pushbutton control circuit
that will activate the WAKE output, indicate pushbutton
status via the PBSTAT pin, and initiate a hard reset
shutdown of the regulators. Grounding the ON pin with the
pushbutton for 400ms will force the WAKE pin to release
HIGH. The WAKE pin output can be tied to the enable pin
of the first regulator in a power-on sequence. Once in the
power-on state, subsequent pushes of the button longer
than 50ms are mirrored by the PBSTAT output. Holding
ON LOW for five seconds disables all the regulators, pulls
down the WAKE pin, and pulls down RSTO for one second
to indicate to the processor that a hard reset occurred. All
regulator enables and pushbutton inputs are inhibited for
one second following the hard reset.
LTC3589— 1 / LTC3589—2 L7HEJWEGR 1 7
LTC3589/LTC3589-1/
LTC3589-2
17
3589fh
For more information www.linear.com/LTC3589
The LTC3589 has flexible options for enabling and
sequencing the regulator enables. The regulators are
enabled using input pins or the I2C serial port. To define
a power-on sequence tie the enable of the first regulator
to be powered up to the WAKE pin. Connect the first
regulators output to the enable pin of the second regulator,
and so on. One or more regulators may be started in any
sequence. Each enable pin has a 200µs (typical) delay
between the pin and the internal enable of the regulator.
When the system controllers are satisfied that power rails
are up, the controller must drive PWR_ON HIGH to keep
WAKE active. To ensure correct start-up sequencing, the
regulators outputs are monitored by voltage comparators
which require each output to discharge below 300mV before
re-enabling. A software control command register function
is available which sets the regulators to effectively ignore
their enable pins but respond to I2C register enables. This
function enables software-only control of any combination
of pin-strapped regulators and is useful for implementing
system power saving modes. Keep-alive mode exempts
selected regulators from turning off during normal
shutdown. In keep-alive mode, the LTC3589 powers down
normally and is ready for the next start-up sequence, but
selected regulators are kept on to power memory or other
functions during system standby modes.
The LTC3589 will shut down all regulators and pull down
the WAKE pin under high temperature, VIN undervoltage,
and extended low regulator output voltage conditions.
Status of a hard shutdown is reported by the IRQ status
pin and the IRQSTAT status register.
The I2C serial port on the LTC3589 contains 13 command
registers for controlling each of the regulators, one read-
only register for monitoring each regulators power good
status, one read-only register for reading the cause of
an IRQ event, and one clear IRQ command register. The
LTC3589 I2C supports random addressing of any register.
LTC3589, LTC3589-1, AND LTC3589-2 FUNCTIONAL
COMPARISON
Table 1. summarizes the functional differences between
the LTC3589, LTC3589-1, and LTC3589-2.
Table 1. LTC3589, LTC3589-1, and LTC3589-2 Functional
Differences
LTC3589 LTC3589-1 LTC3589-2
Power-On Inhibit
Enable Delay
1 second <2ms <2ms
Buck2 Current
Output
1A 1.2A 1.2A
Buck3 Current
Output
1A 1.2A 1.2A
PGOOD Fault
Timeout
Enabled by
Default. I2C
Disable.
Disabled by
Default. I2C
Enable.
Disabled by
Default. I2C
Enable.
PWR_ON to WAKE
Delay
50ms 2ms 2ms
LDO3 VOUT 1.8V 2.8V 2.8V
LDO4 VOUT
* Indicates Default
VOUT
1.8V, 2.5V,
2.8V*, 3.3V
1.2V*, 1.8V,
2.5V, 3.2V
1.2V*, 1.8V,
2.5V, 3.2V
Default LDO4
Enable
LDO34_EN Pin I2C I2C
Wait to Enable Until
Output < 300mV
Yes by Default.
I2C Select.
Yes by Default.
I2C Select.
No by Default.
I2C Select.
Insert 2k Discharge
Resistor When
Disabled
Yes if Start-Up
is Wait to Enable
Until Output <
300mV
Yes if Start-Up
is Wait to Enable
Until Output <
300mV
Always
Details of the operation of the LTC3589 are found in the
following sections.
ALWAYS-ON LDO
The LTC3589 includes a low quiescent current low dropout
regulator that remains powered whenever a valid supply
is present on VIN. The always-on LDO will remain active
until VIN drops below 2.0V (typical). This is below the 2.5V
operaTion
LTC3589/ LT LTC3589—2 18 [TH—4 L7LJCUEN2
LTC3589/LTC3589-1/
LTC3589-2
18
3589fh
For more information www.linear.com/LTC3589
undervoltage threshold in effect for the rest of the LTC3589
circuits. The always-on LDO is used to provide power to
a standby microcontroller, real-time clock, or other keep-
alive circuits. The LDO is guaranteed to support a 25mA
load. A 1µF low impedance ceramic bypass capacitor from
LDO1_STBY to GND is required for compensation. A power
good monitor pulls RSTO LOW for a minimum of 14ms
(typical) whenever LDO1_STBY is 8% below its regulation
target. An LDO1_STBY undervoltage condition is reported
in the PGOOD status register. The output voltage of LDO1
is set with a resistor divider connected from LDO1_STBY
to the feedback pin LDO1_FB, as shown in Figure 1.
VLDO1_ STBY =0.8 1+R1
R2
(V)
Typical values for R1 are in the range of 40k to 1M.
LDO1_STBY is protected from short-circuits and
overloading.
250mA LDO REGULATORS
Three LDO regulators on the LTC3589 will each deliver
up to 250mA output. The LDO regulators are enabled by
pin input or I2C command register. Pin EN_LDO2 enables
LDO2 and the LTC3589 EN_LDO34 pin enables LDO3 and
LDO4 together. An I2C command register bit is available to
decouple LDO4 from pin EN_LDO34 so that LDO4 is under
command register control only. The LTC3589-1/LTC3589-2
EN_LDO3 pin enables LDO3 only. LDO4 is controlled
using the I2C command registers. All the regulators have
operaTion
3589 F02
PVIN
0.3625V
TO 0.75V
EA
FB
LDO2
R1 1µF
R2
DAC 5
Figure 2. LDO2 Application Circuit
+
3589 F01
VIN
0.8V
LDO1_FB
LDO1_STBY
R1 1µF
R2
Figure 1. Always-On LDO Application Circuit
current limit protection circuits. Default operation for the
LTC3589 is when an LDO regulator is disabled, a 2.5k
pull-down resistor is connected to its output.
To help reduce LDO power loss in the system, the regulators
have dedicated supply inputs that may be lower than the
main VIN supply. Connect a low ESR 1µF capacitor to each
of the output pins LDO2, LDO3, and LDO4.
LDO Regulator 2
One of the LTC3589 dynamic slewing DACs serves as the
reference input of LDO2. The output range of LDO2 is set
using an external resistor divider connected from LDO2
to the feedback pin LDO2_FB, as shown in Figure 2. Set
the output voltage of LDO2 using the following formula:
VOUT =1+R1
R2
(0.3625+L2DTVx 0.0125)(V)
L2DTVx is the five bit word contained in the LDO2 dynamic
target voltage 1 (L2DTV1) or the LDO2 dynamic target
voltage 2 (L2DTV2) command registers. The default value
of L2DTVx[4-0] is 11001 to output a reference voltage of
0.675V. LDO2 is enabled by writing bit 4 in the output
voltage enable (OVEN) command register to 1 or driving
the EN_LDO2 pin high. Whenever the command is given to
slew LDO2 DAC reference to a lower voltage an integrated
2.5k pull-down resistor is connected to LDO2 output.
LTC3589— 1 / LTC3589—2 19
LTC3589/LTC3589-1/
LTC3589-2
19
3589fh
For more information www.linear.com/LTC3589
Table 2. Shows the I2C command register settings used
to control LDO2.
Table 2. LDO 2 Command Register Settings
COMMAND
REGISTER[BIT]
VALUE SETTING
OVEN[4] 0*
1
Disable
Enable
SCR2[4]
LTC3589/
LTC3589-1
0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
SCR2[4]
LTC3589-2
0*
1
Enable Immediately
Wait for Output Below 300mV Before Enable
VCCR[7] 0*
1
Select Register L2DTV1 (V1) Reference
Select Register L2DTV2 (V2) Reference
VCCR[6] 1 Initiate Dynamic Voltage Slew
VRRCR[7-6] 00
01
10
11*
Reference Slew Rate = 0.88mV/µs
Reference Slew Rate = 1.75mV/µs
Reference Slew Rate = 3.5mV/µs
Reference Slew Rate = 7mV/µs
L2DTV1[4-0] 11001* DAC Dynamic Target Voltage V1
L2DTV1[5] 0*
1
Force PGOOD Low When Slewing
Normal PGOOD Operation When Slewing
L2DTV1[7] 0*
1
Shutdown LDO2 Normally
Keep LDO2 Alive
L2DTV2[4-0] 11001* DAC Dynamic Target Voltage V2
* Denotes Default Power-On Value
LDO Regulator 3
LDO3 is a fixed 1.8V or 2.8V (LTC3589-1/LTC3589-2)
output regulator. LDO3 is enabled by driving pin EN_LDO34
or EN_LD03 high or by writing command register OVEN[5]
to 1.
Table 3 shows the I2C command register settings used
to control LDO3.
Table 3. LDO 3 Command Register Settings
COMMAND
REGISTER[BIT]
VALUE SETTING
OVEN[5] 0*
1
Disable
Enable
SCR2[5]
LTC3589
LTC3589-1
0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
SCR2[5]
LTC3589-2
0*
1
Enable Immediately
Wait for Output Below 300mV Before Enable
* Denotes Default Power-On Value
operaTion
LDO Regulator 4
LDO4 has four output voltage options that are controlled
by the contents of command register bits L2DTV2[6]
and L2DTV2[5]. When pin EN_LDO34 is low, LDO3 and
LDO4 are controlled by writing to command register
bits OVEN[5] and OVEN[6] respectively. By default, the
LTC3589 pin EN_LDO34 enables and disables LDO3
and LDO4 simultaneously when command register bits
OVEN[5] and OVEN[6] are low. When command register
bit L2DTV2[7] is high, control of LDO4 is disconnected
from pin EN_LDO34 and controlled by command register
bit OVEN[6] regardless of the status of EN_LDO34. The
LTC3589-1/LTC3589-2 pin EN_LDO3 enables only LDO3.
Control of LDO4 on the LTC3589-1/LTC3589-2 is under
I2C control only. Table 4 shows the I2C command register
settings that control LDO4.
Table 4. LTC3589 LDO4 Command Register Settings
COMMAND
REGISTER[BIT]
VALUE SETTING
OVEN[6] 0*
1
Disable
Enable
SCR2[6] 0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
L2DTV2[6-5] 00*
01
10
11
VLDO4 = 2.8V
VLDO4 = 2.5V
VLDO4 = 1.8V
VLDO4 = 3.3V
L2DTV2[7] 0*
1
LDO4 Enable Controlled by EN_LDO34
LDO4 Enable Controlled by OVEN[6]
LTC3589-1/LTC3589-2 LDO4 Command Register Settings
OVEN[6] 0*
1
Disable
Enable
SCR2[6]
LTC3589-1
0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
SCR2[6]
LTC3589-2
0*
1
Enable Immediately
Wait for Output Below 300mV Before Enable
L2DTV2[6-5] 00*
01
10
11
VLDO4 = 1.2V
VLDO4 = 1.8V
VLDO4 = 2.5V
VLDO4 = 3.2V
L2DTV2[7] 0*
1
Unused
* Denotes Default Power-On Value
LTC3589/ LT LTC3589—2 4:37 $1.
LTC3589/LTC3589-1/
LTC3589-2
20
3589fh
For more information www.linear.com/LTC3589
STEP-DOWN SWITCHING REGULATORS
Output Voltage Programming
Each of the step-down converters uses a dynamically
slewing DAC output for its reference. The full-scale output
voltage is set by using a resistor divider connected from
the step-down switching regulator output to the feedback
pins (B1_FB, B2_FB, and B3_FB), as shown in Figure 3.
Set the output voltage of step-down switching regulators
using the following formula:
VOUT =1+
R1
R2
(0.3625+BxDTVx 0.0125)(V)
BxDTVx is the decimal value of the five bit binary number
in the I2C BxDTV1 or BxDTV2 command registers. BxDTV1
and BxDTV2 default to 11001 to output a reference voltage
of 0.675V. Typical values for R1 are in the range of 40k
to 1M. The capacitor CFB cancels the pole created by the
feedback resistors and the input capacitance on the FB pin
and also helps to improve load step transient response.
A value of 10pF is recommended for most applications.
Experimentation with capacitor sizes between 10pF and
33pF may yield improved transient response.
Operating Modes
The step-down switching regulators include three possible
operating modes to meet the noise and power needs of a
variety of applications.
In pulse-skipping mode, at the start of every cycle, a latch
is set that turns on the main P-channel MOSFET switch.
During the cycle, a current comparator compares the peak
inductor current to the output of an error amplifier. The
output of the current comparator resets the latch. At this time
the P-channel MOSFET switch turns off and the N-channel
MOSFET synchronous rectifier turns on. The N-channel
MOSFET synchronous rectifier will turn off when the end of
the clock cycle is reached or if the inductor current drops
through zero. Using this method of operation, the error
amplifier adjusts the peak inductor current to deliver the
required output power. All necessary loop compensation
is internal to the step-down switching regulator requiring
only a single ceramic output capacitor for stability. At light
loads in pulse-skipping mode, the inductor current may
reach zero on each pulse that will turn off the N-channel
MOSFET synchronous rectifier. In this case the switch
node (SW1, SW2, or SW3) goes HIGH impedance and the
switch node will ring. This is discontinuous operation and
is normal behavior for a switching regulator. At very light
loads in pulse-skipping mode, the step-down switching
regulators will automatically skip pulses as needed to
maintain output regulation. At high duty cycle (VOUTX >
VIN/2) it is possible for the inductor current to reverse at
light loads causing the step-down switching regulator
to operate continuously. When operating continuously,
regulation and low noise output voltage are maintained,
but input operating current will increase to a few milliamps.
In the forced continuous mode of operation, the inductor
current is allowed to be less than zero over the full range
of duty cycles. Operating in forced continuous mode is
a lower noise option at light loads than pulse-skipping
operation but with the drawback of higher VIN current
due to the continuous operation of the MOSFET switch
operaTion
Figure 3. Step-Down Switching Regulator
Application Circuit
3589 F03
PVIN
PWM
CONTROL
0.3625V
TO 0.75V
SW
FB
L1
EN
MODE
R1
COUT
R2
CFB
DAC
5
LTC3589— 1 / LTC3589—2 L7 LJUW 2 1
LTC3589/LTC3589-1/
LTC3589-2
21
3589fh
For more information www.linear.com/LTC3589
and rectifier. Since the inductor current is allowed to be
negative in forced continuous operation the step-down
switching regulator has the ability to sink output current.
The LTC3589 automatically forces the step-down switching
regulator into forced continuous mode when dynamically
slewing the DAC voltage reference down.
When the LTC3589 step-down switching regulators are in
Burst Mode operation, they automatically switch between
fixed frequency pulse-skipping operation and hysteretic
Burst Mode control as a function of the load current. At
light loads the step-down switching regulators control
the inductor current directly and use a hysteretic control
loop to minimize both noise and switching losses. While
in Burst Mode operation, the output capacitor is charged
to a voltage slightly higher than the regulation point. The
step-down switching regulator then goes into a low power
sleep mode during which the output capacitor provides
the load current. In sleep mode, most of the switching
regulator’s circuitry is powered off to conserve battery
power. When the output voltage drops below the regulation
point the regulator’s circuitry is powered on and another
burst cycle begins. As the load current increases, the time
between burst cycles decreases. Above a load current about
one-quarter rated output load, the step-down switching
regulators will switch to low noise constant-frequency
PWM operation.
Set the mode of operation for the step-down switching
regulators by using the I2C command register SCR1. Each
of the three regulators has independent mode control.
A step-down switching regulator may enter a dropout
condition when its input voltage drops to near its
programmed output voltage. For example, a discharging
battery voltage of 3.4V dropping to the regulators
programmed output voltage of 3.3V. When this happens
the duty cycle of the P-channel MOSFET switch is increased
until it turns on continuously with 100% duty cycle. In
dropout, the regulators output voltage equals the regulators
input voltage minus the voltage drops across the internal
P-channel MOSFET and the inductor DC resistance.
operaTion
Table 5, Table 6, and Table 7 show the I2C command
register settings used to control the step-down switching
regulators.
Table 5. Step-Down Switching Regulator 1 Command Register
Settings
COMMAND
REGISTER[BIT]
VALUE SETTING
SCR1[1-0] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
OVEN[0] 0*
1
Disable
Enable
SCR2[0]
LTC3589/
LTC3589-1
0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
SCR2[0]
LTC3589-2
0*
1
Enable Immediately
Wait for Output Below 300mV Before Enable
VCCR[1] 0*
1
Select Register B1DTV1 (V1) Reference
Select Register B1DTV2 (V2) Reference
VCCR[0] 1 Initiate Dynamic Voltage Slew
VRRCR[1-0] 00
01
10
11*
Reference Slew Rate = 0.88mV/µs
Reference Slew Rate = 1.75mV/µs
Reference Slew Rate = 3.5mV/µs
Reference Slew Rate = 7mV/µs
B1DTV1[5] 0*
1
Force PGOOD Low When Slewing
Normal PGOOD Operation When Slewing
B1DTV1[4-0] 11001* DAC Dynamic Target Voltage V1
B1DTV2[4-0] 11001* DAC Dynamic Target Voltage V2
B1DTV2[5] 0*
1
2.25MHz Switching Frequency
1.125MHz Switching Frequency
B1DTV2[6] 0*
1
Switch on Clock Phase 1
Switch on Clock Phase 2
B1DTV2[7] 0*
1
Shutdown Regulator 1 Normally
Keep Regulator 1 Alive
* Denotes Default Power-On Value
Soft-Start
Soft-start is accomplished by gradually increasing the
input reference voltage on each step-down switching
regulator from 0V to the dynamic reference DAC output
level at a rate of 0.8V/ms. This allows each output to
rise slowly, helping minimize inrush current required to
charge up the regulator output capacitor. A soft-start cycle
LTC3589/ LT LTC3589—2
LTC3589/LTC3589-1/
LTC3589-2
22
3589fh
For more information www.linear.com/LTC3589
occurs whenever a regulator is enabled either initially or
while powering up following a fault condition. A soft-start
cycle is not triggered by a change of operating modes or
a dynamic voltage slew. During soft-start the converter is
forced to pulse-skipping mode regardless of the settings
in the SCR1 command register.
Table 6. Step-Down Switching Regulator 2 Command Register
Settings
COMMAND
REGISTER[BIT]
VALUE SETTING
SCR1[3-2] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
OVEN[1] 0*
1
Disable
Enable
SCR2[1]
LTC3589/
LTC3589-1
0*
1
Wait for Output Below 300mV Before Enable
Enable immediately
SCR2[1]
LTC3589-2
0*
1
Enable immediately
Wait for Output Below 300mV Before Enable
VCCR[3] 0*
1
Select Register B2DTV1 (V1) Reference
Select Register B2DTV2 (V2) Reference
VCCR[2] 1 Initiate Dynamic Voltage Slew
VRRCR[3-2] 00
01
10
11*
Reference Slew Rate = 0.88mV/µs
Reference Slew Rate = 1.75mV/µs
Reference Slew Rate = 3.5mV/µs
Reference Slew Rate = 7mV/µs
B2DTV1[5] 0*
1
Force PGOOD Low When Slewing
Normal PGOOD Operation When Slewing
B2DTV1[4-0] 11001* DAC Dynamic Target Voltage V1
B2DTV2[4-0] 11001* DAC Dynamic Target Voltage V2
B2DTV2[5] 0*
1
2.25MHz Switching Frequency
1.125MHz Switching Frequency
B2DTV2[6] 0*
1
Switch on Clock Phase 1
Switch on Clock Phase 2
B2DTV2[7] 0*
1
Shutdown Regulator 2 Normally
Keep Regulator 2 Alive
* Denotes Default Power-On Value
Switching EMI Control
The step-down switching regulators contain new patent
pending circuitry to limit the edge rate of the switch
nodes SW1, SW2, and SW3. This new circuitry controls
the transition of the switch node over a period of a few
nanoseconds, significantly reducing radiated EMI and
conducted supply noise while maintaining high efficiency.
operaTion
Since slowing the slew rate of the switch nodes causes
efficiency loss, the slew rate of the step-down switching
regulators is adjustable using the I2C command register
B1DTV1 bits 6 and 7. Optimize efficiency or EMI as
necessary with four different slew rate settings. The power-
on default is the fastest slew rate, highest efficiency setting.
Table 7. Step-Down Switching Regulator 3 Command Register
Settings
COMMAND
REGISTER[BIT]
VALUE SETTING
SCR1[5-4] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
OVEN[2] 0*
1
Disable
Enable
SCR2[2]
LTC3589/
LTC3589-1
0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
SCR2[2]
LTC3589-2
0*
1
Enable Immediately
Wait for Output Below 300mV Before Enable
VCCR[5] 0*
1
Select Register B3DTV1 (V1) Reference
Select Register B3DTV2 (V2) Reference
VCCR[4] 1 Initiate Dynamic Voltage Slew
VRRCR[5-4] 00
01
10
11*
Reference Slew Rate = 0.88mV/µs
Reference Slew Rate = 1.75mV/µs
Reference Slew Rate = 3.5mV/µs
Reference Slew Rate = 7mV/µs
B3DTV1[5] 0*
1
Force PGOOD Low When Slewing
Normal PGOOD Operation When Slewing
B3DTV1[4-0] 11001* DAC Dynamic Target Voltage V1
B3DTV2[4-0] 11001* DAC Dynamic Target Voltage V2
B3DTV2[5] 0*
1
2.25MHz Switching Frequency
1.125MHz Switching Frequency
B3DTV2[6] 0*
1
Switch on Clock Phase 1
Switch on Clock Phase 2
B3DTV2[7] 0*
1
Shutdown Regulator 3 Normally
Keep Regulator 3 Alive
* Denotes Default Power-On Value
Operating Frequency
The switching frequency of each of the LTC3589 step-
down switching regulators may be independently set using
I2C command register bits B1DTV2[5], B2DTV2[5] and
B3DTV2[5]. The power-on default frequency is 2.25MHz.
Writing bit BxDTV2[5] HIGH will reduce the switching
frequency to 1.125MHz. Selection of the operating
LTC3589— 1 / LTC3589—2 L7HEJWEGR 23
LTC3589/LTC3589-1/
LTC3589-2
23
3589fh
For more information www.linear.com/LTC3589
operaTion
frequency is determined by desired efficiency, component
size and converter duty cycle.
Operation at lower frequency improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance and capacitance values for
comparable output ripple voltage. The lowest duty cycle
of the step-down switching regulator is determined by
the converters minimum on-time. Minimum on-time is
the shortest time duration that the converter is capable of
turning its top PMOS on and off again. The time consists
of the gate charge time plus internal delays associated
with peak current sensing. The minimum on-time of the
LTC3589 is approximately 90ns. If the duty cycle falls
below what can be accommodated by the minimum on-
time, the converter will begin to skip cycles. The output
voltage will continue to be regulated but the ripple voltage
and current will increase. With the switching frequency
set to 2.25MHz, the minimum supported duty cycle is
20%. Switching at 1.125MHz the converter can support
a 10% duty cycle.
Phase Selection
To reduce the cycle by cycle peak current drawn by the
switching regulators, the clock phase of each of the
LTC3589 step-down switching regulators can be set using
I2C command register bits B1DTV2[6], B2DTV2[6] and
B3DTV2[6]. The internal full-rate clock has a nominal
duty cycle of 20% while the half-rate clocks have a 50%
duty cycle. Setting the command register bits high will
delay the start of each converter switching cycle by 20%
or 50% depending on the selected operating frequency.
Inductor Selection
The choice of step-down switching regulator inductor
influences the efficiency of the converter and the magnitude
of the output voltage ripple. Larger inductance values
reduce inductor current ripple and therefore lower output
voltage ripple. A larger value inductor improves efficiency
by lowering the peak current to be closer to the average
output current. Larger inductors, however, generally
have higher series resistance that counters the efficiency
advantage of reduced peak current.
Inductor ripple current is a function of switching frequency,
inductance, VIN, and VOUT, as shown in this equation:
ΔIL=1
fLVOUT 1VOUT
VIN
In an example application the LTC3589 step-down
switching regulator 3 has a maximum load of 1A, VIN
equals 3.8V, and VOUT is set for 1.2V. A good starting
design point for inductor ripple is 30% of output current
or 300mA. Using the equation for ripple current, a 1.2µH
inductor should be selected.
An inductor with low DC resistance will improve converter
efficiency. Select an inductor with a DC current rating at least
1.5 times larger than the maximum load current to ensure
the inductor does not saturate during normal operations.
If short-circuit is a possible condition, the inductor should
be rated to handle the maximum peak current specified
for the step-down converter. Table 8 shows inductors
that work well with the step-down switching regulators.
Input/Output Capacitor Selection
Low ESR (equivalent series resistance) ceramic capacitors
should be used at both the output and input supply of the
switching regulators. Only X5R or X7R ceramic capacitors
should be used because they retain their capacitance over
wider voltage and temperature ranges than other ceramic
types. A 22µF capacitor is sufficient for the step-down
switching regulator outputs. For good transient response
and stability the output capacitor should retain at least
10µF of capacitance over operating temperature and bias
voltage. Place at least 4.7µF decoupling capacitance as
close as possible to each PVIN pin. Refer to Table 12 for
recommended ceramic capacitor manufacturers.
LTC3589/LT |_TC3589-2
LTC3589/LTC3589-1/
LTC3589-2
24
3589fh
For more information www.linear.com/LTC3589
operaTion
BUCK-BOOST SWITCHING REGULATOR
Output Voltage Programming
Set the output voltage of the LTC3589 buck-boost switching
regulator using an external resistor divider connected
from BB_OUT to the feedback pin BB_FB and to GND, as
shown in Figure 4.
VBB _ OUT =0.8 1+R1
R2
(V)
The value of R1 plays a role in setting the dynamics of
the buck-boost voltage mode control loop. In general, a
larger value for R1 will increase stability but reduce the
speed of the transient response. A good starting point is
to choose R1 equal to 1MΩ and calculate the value of R2
needed to set the target output voltage. If a large output
capacitor is used, the bandwidth of the converter is reduced
and R1 may be reduced to improve transient response. If
a large inductor or small output capacitor is used then a
larger R1 should be used to bring the loop toward more
stable operation.
Table 8. Inductors for Step-Down Switching Regulator 1
MANUFACTURERS
PART NUMBER
VALUE
(µH)
DCR ()
MAX DC
CURRENT (A)
SIZE (mm) W × L × H
Coilcraft XPL4020-102ML
XPL4020-152ML
XPL4020-222ML
LPS6225-222ML
LPS6225-332ML
LPS6225-472ML
1.0
1.5
2.2
2.2
3.3
4.7
0.029
0.036
0.060
0.045
0.055
0.065
4.00
3.60
2.60
3.90
3.50
3.00
4.2 × 4.2 × 2.0
4.2 × 4.2 × 2.0
4.2 × 4.2 × 2.0
6.0 × 6.0 × 2.0
6.0 × 6.0 × 2.0
6.0 × 6.0 × 2.0
Cooper SD14-1R2-R
SD14-1R5-R
SD14-2R0-R
SD25-2R2-R
1.2
1.5
2.0
2.2
0.034
0.039
0.045
0.031
3.35
2.91
2.56
2.80
5.2 × 5.2 × 1.45
5.2 × 5.2 × 1.45
5.2 × 5.2 × 1.45
5.2 × 5.2 × 2.5
Sumida CDRH5D16NP-3R3N 3.3 0.045 2.60 5.6 × 5.6 × 1.8
TDK VLF5014ST- 1R0N2R7
VLF5014st-2R2N2R3
VLCF5020T-2R2N2R6-1
1.0
2.2
2.2
0.050
0.073
0.071
2.7
2.3
2.6
4.8 × 4.6 × 1.4
4.8 × 4.6 × 1.4
5.0 × 5.0 × 2.0
TOKO 1124BS-1R2N
1124BS-1R8N
1.2
1.8
0.047
0.056
2.9
2.7
4.5 × 4.7 × 1.8
4.5 × 4.7 × 1.8
Tokin H-DI-0520-2R2
H-DI-0630-2R4
H-DI-0630-3R8
2.2
2.4
3.8
0.048
0.028
0.040
2.6
2.5
2
5.3 × 5.3 × 2.0
6.3 × 6.3 × 3.0
6.3 × 6.3 × 3.0
Wurth 744042001
744052002
744053003
7440530047
7440430022
1.0
2.5
3.0
4.7
2.2
0.028
0.030
0.024
0.030
0.023
2.60
2.4
2.8
2.4
2.5
4.8 × 4.8 × 1.8
5.8 × 5.8 × 1.8
5.8 × 5.8 × 2.8
5.8 × 5.8 × 2.8
4.8 × 4.8 × 2.8
LTC3589— 1 / LTC3589—2 —_L _|_ ”FHLJH— ""IH'lu _T T MODE "d III—4M .||—| E5 L7HEJWEGR 25
LTC3589/LTC3589-1/
LTC3589-2
25
3589fh
For more information www.linear.com/LTC3589
Table 9. Inductors for Step-Down Switching Regulators 2 and 3
MANUFACTURERS
PART NUMBER
VALUE
(µH)
DCR ()
MAX DC
CURRENT (A)
SIZE (mm) W × L × H
Coilcraft XPL4020-102ML
XPL4020-152ML
XPL4020-472ML
1.0
1.5
4.7
0.029
0.036
0.130
4.00
3.60
1.90
4.2 × 4.2 × 2.0
4.2 × 4.2 × 2.0
4.2 × 4.2 × 2.0
Cooper SD14-1R2-R
SD14-3R2-R
SD25-3R3-R
1.2
3.2
3.3
0.034
0.066
0.038
3.35
2.00
2.21
5.2 × 5.2 × 1.45
5.2 × 5.2 × 1.45
4.8 × 4.8 × 2.5
Sumida CDRH5D16NP-4R7N
CDRH38D16RHPNP-3R3M
4.7
3.3
0.064
0.059
2.05
1.46
5.6 × 5.6 × 1.8
4.2 × 4.2 × 1.8
TDK VLF5014ST- 2R2N2R3
VLCF5020T-2R7N2R2-1
VLCF5020T-3R3N2R0-1
2.2
2.7
3.3
0.073
0.083
0.096
2.3
2.2
2
4.8 × 4.6 × 1.4
5.0 × 5.0 × 2.0
5.0 × 5.0 × 2.0
TOKO 1124BS-2R4N
1124BS-3R3N
2.4
3.3
0.065
0.074
2.30
2.10
4.5 × 4.7 × 1.8
4.5 × 4.7 × 1.8
Tokin H-DI-0520-3R3
H-DI-0520-4R7
H-DI-0630-3R8
H-DI-0630-4R7
3.3
4.7
3.8
4.7
0.062
0.090
0.040
0.043
2.00
1.80
2.00
1.90
5.3 × 5.3 × 2.0
5.3 × 5.3 × 2.0
6.3 × 6.3 × 3.0
6.3 × 6.3 × 3.0
Wurth 744043004
744052002
7440530047
744042003
7440430022
4.7
2.5
4.7
3.3
2.2
0.052
0.030
0.030
0.055
0.023
1.55
2.4
2.4
1.95
2.5
5.0 × 5.0 × 3.0
5.8 × 5.8 × 1.8
5.8 × 5.8 × 2.8
4.8 × 4.8 × 1.8
4.8 × 4.8 × 2.8
operaTion
Figure 4. Buck-Boost Switching Regulator Application Circuit
3589 F04
PVIN4 BB_OUTSW4AB SW4CD
A
B C
D
PWM
CONTROL
0.8V
EN
MODE
BB_FB
R1 22µF
R2
+
LTC3589/ LT LTC3589—2 0.28'VIN 26 L7ELUEN2
LTC3589/LTC3589-1/
LTC3589-2
26
3589fh
For more information www.linear.com/LTC3589
Operating Modes
Table 10 shows the I2C command registers used to
control the operating modes of the LTC3589 buck-boost
converter. When command register SCR1 bit 6 is LOW,
the LTC3589 buck-boost switching regulator operates
in a fixed frequency pulse width modulation mode using
voltage mode feedback control. A proprietary switching
algorithm allows the converter to transition between
buck, buck-boost, and boost modes without discontinuity
in inductor current or loop characteristics. The switch
topology is shown in the application circuit in Figure 4.
When the input voltage is significantly greater than the
output voltage, the buck-boost converter operates in
buck mode. Switch D turns on continuously and switch C
remains off. Switches A and B are pulse width modulated
to produce the required duty cycle to support the output
regulation voltage. As the input voltage decreases, switch A
remains on for a larger portion of the switching cycle.
When the duty cycle reaches approximately 85%, the
switch pair AC begins turning on for a small fraction of the
switching period. As the input voltage decreases further,
the AC switch pair remains on for longer durations and
the duration of the BD phase decreases proportionately.
As the input voltage drops below the output voltage, the
AC phase will eventually increase to the point that there is
no longer any BD phase. At this point, switch A remains
on continuously while switches CD operate as a boost
converter to regulate the desired output voltage.
The buck-boost is set to Burst Mode operation by writing
a 1 to command register SCR1 bit 6. Using Burst Mode
operation at light loads improves efficiency and reduces
standby current at zero loads. In Burst Mode operation,
the inductor is charged with bursts of fixed peak amplitude
current pulses. The current pulses are repeated as often
as necessary to maintain the target output voltage. The
maximum output current that can be supplied in Burst Mode
operation is dependent upon the input and output voltage.
Typically IOUT(MAX) in Burst Mode operation is equal to:
IOUT(MAX) =
0.28 V
IN
VBB _ OUT +VIN
(A)
operaTion
If the buck-boost load exceeds the maximum Burst Mode
current capability then the output rail will lose regulation and
the power good comparator will indicate a fault condition.
When the LTC3589 buck-boost is not enabled, a 2.5k pull-
down resistor is connected between BB_OUT and ground.
Soft-Start
The buck-boost converter has an internal voltage mode
soft-start circuit that ramps the buck-boosts error amp
reference from 0V to 800mV at a rate of 2V/ms. During
soft-start, the converter is regulating to the ramping
reference and will respond to output load transients.
During soft-start the buck-boost converter is forced into
continuous mode operation regardless of the state of the
SCR1 command register.
Current Limit Operation
The LTC3589 buck-boost regulator has current limit
circuits to limit forward current through the A switch and
reverse current through the D switch. The primary forward
current limit circuit injects a small fraction of the induc-
tor current into the feedback node whenever the inductor
current exceeds 2.7A (typical). Forcing the current into
the feedback node in the high gain feedback circuit has
the effect of lowering the output voltage until the aver-
age current in switch A is equal to the current limit. The
average limit uses the error amplifier in its active linear
state so once the fault condition is removed the recovery
is smooth with little overshoot.
A hard short on the output of the buck-boost will cause the
inductor current to exceed the 2.7A average current limit.
A second current limit turns off switch A in the event peak
inductor current reaches 3A (typical). The instantaneous
forward current limit provides extra protection in the event
of a sudden hard short.
The reverse current comparator on the D switch moni-
tors the current entering the BB_OUT pin. When this
current exceeds 1A (typical) switch D will turn off for the
remainder of the switching cycle. This feature protects
the buck-boost converter from excessive reverse current
if the buck-boost output is held above the regulation point
by an external source.
LTC3589— 1 / LTC3589—2 27
LTC3589/LTC3589-1/
LTC3589-2
27
3589fh
For more information www.linear.com/LTC3589
Table 11. Inductors for Buck-Boost Switching Regulator
MANUFACTURERS
PART
NUMBER
VALUE
(µH)
DCR ()
MAX DC
CURRENT (A)
SIZE (mm) W × L × H
Coilcraft XFL4020-152ME
XFL4020-222ME
XFL4020-332ME
LPS6225-332ML
LPS6225-472ML
1.5
2.2
3.3
3.3
4.7
0.014
0.021
0.035
0.055
0.065
4.10
3.10
2.70
3.50
3.00
4.0 × 4.0 × 2.1
4.0 × 4.0 × 2.1
4.0 × 4.0 × 2.1
6.0 × 6.0 × 2.0
6.0 × 6.0 × 2.0
Cooper SD14-1R5-R
SD14-2R0-R
SD14-2R5-R
SD14-3R2-R
SD25-3R3-R
1.5
2.0
2.5
3.2
3.3
0.039
0.045
0.060
0.066
0.038
2.91
2.56
2.29
2.00
2.21
5.2 × 5.2 × 1.45
5.2 × 5.2 × 1.45
5.2 × 5.2 × 1.45
5.2 × 5.2 × 1.45
4.8 × 4.8 × 2.5
Sumida CDRH5D16NP-3R3N
CDRH5D16NP-4R7N
3.3
4.7
0.045
0.064
2.60
2.05
5.6 × 5.6 × 1.8
5.6 × 5.6 × 1.8
TDK VLF5014ST- 2R2N2R3
VLCF5020T-2R7N2R2-1
VLCF5020T-3R3N2R0-1
2.2
2.7
3.3
0.073
0.083
0.096
2.3
2.2
2
4.8 × 4.6 × 1.4
5.0 × 5.0 × 2.0
5.0 × 5.0 × 2.0
TOKO 1124BS-1R8N
1124BS-3R3N
1.8
3.3
0.056
0.074
2.70
2.10
4.5 × 4.7 × 1.8
4.5 × 4.7 × 1.8
Tokin H-DI-0520-3R3
H-DI-0630-3R8
3.3
3.8
0.062
0.040
2.00
2.00
5.3 × 5.3 × 2.0
6.3 × 6.3 × 3.0
Wurth 744052002
7440420027
744053003
7440530047
2.5
2.7
3.0
4.7
0.030
0.047
0.024
0.030
2.4
2.2
2.8
2.4
5.8 × 5.8 × 1.8
4.8 × 4.8 × 1.8
5.8 × 5.8 × 2.8
5.8 × 5.8 × 2.8
Inductor Selection
Inductor selection criteria for the buck-boost are similar to
those given for the step-down switching regulators. The
buck-boost converter is designed to work with inductors
in the range of 1µH to 3.3µH. For most applications use a
1.5µH inductor. Choose an inductor with a DC current rating
at least two times larger than the maximum load current to
ensure that the inductor does not saturate during normal
operation. If output short-circuit is a possible condition,
the inductor should be rated to handle the maximum peak
current specified for the buck-boost converter. Table 11
shows several inductors that work well with the LTC3589
buck-boost regulator.
Table 10. Buck-Boost Command Register Settings
COMMAND
REGISTER[BIT]
VALUE SETTING
SCR1[6] 0*
1
Continuous Mode
Burst Mode Operation
OVEN[3] 0*
1
Disable
Enable
SCR2[3]
LTC3589/
LTC3589-1
0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
SCR2[3]
LTC3589-2
0*
1
Enable Immediately
Wait for Output Below 300mV Before Enable
* Denotes Default Power-On Value
operaTion
LTC3589/ LT LTC3589—2 28 L7ELUEN2
LTC3589/LTC3589-1/
LTC3589-2
28
3589fh
For more information www.linear.com/LTC3589
Table 13. Slewing DAC Command Register Control Summary
COMMAND
REGISTER[BIT]
FUNCTION
VCCR[0], VCCR[2],
VCCR[4], VCCR[6]
Voltage Change Control Register
G0 / Slew
Write a 1 to Initiate a Slew to the Voltage
Selected in VCCR[1], VCCR[3], VCCR[5],
VCCR[7] Respectively.
Bits are Reset to 0 at the End of the Slew
Operation.
VCCR[1], VCCR[3],
VCCR[5], VCCR[7]
Voltage Change Control Register
Dynamic Target Select
Write a 0 to Select Voltage V1 Stored in
Registers B1DTV1[4-0], B2DTV1[4-0],
B3DTV1[4-0], L2DTV1[4-0].
Write a 1 to Select Voltage V2 in Registers
B1DTV2[4-0], B2DTV2[4-0], B3DTV2[4-0],
L2DTV2[4-0].
B1DTV1[4-0], B2DTV1[4-0],
B3DTV1[4-0], L2DTV1[4-0]
Dynamic Target Voltage 1
Five Bits Corresponding to V1 Output from
Each DAC.
B1DTV1[5], B2DTV1[5],
B3DTV1[5], L2DTV1[5]
PGOOD Mask
Write a 1 to Continue Normal PGOOD
Operation When Slewing.
Write a 0 to Force PGOOD to Pull Low
During Slew.
B1DTV2[4-0], B2DTV2[4-0],
B3DTV2[4-0], L2DTV2[4-0]
Dynamic Target Voltage 2
Five Bits Corresponding to V2 Output from
Each DAC.
VRRCR[1-0], VRRCR[3-2],
VRRCR[5-4], VRRCR[7-6]
Voltage Ramp Rate Control
Two Bits That Set the DAC Output Slew
Rate for Step-Down Switching Regulator
and LDO2.
Setting and Slewing the DAC Outputs
The 5-bit word in dynamic target voltage command reg-
isters B1DTV1, B2DTV1, B3DTV1, and L2DTV1 programs
reference voltage V1. The 5-bit word in command registers
B1DTV2, B2DTV2, B3DTV2, and L2DTV2 programs refer-
ence voltage V2. A resistor divider network on the output
and feedback pins of the regulators set their output voltage.
Capacitor Selection
Low ESR ceramic capacitors should be used at both the
output and input supply of the buck-boost switching
regulator. Only X5R or X7R ceramic capacitors should
be used because they retain their capacitance over wider
voltage and temperature ranges than other ceramic types.
A 22µF capacitor is sufficient for the buck-boost switch-
ing regulator output. For good transient response and
stability the output capacitor should retain at least 10µF of
capacitance over operating temperature and bias voltage.
Place at least 4.7µF decoupling capacitance as close as
possible to PVIN4 pin. Refer to Table 12 for recommended
ceramic capacitor manufacturers.
Table 12. Ceramic Capacitor Manufacturers
AVX www.avxcorp.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
Vishay Siliconix www.vishay.com
TDK www.tdk.com
SLEWING DAC REFERENCE OPERATION
Controlling the DAC References
The three LTC3589 step-down switching regulators and
linear regulator LDO2 have programmable DAC reference
inputs. Each DAC is programmable from 0.3625V to 0.75V
in 12.5mV steps:
VOUT =1+R1
R2
(0.3625+BxDTVx 0.0125)(V)
The DAC references may be commanded to independently
slew between two voltages at one of four selectable slew
rates. Table 13 summarizes the command registers used
to control slewing DAC operation.
operaTion
L7 LJUW LTC3589— 1 / LTC3589—2 29
LTC3589/LTC3589-1/
LTC3589-2
29
3589fh
For more information www.linear.com/LTC3589
Figure 5. Pushbutton Controller State Diagram
operaTion
Writing a 0 or 1 to the odd bits of voltage change control
register VCCR selects DAC output voltages V1 or V2,
respectively. A slew of the DAC is initiated by writing a 1
to an even bit of register VCCR. The DAC output will slew
to either voltage, V1 or V2, as selected by the odd bits of
register VCCR. Slew begins when the I2C STOP condition
is detected. At the end of the slewing operation the GO
bits in command register VCCR are cleared.
The slew rate for each regulator is set in the ramp rate
control register VRRCR. Each DAC has independent output
voltage registers, voltage register select, and slew rate and
start controls. The regulators do not have to be enabled
to change the DAC outputs.
The VSTB pin is used to set the DAC controlled output rails
to a low power standby condition. When VSTB is driven
HIGH, all four of the DAC references will immediately slew
to V2. To use VSTB to set the rails to standby voltage,
select V1 for normal rail voltages and V2 for standby rail
voltages. Drive VSTB high to immediately slew all the
DAC outputs to V2. When VSTB is driven LOW, the DAC
outputs will slew to V1.
The default power-up value of all the dynamic target voltage
registers is 11001 corresponding to a DAC output volt-
age of 0.675V. The DTV registers may be reprogrammed
prior to initiating a power-up sequence or at any time for
dynamic slewing.
When a step-down switching regulator output is slewing
down its mode is automatically switched to forced continu-
ous to enable the regulator to sink current. When LDO2 is
slewing down, a 2.5k pull-down is connected to its output.
Table 14 shows command register and feedback divider
settings to enable slewing step-down switching regulator 1
between 1.2V and 1V in 70µs. The voltage ramp rate
control register bits VRRCR[1:0] are set to 01 which selects
a ramp rate of 1.75mV/µs at the DAC output. The slew rate
at the regulator output is a function of the feedback resistor
divider gain. In this example, the slew is equal to 1.75 (1
+ 301/499) = 2.8mV/µs. Therefore, a slew of 200mV will
take 70µs. To initiate a change from 1.2V to 1V write 11 to
voltage change control register bits VCCR[1:0]. VCCR[1]
selects target register B1DTV2 to set the regulator reference
input to 0.625V. VCCR[0] set to 1 initiates the dynamic
slew to go to the new voltage. To slew back to 1.2V write
01 to command register bits VCCR[1:0].
Table 14. Dynamic Slewing Example for Step-Down Switching
Regulator 1
COMMAND
REGISTER
VOUT =1.2V VOUT =1V
VRRCR[1:0] 01 01 Dynamic Slew Rate
VCCR[1] 0 1 Select DTV
B1DTV1[4:0] 11111 11111 Resistor Divider Shown
in Figure 3
R1 = 301kΩ
R2 = 499kΩ
B1DTV2[4:0] 10101 10101
PUSHBUTTON OPERATION
State Event Diagram
Figure 5 shows the LTC3589 pushbutton state diagram.
Upon the first power application to the LTC3589 VIN pin an
internal power-on reset circuit puts the pushbutton into the
power-down (PDN) state and initiates a one second timer.
The LTC3589 status pin RSTO is pulled low until one second
times out and the always-alive LDO1 is indicating power
good status. After the one second interval the pushbutton
circuit will transition to the power-off (POFF) standby state.
The LTC3589-1/LTC3589-2 powers on directly to the POFF
state bypassing the one second delay. Status pin RSTO will
be released high when LDO1 indicates power good status.
The LTC3589 will not leave the POFF state and enter the
power-up state (PUP) until ON is held LOW for at least
1 SEC
POR
5 SEC
LTC3589 LTC3589-1/LTC3589-2
ON OR
PWR_ON
FAULT OR
PWR_ON OR
HARD RESET
PUP
PONPOFF
PDN
1 SEC
POR
3589 F05
5 SEC
ON OR
PWR_ON
FAULT OR
PWR_ON OR
HARD RESET
PUP
PONPOFF
PDN
LTC3589/ LT LTC3589—2 3O L7ELUEN2
LTC3589/LTC3589-1/
LTC3589-2
30
3589fh
For more information www.linear.com/LTC3589
operaTion
400ms (PB400ms) or until PWR_ON is activated by the
PWR_ON pin. When the controller enters the PUP state
the open-drain WAKE pin releases HIGH. The WAKE pin
is typically used to enable the first regulator in a start-up
sequence. The pushbutton state will stay in PUP for five
seconds before transitioning to the power-on (PON) state.
Before leaving PUP, the PWR_ON pin must be brought
HIGH by the application to indicate that the system rails
are correct. If PWR_ON is not active at the end of five
seconds the pushbutton controller will continue directly
through PON to the power-down (PDN) state and pull the
WAKE pin down. Three events will cause the pushbutton
to leave the PON state: 1) lowering the PWR_ON pin, 2)
forcing a hard reset by holding the ON pin LOW for five
seconds, and 3) a fault condition is detected. Fault condi-
tions are low VIN, device over temperature, or extended
undervoltage of one of the regulator outputs. All regulator
enables, the ON input, and PWR_ON signals are inhibited
for one second while in the PDN state. After one second
in PDN the pushbutton controller returns to POFF.
PBSTAT Operation
PBSTAT goes LOW 50ms after the initial pushbutton ap-
plication (ON LOW) and will stay LOW for a minimum of
50ms. PBSTAT will go HIGH coincident with ON going HIGH
unless ON goes HIGH before the 50ms minimum on-time.
Power-Up Using the Pushbutton
When in the POFF standby state, the LTC3589 is in com-
plete shutdown except the always active LDO1 and any
regulators enabled with the keep-alive control bits. Pull the
ON pin to ground with a pushbutton for 400ms to begin a
power-up sequence with the WAKE pin tied to an enable
pin. Drive PWR_ON high within five seconds to signal the
LTC3589 to remain in the power-on state.
Power-Down Using the Pushbutton
The pushbutton power-down operation is performed by
the system microprocessor by monitoring the PBSTAT pin.
Once in the PON state, the system controller is responsible
for deciding what action to take with a pushbutton event.
When the ON pin is held LOW for a 50ms debounce period,
the PBSTAT pin is pulled LOW. The system controller should
monitor the PBSTAT pin to determine the pushbutton has
been pushed. If the controller decides that a power-down
is desired, then it should drive the PWR_ON pin LOW.
Power-Up and Down Using PWR_ON Pin
An alternate power-up method is to drive the PWR_ON pin
to a HIGH state. After a delay of 50ms from the PWR_ON
signal, the WAKE pin will pull HIGH to drive regulator en-
able pins. When PWR_ON is HIGH for five seconds, the
sequence controller will enter the PON state. To power
down, drive the PWR_ON pin LOW. 50ms later WAKE will
pull low, all enabled regulators are disabled and the OVEN
command register is reset to 0x00.
Hard Reset Using the Pushbutton
When the ON pin is pulled LOW for five seconds, a hard
reset is initiated. At the end of five seconds, WAKE is
pulled LOW, the I2C command registers are reset to POR
states, enable pin states are ignored, and the one second
power-down timer is started. During the power-down time,
the enables continue to be ignored to allow the regulator
outputs to discharge. The RSTO pin is pulled LOW for
the power-down time to indicate a pushbutton hard reset
occurred. If the PWR_ON pin is LOW at the end of the
one second power-down time, the LTC3589 will remain
in standby mode. If PWR_ON is HIGH at the end of one
second and there are no fault conditions, the LTC3589 will
power-up in the same way shown in Figure 8.
Hard Reset Due to a Fault Condition
A hard reset due to VIN undervoltage, extended undervolt-
age of an output rail, or an overtemperature condition
initiates a hard shutdown of the LTC3589. When the fault
occurs, wake is pulled LOW, the I2C command registers
are reset to POR states, enable pin inputs are ignored,
and the one second power-down timer is started. Dur-
ing the power-down time, the enables continue to be
ignored to allow the regulator outputs to discharge. If the
PWR_ON pin is LOW at the end of the power-down time,
the LTC3589 will remain in standby mode with just the
always-active LDO operating. If PWR_ON is HIGH at the
LTC3589— 1 / LTC3589—2 4—: 50 —aflEC I— 31
LTC3589/LTC3589-1/
LTC3589-2
31
3589fh
For more information www.linear.com/LTC3589
Figure 11. Pin-Strap Start-Up Sequence Application Circuit
ON(PB)
PBSTAT
FAULT
WAKE
PWR_ON
CLIRQ
IRQ
3589 F10
µC/µP CONTROL
<1 SEC
Figure 10. Hard Reset Due to a Fault Condition
operaTion
Figure 6. Power-Up Using the Pushbutton
PBSTAT
WAKE
PWR_ON
3589 F06
ON(PB)
µC/µP CONTROL
400ms
<5 SEC
Figure 9. Hard Reset Using the Pushbutton
PBSTAT
WAKE
PWR_ON
RSTO
3589 F09
ON(PB)
µC/µP CONTROL
50ms
1 SEC
5 SEC
Figure 7. Power Down Using Pushbutton
Figure 8. Power-Up and Down Using PWR_ON Pin
3589 F11
EN1
EN2
EN3
EN4
EN_LDO2
EN_LDO34
ON
PWR_ON
LTC3589
PWR_ON
WAKE
SW1
SW2
SW3
BB_OUT
LDO2
LDO3
LDO4
1V TO 1.2V
VIN
1.8V
0.8V TO 1V
3.3V
1.2V
1.8V
2.8V
end of one second and the fault condition has cleared, the
LTC3589 will power-up in the same way shown in Figure 8.
Neither IRQ nor the status registers are cleared by the
fault induced shutdown.
ENABLE AND POWER-ON SEQUENCING
Enable Input Pin Operation
The regulator enable input pins facilitate pin-strapping an
output rail to the enable pin of the next regulator in the
desired sequence. The regulator enable inputs normally
have a 0.8V (typical) input threshold. If any enable is driven
HIGH, the remaining enable input thresholds switch to a
more accurate 500mV (typical) threshold.
Figure 11 shows an application circuit for a typical pin-
strapped start-up sequence. Holding ON LOW for 400ms
brings up the WAKE pin that is tied to EN1 and EN3 to
enable step-down switching regulators 1 and 3. The output
of regulator 1 is tied to EN2 and EN4 which enable step-
down switching regulator 2 and the buck-boost switching
regulator 4. The output of step-down switching regulator 2
is tied to EN_LDO2 and EN_LDO34 to enable LDO2, LDO3
and LDO4. Within five seconds of WAKE going HIGH, the
microprocessor or microcontroller must drive PWR_ON
HIGH to tell LTC3589 that rails are good and to stay in
the power-on state.
PBSTAT
WAKE
PWR_ON
3589 F08
ON(PB)
µC/µP CONTROL 50ms
5 SEC
50ms - LTC3589
2ms - LTC3589-1/LTC3589-2
PBSTAT
WAKE
3589 F07
ON(PB)
50ms
<5 SEC
PWR_ON µC/µP CONTROL
50ms - LTC3589
2ms - LTC3589-1/
LTC3589-2
LTC3589/ LT LTC3589—2 32 L7ELUEN2
LTC3589/LTC3589-1/
LTC3589-2
32
3589fh
For more information www.linear.com/LTC3589
operaTion
Figure 12 shows the start-up timing for the application
shown in Figure 11. There is a 200µs (typical) delay
between the enable pin and the internal enable signal to
each regulator.
a regulator’s keep-alive bit in its dynamic target voltage
register will keep a regulator alive when the LTC3589 is
in standby (POFF) mode. A regulator with its keep-alive
bit set will stay enabled until the bit is reset writing the bit
LOW, resetting the LTC3589 with a pushbutton hard reset,
or a fault condition (UVLO, PGOOD, timeout or thermal
shutdown) occurs. PGOOD and fault status are reported
in the IRQSTAT and PGSTAT registers and on the IRQ and
PGOOD pins for keep-alive regulators when PWR_ON and
WAKE are LOW.
Software Control Mode
Once a power-up sequence is completed each regulator
may be enabled and disabled individually by the system
as needed for power mode requirements. Setting the out-
put voltage enable command register bit OVEN[7] HIGH
disconnects each regulator from its enable pin so control
is solely through the OVEN command register. To enter
software control mode, set command bit OVEN[7] HIGH
and the desired enable bits in OVEN[6:0] HIGH. Any of the
regulators enabled in OVEN[6:0] will stay on regardless
of the state of their enable pins when OVEN[7] is HIGH.
Setting the regulator enable bits and the software control
bit in OVEN[7] may occur on the same I2C start-stop
sequence. A normal shutdown using PWR_ON resets
all eight bits of the OVEN register to 0x00 to ensure all
regulators are shut off.
FAULT DETECTION, SHUTDOWN, AND REPORTING
The LTC3589 monitors VIN, output rail voltages and internal
die temperature. A warning condition is indicated when
VIN is less than 2.9V and when internal die temperature
approaches the thermal shutdown temperature. A fault
condition occurs when VIN is less than 2.6V, any regulator
output is 8% low for 14ms, or the internal die temperature
is HIGH. Warning and fault states are reported via the IRQ,
PGOOD, and RTSO pins. Specific fault states are read via
the I2C serial port status registers IRQSTAT and PGSTAT.
To help ensure startup sequencing, the LTC3589 is
designed to block the internal enable of a regulator until its
output has discharged to less than 300mV. The I2C system
control register 2 (SCR2) controls whether the LTC3589
waits or enables immediately. The POR default setting for
the LTC3589 and LTC3589-1 is to wait for the output to be
less than 300mV before enabling. The output discharge
resistors on the LTC3589 and LTC3589-1 regulators are
tied to the settings in SCR2.
For use in systems that might back drive the regulator
outputs higher than 300mV, the LTC3589-2 POR default
setting is to always enable regardless of output voltage
and to always engage the discharge resistors whenever
the regulator is not enabled.
Keep-Alive Operation
For systems which require an active supply rail when in
system standby, any of the three LTC3589 step-down
switching regulators or LDO2 may be kept alive regard-
less of the status of PWR_ON and WAKE. Writing a 1 to
V1
V3
V2
V4
LDO2
LDO3
LDO4
3589 F12
WAKE
1.8V
2.8V
1.2V
3.3V
0.5V
0.5V
1.8V
1V
1.2V
200µs
200µs
200µs
Figure 12. Pin-Strap Sequencing Timing
LTC3589— 1 / LTC3589—2 L7HEJWEGR 33
LTC3589/LTC3589-1/
LTC3589-2
33
3589fh
For more information www.linear.com/LTC3589
Figure 14. PGOOD Pin and PGSTAT Status Register Timing
VOUTx
PGOOD
IRQ
3589 F14
ENx
200µs 25µs 25µs
1sec
14ms
250µs
250µs
ENABLE DISABLEUNDERVOLTAGE
DISABLED IF
WAKE LOW
WAKE HIGH AFTER 1sec
IF PWR_ON HIGH
EXTENDED
UNDERVOLTAGE
(FAULT)
WAKE
250µs
Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing
RSTO Pin Function
The RSTO (reset output) pin is an open-drain output for
use as a power-on reset signal. It is pulled LOW at initial
power until LDO1 is within 8% of its target and the initial
one second start-up timer is finished. RSTO remains HIGH
during normal operation and will be pulled low if LDO1
loses regulation for more than 25µs or a pushbutton hard
reset is initiated. RSTO is released high 14ms after LDO1
returns to regulation.
Figure 13 shows a initial power-up for the RSTO pin. If
VIN is not above its undervoltage thresholds at the end
of the 1 second start-up time, the IRQ pin will be pulled
LOW and an undervoltage bit will be set in the IRQSTAT
status register.
voltage for longer than 25µs (typical), the PGOOD pin is
pulled LOW and the appropriate bit in the PGSTAT status
register (Table 15) is set.
Table 15. PGSTAT Read-Only Register Bit Definitions
PGSTAT[BIT] VALUE SETTING
0 0
1
LDO1_STBY Output Low
LDO1_STBY Output Good
1 0
1
Step-Down Switching Regulator 1 Output Low
Step-Down Switching Regulator 1 Output Good
2 0
1
Step-Down Switching Regulator 2 Output Low
Step-Down Switching Regulator 2 Output Good
3 0
1
Step-Down Switching Regulator 3 Output Low
Step-Down Switching Regulator 3 Output Good
4 0
1
Buck-Boost Regulator 4 Output Low
Buck-Boost Regulator 4 Output Good
5 0
1
LDO2 Output Low
LDO2 Output Good
6 0
1
LDO3 Output Low
LDO3 Output Good
7 0
1
LDO4 Output Low
LDO4 Output Good
Figure 14 shows the PGOOD pin and PGSTAT status reg-
ister timing. When no regulator is enabled, the PGOOD
pin is pulled LOW and PGSTAT bits are LOW. PGOOD and
the PGSTAT bits are HIGH 250µs after the last enabled
regulator is within 7% of its target.
PGOOD Pin and PGSTAT Status Register Function
Each LTC3589 regulator has an internal power good out-
put that is active whenever the regulators feedback pin is
closer than 7% (typical) from its input reference voltage.
If any of the internal power good signals indicate a low
operaTion
LDO1
RSTO
VIN 2.7V
–8%
1 SEC
INITIAL POWER-UP
LTC3589
LDO1 UNDERVOLTAGE
25µs
14ms
3589 F13
LDO1
RSTO
VIN
–8%
INITIAL POWER-UP
LTC3589-1/LTC3589-2
LDO1 UNDERVOLTAGE
25µs
14ms
14ms
LTC3589/ LT LTC3589—2 L7LJCUEN2
LTC3589/LTC3589-1/
LTC3589-2
34
3589fh
For more information www.linear.com/LTC3589
operaTion
Figure 16. IRQ and IRQSTAT Status Register Warning Timing
IRQ
IRQSTAT
CLIRQ
3589 F16
TSD OR UV
WARNING
If any enabled regulator output falls more than 7% low
for longer than 25µs PGOOD is pulled LOW and a cor-
responding status bit in the PGSTAT register is set to 0.
The PGOOD pin and PGSTAT status bit remain LOW for
as long as the low voltage condition persists plus 250µs.
An extended low output rail causing the PGOOD pin to
be LOW for longer than 14ms defines a PGOOD timeout
fault condition that triggers a hard reset if not masked in
I2C register bit SCR2[7]. When SCR2[7] is HIGH, PGOOD
remains in normal operation.
During a dynamic voltage slew, PGOOD is pulled LOW
unless bit 5 in the dynamic target voltage register for
each regulator is set HIGH. The status register PGSTAT
is unaffected by a dynamic voltage slew.
Undervoltage Detection
The LTC3589 undervoltage (UV) detection circuit will output
a fault condition, locking out regulator operation, until VIN
reaches 2.7V. Once VIN is above 2.7V the LTC3589 will
operate normally until VIN drops to 2.55V (typical). When
VIN drops below 2.55V, the fault condition initiates a hard
shutdown reset. Figure 15 shows undervoltage warning
and fault detection levels.
Thermal Shutdown Fault and Warning
Similar to the VIN undervoltage detection circuits the over-
temperature detection circuits check for warning and fault
levels. An overtemperature fault will initiate a fault induced
shutdown. An overtemperature warning sets register bit
IRQSTAT[6] and pulls the IRQ pin LOW.
IRQ Pin and IRQSTAT Status Register Function
The IRQ pin and IRQSTAT status register report PGOOD
timeout fault, VIN undervoltage warning and fault, and
high temperature warning and fault. Table 16 shows the
meaning of the IRQSTAT read-only status register bits.
Table 16. IRQSTAT Read-Only Register Bit Definitions
IRQSTAT[BIT] VALUE SETTING
3 1 PGOOD Timeout Fault (PGOOD Low >
14ms)
4 1 VIN Undervoltage Warning (VIN < 2.9V)
5 1 VIN Undervoltage Fault (VIN < 2.6V)
6 1 Thermal Limit Warning (TJ > 130°C)
7 1 Thermal Limit Fault (TJ > 150°C)
Figure 16 shows the timing of the IRQ and IRQSTAT status
register following a warning (VIN <2.9V or high temperature
warning) event. When a warning occurs, IRQ is latched
LOW and bit IRQSTAT[4] or IRQSTAT[5] is set. IRQ remains
low and the IRQSTAT status bits remain active until the
I2C CLIRQ command is given and the warning condition
has passed.
Figure 15. UV Detection Hard Reset and Warning Levels
VIN
UNDERVOLTAGE
VIN
FAULT WARNING
3589 F15
2.55V 2.65V 2.9V 3V
An undervoltage warning sets register bit IRQSTAT[4] and
pulls the IRQ pin LOW.
To minimize standby quiescent current the UVLO and
thermal sensor circuits are disabled when all the regula-
tors are off.
LTC3589— 1 / LTC3589—2 ‘ SEC ‘ SEC ‘ L7HEJWEGR 35
LTC3589/LTC3589-1/
LTC3589-2
35
3589fh
For more information www.linear.com/LTC3589
Figure 17. IRQ and IRQSTAT Status Register Fault Timing
IRQ
IRQSTAT
CLIRQ
3589 F17
TSD, UV,
OR PGOOD FAULT
1 SEC 1 SEC
Figure 19. LTC3589 I2C Serial Port Multiple Write Pattern
1 2 3 4 5 6 7 8 9
0 1 1 0 1 0 0 WR S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
ADDRESS SUB ADDRESS DATA SUB ADDRESS DATA
3589 F19
ACK
ACK ACK ACK ACK
01 1 0 0 0 0
1
START
SDA
STOP
Figure 18. LTC3589 I2C Timing
tSU, DAT
tHD, STA
tHD, DAT
SDA
SCL
tHD, STA
tHD, STA tSU, STO
3589 F18
tBUF
tLOW
tHIGH
START
CONDITION
REPEATED START
CONDITION
STOP START
trtf
tSP
operaTion
Figure 17 shows the timing of the IRQ pin and IRQSTAT
status register following a fault induced hard shutdown
event. When a fault occurs, IRQ is latched LOW and bit
IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ re-
mains LOW until the CLIRQ command is issued. When the
CLIRQ command has been issued, the IRQSTAT status bit
remains set for the one second enable inhibit time or as
long as the fault condition persists, whichever is longer.
Fault Induced Shutdown
Any of the three fault conditions will initiate a hard reset
shutdown triggering the following events: 1) A bit corre-
sponding to the fault is set in status register IRQSTAT, 2)
IRQ and WAKE pins are pulled LOW, 3) enable pin inputs
are ignored and the regulators are disabled, 4) all enable
bits and software control mode bit in the output voltage
enable OVEN command register are cleared, and 5) the
pushbutton controller is sent to the PDN state for one
second and then to POFF. Re-enabling of regulators is
inhibited until both the fault condition and the one second
time out have passed to allow regulator outputs sufficient
time to discharge. When one second timeout and the fault
condition are both passed, if PWR_ON is HIGH, WAKE will
come up and the LTC3589 will respond to any enable pins
that are also HIGH.
LTC3589/ LT LTC3589—2 HHHHHHHHH HHHHHHHHH STAR STOP Ll—Ifl—IOOOOOOOQJMOOOOOOOLHI W 36 L7ELUEN2
LTC3589/LTC3589-1/
LTC3589-2
36
3589fh
For more information www.linear.com/LTC3589
I2C OPERATION
I2C Interface
The LTC3589 communicates with a bus master using the
standard I2C 2-wire interface. The two bus lines, SDA and
SCL, must be HIGH when the bus is not in use. External
pull-up resistors or current sources, such as the LTC1694
SMBus accelerator, are required on these lines. The
LTC3589 is both a slave receiver and slave transmitter. The
I2C control signals, SDA and SCL are scaled internally to
the DVDD supply. DVDD should be connected to the same
power supply as the bus pull-up resistors.
The I2C port has an undervoltage lockout on the DVDD
pin. When DVDD is below approximately 1V, the I2C serial
port is reset to power-on states and registers are set to
default values.
I2C Bus Speed
The I2C port operates at speeds up to 400kHz. It has
built-in timing delays to ensure correct operation when
addressed from an I2C compliant master device. It also
contains input filters designed to suppress glitches should
the bus become corrupted.
I2C START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3589, the master may transmit a STOP condition that
commands the LTC3589 to act upon its new command
set. A STOP condition is sent by the master by transition-
ing SDA from LOW to HIGH while SCL is HIGH. The bus
it then free for communication with another I2C device.
I2C Byte Format
Each byte sent to or received from the LTC3589 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3589
most significant bit (MSB) first.
I2C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3589 is written to,
it acknowledges its write address and subsequent register
address and data bytes. When reading from the LTC3589,
it acknowledges its read address and 8-bit status byte.
An acknowledge pulse (active LOW) generated by the
LTC3589 lets the master know that the latest byte of
information was transferred. The master generates the
clock cycle and releases the SDA line (HIGH) during the
acknowledge clock cycle. The LTC3589 pulls down the SDA
line during the write acknowledge clock pulse so that it is
a stable LOW during the HIGH period of this clock pulse.
I2C Slave Address
The LTC3589 responds to factory programmed read and
write addresses. The write address is 0x68. The read ad-
dress is 0x69. The least significant bit of the address byte,
known as the read/write bit, is 0 when writing data to the
LTC3589 and 1 when reading from it.
operaTion
Figure 20. LTC3589 I2C Serial Port Read Pattern
ACK ACK ACK ACK
START STOP
1
0
2 3
1 1
ADDRESS
4
0
5678
000
9123456789 12345678
01101001
9123456789
1
0 1 101 0 0 WR
START
SDA
SCL
SUB ADDRESS
S7 S6 S3S4S5 S2 S1 S0
ADDRESS
0 1 101 0 0 RD
DATA
R7 R6 R3R4R5 R2 R1 R0
3589 F20
LTC3589— 1 / LTC3589—2 L7HEJWEGR 37
LTC3589/LTC3589-1/
LTC3589-2
37
3589fh
For more information www.linear.com/LTC3589
operaTion
I2C Sub-Addressed Writing
The LTC3589 has 14 writable command registers for
control inputs. They are accessed by the I2C port via a
sub-addressed writing system.
Each write cycle of the LTC3589 consists of a series of
three or more bytes beginning with the LTC3589 write ad-
dress. The second byte is the sub address of the command
register being written to. The sub address is a pointer to the
register where the data in the third byte will be stored. The
third byte is the data to be written to the just-received sub
address. Continue alternating sub address and data bytes
to write multiple registers in a single START sequence.
I2C Bus Write Operation
The master initiates communication with the LTC3589
with a START condition and the LTC3589 write address.
If the address matches that of the LTC3589, the LTC3589
returns an acknowledge pulse. The master should then
deliver the sub address. Again the LTC3589 acknowl-
edges and the cycle is repeated for the data byte. The
data byte is transferred to an internal holding latch
upon the return of its acknowledge by the LTC3589.
Continue writing sub address and data pairs into the
holding latches. Addressing the LTC3589 is not required
for each sub address and data pair. If desired a REPEAT-
START condition may be initiated by the master where
another device on the I2C bus is addressed. The LTC3589
remembers the valid data it has received. Once all the
devices on the I2C have been addressed and sent valid
data and a global STOP has been sent, the LTC3589 will
update its command latches with the data it has received.
I2C Sub-Addressed Reading
The LTC3589 I2C interface supports random address
reading of the I2C command and status registers. Before
reading a register, the registers sub address must be
written. Send a START condition followed by the LTC3589
write address followed by the sub address of the register
to be read. The sub address is now stored as a pointer to
the register. Send a REPEAT-START condition followed
by the LTC3589 read address. Following the acknowledg-
ment of its read address the LTC3589 returns one bit of
information for each of the next 8 clock cycles. A STOP
condition is not required for the read operation. The read
sub address is stored until a new sub address is written.
Verify the data written to the internal data hold latches
prior to committing data to the command registers by
reading back the data before sending a STOP condition.
Continuously poll a register by repeatedly sending a START
condition followed by the LTC3589 read address, and then
clocking the data out after the read address acknowledge.
I2C Command and Status Registers
Table 17 and Table 18 show the LTC3589 I2C command
and status registers. System control register (SCR1) sets
the operating modes of the switching regulators. Each
step-down switching regulator has pulse-skipping, Burst
Mode operation, or forced continuous operation. The
buck-boost switching regulator can be put in continuous
or Burst Mode operation.
The output voltage enable (OVEN) command register
controls the individual enables of each regulator. When
OVEN[7] is set to a logic LOW value, bits OVEN[6-0] are
ORed with their respective enable pins. When OVEN[7]
is HIGH, the input pins EN1, EN2, EN3, EN4, EN_LDO2,
and EN_LDO34, are ignored and the LTC3589 regulators
respond only to the OVEN register. When the regulators
are configured in a hard wired power-up sequence, setting
OVEN[7] allows software control of individual regulators.
When the PWR_ON pin is pulled LOW all bits in the OVEN
register are reset to POR state of 0x00.
System control register 2 (SCR2) controls the operation of
the regulator start-up and regulator power good (PGOOD)
hard shutdown operation. Command register bit SCR2[7]
controls the LTC3589 behavior during an extended PGOOD
fault condition longer than 14ms. Bit SCR2[7] does not
alter PGOOD status reporting by the IRQ pin or IRQSTAT
status register. The bits in SCR2[6-0] control whether a
regulator will wait to turn on when its output is greater
than 300mV. Default POR LOW cause the LTC3589 and
LTC3589-1 regulators to wait for the output to discharge
to less than 300mV. Default POR low of the LTC3589-2
allows the regulators to start at any output voltage.
LTC3589/ LT LTC3589—2
LTC3589/LTC3589-1/
LTC3589-2
38
3589fh
For more information www.linear.com/LTC3589
operaTion
Table 17. LTC3589 Command Register Table
REG NAME B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] DEFAULT
0x07 SCR1Buck-Boost
Mode:
0 = Continuous
1 = Burst Mode
Step-Down Switching
Regulator 3 Mode :
0 0 = Pulse-Skipping
0 1 = Burst
1 0 = Forced Continuous
Step-Down Switching
Regulator 2 Mode :
0 0 = Pulse-Skipping
0 1 = Burst
1 0 = Forced Continuous
Step-Down Switching
Regulator 1 Mode :
0 0 = Pulse-Skipping
0 1 = Burst
1 0 = Forced Continuous
0000 0000
0x10 OVEN Software
Control Mode:
0 = Enable
with Pin or
OVEN Register
1 = Enable/
Disable with
OVEN Register
Only
EN_LDO4EN_LDO3EN_LDO2EN4EN3EN2EN10000 0000
0x12
LTC3589
SCR2 Mask PGOOD
Hard
Shutdown:
0 = Allow
PGOOD
Timeout Hard
Shutdown.
1 = Inhibit
PGOOD Hard
Shutdown.
LDO4
Start-Up:
0 = Wait for
Output < 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
LDO3
Start-Up:
0 = Wait
for Output
< 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
LDO2
Start-Up:
0 = Wait for
Output <
300mV Before
Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Buck-Boost
Start-Up:
0 = Wait
for Output
< 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Step-Down
Switching
Regulator 3
Start-Up:
0 = Wait
for Output
< 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Step-Down
Switching
Regulator 2
Start-Up:
0 = Wait
for Output
< 300mV Before
Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Step-Down
Switching
Regulator 1
Start-Up:
0 = Wait for
Output <
300mV Before
Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
0000 0000
0x12
LTC3589-1
SCR2Mask PGOOD
Hard
Shutdown:
0 = Inhibit
PGOOD
Timeout Hard
Shutdown.
1 = Allow
PGOOD Hard
Shutdown.
LDO4
Start-Up:
0 = Wait for
Output < 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
LDO3
Start-Up:
0 = Wait
for Output
< 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
LDO2
Start-Up:
0 = Wait for
Output <
300mV Before
Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Buck-Boost
Start-Up:
0 = Wait
for Output
< 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Step-Down
Switching
Regulator 3
Start-Up:
0 = Wait
for Output
< 300mV
Before Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Step-Down
Switching
Regulator 2
Start-Up:
0 = Wait
for Output
< 300mV Before
Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
Step-Down
Switching
Regulator 1
Start-Up:
0 = Wait for
Output <
300mV Before
Enable
1 = Dont Wait
and Disable
Discharge
Resistor.
0000 0000
LTC3589— 1 / LTC3589—2 39
LTC3589/LTC3589-1/
LTC3589-2
39
3589fh
For more information www.linear.com/LTC3589
operaTion
Table 17. LTC3589 Command Register Table
REG NAME B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] DEFAULT
0x12
LTC3589-2
SCR2 Mask PGOOD
Hard
Shutdown:
0 = Inhibit
PGOOD
Timeout Hard
Shutdown.
1 = Allow
PGOOD Hard
Shutdown.
LDO4
Start-Up:
0 = Dont Wait
for Output <
300mV Before
Enable
1 = Wait for
Output < 300mV
Before Enable
LDO3
Start-Up:
0 = Dont Wait
for Output <
300mV Before
Enable
1 = Wait for
Output <
300mV Before
Enable
LDO2
Start-Up:
0 = Dont Wait
for Output <
300mV Before
Enable
1 = Wait for
Output <
300mV Before
Enable
Buck-Boost
Start-Up:
0 = Dont Wait
for Output
< 300mV
Before Enable
1 = Wait
for Output
< 300mV
Before Enable
Step-Down
Switching
Regulator 3
Start-Up:
0 = Dont Wait
for Output <
300mV Before
Enable
1 = Wait for
Output <
300mV Before
Enable
Step-Down
Switching
Regulator 2
Start-Up:
0 = Dont Wait
for Output <
300mV Before
Enable
1 = Wait for
Output <
300mV Before
Enable
Step-Down
Switching
Regulator 1
Start-Up:
0 = Dont Wait
for Output <
300mV Before
Enable
1 = Wait for
Output <
300mV Before
Enable
0000 0000
0x20 VCCR LDO2
Reference
Select:
0 =
L2DTV1[4-0]
1 =
L2DTV2[4-0]
Start LDO2
Slew:
0 = Went
1 = GO
Step-Down
Switching
Regulator 3
Reference
Select:
0 =
B3DTV1[4-0]
1 =
B3DTV2[4-0]
Start
Step-Down
Switching
Regulator 3
Slew:
0 = Went
1= GO
Step-Down
Switching
Regulator 2
Reference
Select:
0 =
B2DTV1[4-0]
1 =
B2DTV2[4-0]
Start
Step-Down
Switching
Regulator 2
Slew:
0 = Went
1= GO
Step-Down
Switching
Regulator 1
Reference
Select:
0 =
B1DTV1[4-0]
1 =
B1DTV2[4-0]
Start
Step-Down
Switching
Regulator 1
Slew:
0 = Went
1= GO
0000 0000
0x21 CLIRQ
0x23 B1DTV1 Step-Down Switching
Regulator Switch DV/DT
Control:
00 = 1ns
01 = 2ns
10 = 4ns
11 = 8ns
PGOOD Mask:
0 = PGOOD
Low When
Slewing
1 = PGOOD
Not Forced
Low When
Slewing.
Step-Down Switching Regulator 1 Feedback Reference Input (V1)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
0x24 B1DTV2 Keep-Alive
Mode:
0 = Normal
Shutdown
1 = Keep-Alive
Phase
Select:
0 = Clock
Phase 1
1 = Clock
Phase 2
Step-Down
Switching
Regulator 1
Clock Rate
0 = 2.25MHz
1 = 1.12MHz
Step-Down Switching Regulator 1 Feedback Reference Input (V2)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
0x25 VRRCR LDO2 Dynamic Reference
Slew Rate:
00 = 0.88mV/µs
01 = 1.75mV/µs
10 = 3.5mV/µs
11 = 7mV/µs
Step-Down Switching
Regulator 3 Dynamic
Reference Slew Rate:
00 = 0.88mV/µs
01 = 1.75mV/µs
10 = 3.5mV/µs
11 = 7mV/µs
Step-Down Switching
Regulator 2 Dynamic
Reference Slew Rate:
00 = 0.88mV/µs
01 = 1.75mV/µs
10 = 3.5mV/µs
11 = 7mV/µs
Step-Down Switching
Regulator 1 Dynamic
Reference Slew Rate:
00 = 0.88mV/µs
01 = 1.75mV/µs
10 = 3.5mV/µs
11 = 7mV/µs
1111 1111
LTC3589/LT |_TC3589-2
LTC3589/LTC3589-1/
LTC3589-2
40
3589fh
For more information www.linear.com/LTC3589
operaTion
Table 17. LTC3589 Command Register Table
REG NAME B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] DEFAULT
0x26 B2DTV1 Unused PGOOD Mask:
0 = PGOOD
Low When
Slewing
1 = PGOOD
Not Forced
Low When
Slewing.
Step-Down Switching Regulator 2 Feedback Reference Input (V1)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
0x27 B2DTV2 Keep-Alive
Mode:
0 = Normal
Shutdown
1 = Keep-Alive
Phase
Select:
0 = Clock
Phase 1
1 = Clock
Phase 2
Step-Down
Switching
Regulator 2
Clock Rate
0 = 2.25MHz
1 = 1.125MHz
Step-Down Switching Regulator 2 Feedback Reference Input (V2)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
0x29 B3DTV1 Unused PGOOD Mask:
0 = PGOOD
Low When
Slewing
1 = PGOOD
Not Forced
Low When
Slewing.
Step-Down Switching Regulator 3 Feedback Reference Input (V1)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
0x2A B3DTV2 Keep-Alive
Mode:
0 = Normal
Shutdown
1 = Keep-Alive
Phase
Select:
0 = Clock
Phase 1
1 = Clock
Phase 2
Step-Down
Switching
Regulator 3
Clock Rate
0 = 2.25MHz
1 = 1.125MHz
Step-Down Switching Regulator 3 Feedback Reference Input (V2)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
0x32 L2DTV1 Keep-Alive
Mode:
0 = Normal
Shutdown
1 = Keep-Alive
Unused PGOOD Mask:
0 = PGOOD
Low When
Slewing
1 = PGOOD
Not Changed
When
Slewing.
LDO 2 Feedback Reference Input (V1)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
LTC3589— 1 / LTC3589—2 L7 LJUW 4 1
LTC3589/LTC3589-1/
LTC3589-2
41
3589fh
For more information www.linear.com/LTC3589
Table 18. LTC3589 Read-Only Status Register Table
REG NAME B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
0x02 IRQSTAT Thermal
Limit Hard
Shutdown
Occurred
Near Thermal
Limit
Undervoltage
Hard Shutdown
Occurred
Near Undervoltage
Limit
PGOOD
Timeout Hard
Shutdown
Occurred
Unused Unused Unused
0x13 PGSTAT LDO4 Status:
0 = VOUT Low
1 = VOUT Good
LDO3 Status:
0 = VOUT Low
1 = VOUT Good
LDO2 Status:
0 = VOUT Low
1 = VOUT Good
Buck_Boost Status:
0 = VOUT Low
1 = VOUT Good
Step-Down
Switching
Regulator 3
Status:
0 = VOUT Low
1 = VOUT Good
Step-Down
Switching
Regulator 2
Status:
0 = VOUT Low
1 = VOUT Good
Step-Down
Switching
Regulator 1
Status:
0 = VOUT Low
1 = VOUT Good
LDO1 Status:
0 = VOUT Low
1 = VOUT Good
Table 17. LTC3589 Command Register Table
REG NAME B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] DEFAULT
0x33
LTC3589
L2DTV2 LDO4 Control
MODE:
0 = LDO4
Enable with
EN_LDO34
1 = LDO4
Enable with
OVEN[6]
LDO4 Output Voltage:
00 = 2.8V
01 = 2.5V
10 = 1.8V
11 = 3.3V
LDO 2 Feedback Reference Input (V2)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
0x33
LTC3589-1
LTC3589-2
L2DTV2Unused LDO4 Output Voltage:
00 = 1.2V
01 = 1.8V
10 = 2.5V
11 = 3.2V
LDO 2 Feedback Reference Input (V2)
00000 = 362.5mV
11001 = 675mV
11111 = 750mV
12.5mV Step Size
0001 1001
operaTion
LTC3589/LT |_TC3589-2 1007Eff 100
LTC3589/LTC3589-1/
LTC3589-2
42
3589fh
For more information www.linear.com/LTC3589
LDO2 and step-down switching regulators 1 to 3 each have
a pair of control bits in the voltage change control register
VCCR. The reference select bit selects which of two 5-bit
words are used as inputs to the regulators feedback refer-
ence DAC inputs. The slew GO bit initiates a DAC slew to
the voltage selected by the reference select bit. When the
slew is complete, the slew GO bits are reset LOW.
Accessing the CLIRQ command register will clear the IRQ
pin and will let the IRQ pin to release HIGH. The pin is
cleared when the LTC3589 acknowledges the sub address.
Data written to the CLIRQ command register is ignored.
There are eight command registers that are used to store
the 5-bit dynamic target voltage input to the feedback
reference slewing DACs – B1DTV1, B1DTV2, B2DTV1,
B2DTV2, B3DTV1, B3DTV2, L2DTV1 and L2DTV2. The
registers ending with V2 use bits 4 through 0 to store
the V2 feedback reference voltage for the regulators. The
regulators input reference voltage is set to V2 by setting
the reference select bits HIGH in VCCR and writing to the
go bits in VCCR. The V2 voltage is also selected whenever
the VSTB pin is driven HIGH. The registers ending with
V1 use bits 4 through 0 to store the V1 feedback voltage
reference for the regulators. The regulators input refer-
ence voltage is set to V1 voltage by setting the reference
select bits LOW in command register VCCR. Whenever
a new dynamic target voltage is set, either by changing
the 5-bit value or by changing the reference select bits in
VCCR, the go bits in VCCR must be written to initiate the
dynamic voltage slew. When bit 5 in B1DTV1, B2DTV1,
B3DTV1, and L2DTV1 is LOW the PGOOD pin pulls LOW
during a dynamic voltage slew. Bits 7 and 6 in B1DTV1
set the switch DV/DT rate for all the step-down switch-
ing regulators. Bit 5 in registers B1DTV2, B2DTV2 and
B3DTV2 selects the switching frequency of step-down
switching regulators 1, 2 and 3. Writing the bit LOW sets
the switching frequency to 2.25MHz. Writing the bit HIGH
sets the switching frequency to 1.125MHz.
The dynamic slew rates of the four feedback reference
DACs are independently set using bits in voltage ramp
rate command register (VRRCR). The rate shown is the
slew of the DAC output as it slews up or down to its target
value. The slew rate of the output voltage is scaled by the
gain of the resistor divider network that sets the regulator
output voltage. For example, a regulator set to an output
voltage of 1.2V when the dynamic target voltage reference
is 0.75V has a gain of 1.6. Slewing the regulator output
from 1.2V to 1V requires slewing the DAC output down
125mV from 750mV to 625mV. With a VRRCR slew rate
setting of 01 the slew time of the regulator output is 71µs.
THERMAL CONSIDERATIONS AND BOARD LAYOUT
Printed Circuit Board Power Dissipation
In order to ensure optimal performance and the ability
to deliver maximum output power to any regulator, it is
critical that the exposed ground pad on the backside of
the LTC3589 package be soldered to a ground plane on
the board. The exposed pad is the only GND connection
for the LTC3589. Correctly soldered to a 2500mm2 ground
plane on a double sided 1oz copper board the LTC3589
has a thermal resistance (θJA) of approximately 34°C/W.
Failure to make good thermal contact between the exposed
pad on the backside of the package and an adequately
sized ground plane will result in thermal resistances far
greater than 34°C/W.
To ensure the junction temperature of the LTC3589 die
does not exceed the maximum rated limit and to prevent
overtemperature faults, the power output of the LTC3589
must be managed by the application. The total power dis-
sipation in the LTC3589 is approximated by summing the
power dissipation in each of the switching regulators and
the LDO regulators.
The power dissipation in a switching regulator is esti-
mated by:
PD(SWX) =(VOUTX IOUTX)
100 Eff
100
(W)
Where VOUTX is the programmed output voltage, IOUTX
is the load current and Eff is the % efficiency that can
be measured or looked up in an efficiency table for the
programmed output voltage.
operaTion
LTC3589— 1 / LTC3589—2 L7HEJWEGR 43
LTC3589/LTC3589-1/
LTC3589-2
43
3589fh
For more information www.linear.com/LTC3589
operaTion
The power dissipated by an LDO regulator is estimated by:
P
D(LDO) =
(V
IN(LDO)
V
LDO
)I
LDO
(W)
Where VLDO is the programmed output voltage, VIN(LDO)
is the LDO supply voltage, and ILDO is the output load
current. If one of the switching regulator outputs is used
as an LDO supply voltage, remember to include the LDO
supply current in the switching regulator load current for
calculating power loss.
An example using the equations above with the parameters
in Table 19 shows an application that is at the maximum
junction temperature of 125°C at an ambient temperature
of 85°C. LDO2, LDO3, and LDO4 are powered by step-
down switching regulator 2 and the buck-boost switching
regulator. The total load on those two switching regula-
tors is the sum of the application load and the LDO load.
This example is with the LDO regulators at one half rated
current and the switching regulators at three quarters
rated current.
Table 19. TJ Calculation Example
OUTPUT VIN VOUT APP LOAD TOTAL
LOAD
EFF POWER
DISS
LDO1_VSTB 3.8V 1.2V 10mA 10mA 30mW
LDO2 1.8V 1.2V 100mA 100mA 60mW
LDO3 3.3V 1.8V 100mA 100mA 150mW
LDO4 3.3V 2.5V 100mA 100mA 80mW
VOUT1 3.8V 1.2V 1.2A 1.2A 80% 290mW
VOUT2 3.8V 1.8V 0.65A 0.75A 90% 140mW
VOUT3 3.8V 1.25V 0.75A 0.75A 85% 140mW
VOUT4 3.8V 3.3V 0.70A 0.90A 90% 300mW
TOTAL POWER 1180mW
INTERNAL JUNCTION TEMPERATURE AT 85°C AMBIENT 125°C
Printed Circuit Board Layout
When laying out the printed circuit board, the following
checklist should be followed to ensure proper operation
of the LTC3589:
1. Connect the exposed pad of the package (Pin 41)
directly to a large ground plane to minimize thermal
and electrical impedance.
2. The switching regulator input supply traces and their
decoupling capacitors should be as short as possible.
Connect the GND side of the capacitors directly to the
ground plane of the board. The decoupling capacitors
provide the AC current to the internal power MOSFETs
and their drivers. It is important to minimize inductance
from the capacitors to the LTC3589 pins.
3. Minimize the switching power traces connecting SW1,
SW2, SW3, and buck-boost switch pins SW4AB and
SW4CD to the inductors to reduce radiated EMI and
parasitic coupling. Keep sensitive nodes such as the
feedback pins away from or shielded from the large
voltage swings on the switching nodes.
4. Minimize the length of the connection between the
step-down switching regulator inductors and the output
capacitors. Connect the GND side of the output capaci-
tors directly to the thermal ground plane of the board.
5. Minimize the length of the connection between the
buck-boost regulator output (BB_OUT) and the output
capacitor. Connect the GND side of the output capacitor
directly to the thermal ground plane of the board.
LTC3589/ LT LTC3589—2 m
LTC3589/LTC3589-1/
LTC3589-2
44
3589fh
For more information www.linear.com/LTC3589
applicaTions inForMaTion
The LTC3589 is optimized to support several families of
advanced portable applications processors including the
Marvell PXA3xx and PXA168 Xscale processors, the Fre-
escale i.MX family including the new i.MX53 and i.MX51,
the TI OMAP processors utilizing their Smart reflex, and
many additional ARM processors.
PXA3XX Monahans Processor Support
The PXA3XX processors are hard-coded to communicate
with a PMIC at specific command register addresses in
order to power up the processor supply rails from the
low power state. The LTC3589 I2C device address and
command register addresses map to PXA3xx command
register sub-address requirements. The LTC3589 write
address is 0x68. The key command register addresses
for PXA3xx support are the Output Voltage Enable (OVEN)
register at address 0x10. VCC_APPS/A_EN is mapped
to OVEN bit 0 (enable step-down switching regulator 1).
VCC_SRAM/S_EN is mapped to OVEN bit 2 (enable step-
down switching regulator 3). The voltage change control
register (VCCR) at command register address 0x20 con-
trols the dynamic voltage select and go bits required to
command a voltage change and slew when coming out of
low voltage standby or sleep modes into run mode. The
dynamic target voltage (xxDTV[1,2]) registers map to the
mandatory command register addresses. The full register
map for the LTC3589 shown in Table 17 and Table 18
supports Monahans, hard-coded I2C commands for start-
of-day operation, voltage-change sequence, supply enable,
and return-to-D0 state sequence.
The LTC3589 does not specifically reference the Mona-
hans SYS_EN and PWR_EN enable pins but supports
these signals with individual enable input pins EN[1-4]
and EN_LDO[2,34] that should be hard-wired to SYS_EN
or PWR_EN as required for proper system-level power
sequencing.
The LTC3589 RSTO signal is used to drive the Monahans
hard reset signal nRESET and is based on the state of
the always-active regulator output LDO1_STBY and by a
pushbutton hard reset request. The release of the RSTO
output is delayed a minimum of 10ms as required or as
long as 1s when the LTC3589 is reset using its pushbut-
ton controller.
PXA16X Armada Processor Support
LTC3589 includes spare register bits that can be accessed
by the processor for setting and recalling hibernate and
resume operation.
The keep-alive function allow a step-down switching
regulator to maintain system memory during a hibernate
shutdown state of the Armada processor.
i.MX53 and i.MX51 Processor Support
The LTC3589 has hardware features specifically designed
for the latest i.MX family of processors from Freescale
Semiconductor. The i.MX53 and i.MX51 control the
VSTB input pin of the LTC3589 to command transitions
between the run mode core voltage and the lower level
standby voltage. The run and standby voltage levels are
initially programmed in I2C command registers xxBTV1
and xxBTV2. When the VSTB pin is asserted high all four
dynamically controlled output supply rails will slew to the
xxBTV2 set point. When xxBTV1 and xxBTV2 are set at
the same value, as they are by default, then no slewing
occurs. This allows the single VSTB pin to control any
combination of the four DAC controlled regulators to slew
between two programmed output voltages. When VSTB is
de-asserted back to a zero value the regulators slew back
up to the xxBTV1 set point.
LTC3589— 1 / LTC3589—2 L7HEJWEGR 45
LTC3589/LTC3589-1/
LTC3589-2
45
3589fh
For more information www.linear.com/LTC3589
applicaTions inForMaTion
Earlier i.MX family processors such as the i.MX31 included
two VSTB pins used for controlling the regulator outputs
for a low voltage standby mode, nominal voltage run mode,
and a higher voltage overdrive mode. The LTC3589 can
be used with these processors using the VSTB input pin
to select between run and standby voltages and using
minimal software overhead to set the overdrive voltage
in I2C command registers.
The default DAC reference value in all xxBTVx registers
is 0x19. This accommodates i.MX processors and others
requiring an overdrive voltage. The value can be increased
up to 0x1F for overdrive or supply margining above the
nominal run voltage. Once programmed into the I2C com-
mand registers xxBTVx two voltage outputs are selected
by the VSTB pin. All voltage levels and changes are fully
controllable using the I2C serial port.
Reference Designs and Drivers
Reference designs, schematics, and software drivers are
available to assist the development of Freescale i.MX53
systems that use the LTC3589. Please contact your local
Linear Technology sales representative for details.
OMAP3 and DaVinci Processor Support
The OMAP3 family of ARM processors has similar require-
ments to the processors described above. The LTC3589 I2C
control can fully accommodate the smart reflex dynamic
voltage control with proper embedded software drivers
tailored to the LTC3589 register mapping. The LTC3589
demo board demonstrates configuring and dynamically
slewing and sequencing the outputs using I2C control. The
same provisions can be incorporated into embedded soft-
ware drivers for the OMAP3 or any other target processor.
Back-Driving LTC3589 Outputs
Multirail processors or board level designs may have
surprise leakage paths between power rails. During a
start-up sequence an LTC3589 regulator output may be
pulled higher than 300mV. This violates the default set-
tings for a LTC3589 and LTC3589-1 start-up sequence.
The LTC3589-2 power up default is to allow its regulators
to enable at any output voltage and is recommended for
designs with rail back-drive conditions.
LTC3589/ LT LTC3589—2
LTC3589/LTC3589-1/
LTC3589-2
46
3589fh
For more information www.linear.com/LTC3589
Typical applicaTion
VIN
VIN
PVIN1
37
6
7
39
24
25
33
27
26
34
15
16
40
12
19
1
2
38
5
3
4
32
31
30
28
8
29
17
22
23
SW1
158k
10pF 47µF
100k
LDO1_STDBY
LDO1_FB
EN1
EN2
EN3
EN4
EN_LDO2
EN_LDO3
ON
LTC3589-2
GND
BUCK1_FB
PVIN2
SW2
PVIN3
PVIN4
BUCK2_FB
36
VRTC
1.3V
25mA
35
11
10IMX_LDO_1V8
WAKE
SW2_VCC
DDR_1V5
ENABLE_DDR_1V5
13
14
9
18
20
21
100k
158k
SW3
SW4AB
SW4CD
VIN_LDO2
LDO2_FB
VIN_LDO34
LDO2
LDO3
LDO4
F
BUCK3_FB
BB_OUT
BB_FB
41 GND 1-95
PWR_ONPWR_ON
DVDD
SDA
SCL
VSTB
RST0
PGOOD
PBSTAT
WAKE
IRQ
3589 TA02
VDDA_1-4
VDDAL1
VP1-2
NVCC_EMI_DRAM_1-5
DDR_REF
FASTR_ANA
FASTR_DIG
VDD_FUSE
I2C2_SDA (KEY_ROW3)
I2C2_SCL (EMI_EB2)
PMIC_STBY_REQ
PMIC_ON_REQ
GPIO/PMIC_RDY
GPIO/IRQ
GPIO
DDR_1V5
DDR_REF
NVCC_LCD_1-2
NVCC_JTAG
TVDAC_AHVDDRGB_1-2
TVDAC_DHVDD
VDD_REG(IMX_LDO_1V8_IN)
NVCC_XTAL
NVCC_LVDS
NVCC_LVDS_BG
USB_OTG_VDDA25
USB_H1_VDDA25
VPH1
VHP2
NVCC_NANDF
NVCC_EIM_MAIN_1
NVCC_EIM_MAIN_2
NVCC_EIM_SEC
NVCC_SD1
NVCC_SD2
NVCC_PATA
NVCC_FEC
NVCC_GPIO
NVCC_CSI
NVCC_KEYPAD
USB_H1_VDDA33
USB_OTG_VDDA33
VDD_DIG_PLL(LDO_OUT)
VDDGP_1-15
VCC_1-33
VDD_ANA_PLL(LDO_OUT)
NVCC_CKIH
NVCC_RESET
NVCC_SRTC_PDW
PWR_ON
10µF
H
1.5µH
2.2µH
10µF
10µF
10µF
10µF
191k
10pF 22µF IMX_LDO_1V8
SW2_VCC
PERIPHERAL CORE
1.31V RUN
0.95V STBY
1.2A
2.5V 1.2A
1.3V
VI-O
3.35V
1.2A
ANALOG
2.8V
250mA
3.2V 250mA
ANALOG
1.3V
250mA
ARM CORE
1.10V RUN
0.85V STBY
1.6A
180k
22µF
22µF
100k
10pF 22µF
270k
158k
22µF
F
2.5µH
511k 10pF
191k
180k
4.7k4.7k
47k 47k 47k
2.2µF
10µF
2.2µF
2.2µF
FREESCALE
i.MX536
47k
VIN
LTC3589— 1 / LTC3589—2 L7Hfl§0g 47
LTC3589/LTC3589-1/
LTC3589-2
47
3589fh
For more information www.linear.com/LTC3589
Typical applicaTion
VIN
VIN
PVIN1
37
6
7
39
24
25
33
27
26
34
15
16
40
12
19
1
2
38
5
3
4
32
31
30
28
23
22
29
17
8
SW1
768k
10pF 47µF
604k
LDO1_STDBY
LDO1_FB
EN1
EN2
EN3
EN4
EN_LDO2
EN_LDO34
ON
LTC3589
GND
BUCK1_FB
PVIN2
SW2
PVIN3
PVIN4
BUCK2_FB
36
VRTC
1.2V
25mA
35
11
10
13
14
9
18
20
21
511k
1.02M
SW3
SW4AB
SW4CD
VIN_LDO2
LDO2_FB
VIN_LDO34
LDO2
LDO3
LDO4
1µF
BUCK3_FB
BB_OUT
BB_FB
41
GND
PWR_ON
WAKE
VSRAM
VCORE
10k
9.09k
9.09k
18.2k
PWR_ON
DVDD
SDA
SCL
VSTB
WAKE
PBSTAT
PGOOD
IRQ
RST0
I2C2_SDA
I2C2_SCL
PMIC_VSTBY_REQ
GPIO
GPIO
PMIC_RDY
GPIO1/IRQ
POR_B
3589 TA03
NVCC_IPU
VDD_TVSUPPLY
AHVDDRGB
NVCC_DAC
VDDA
VDD_DIG_PLL_A&B
VDD_TVDIG
VDD_AVA_PLL_A&B
VDDA33
VDDGP
VDD_FUSE
NVCC__EMI
NVCC_PER13,14
VCC(CORE)
NVCC_SRTC_POW
FASTR_ANA
FASTR_DIG
NVCC_EMI_DRAM
NVCC_CNTL_EMI
NVCC_PER2,3,4,5,6,8,9
NVCC_EMI(NAND+EMI)
NVCC_TV_BACK
NVCC_USBPHY
NVCC_OSC
GPIOPWR_ON
10µF
1µH
1.5µH
1.5µH
10µF
10µF
10µF
10µF
422k
10pF 22µF
VSRAM/DDR
1.8V
1A
VSOC
0.676V to 1.4V
1A
VIO
3.3V
1.2A
VANALOG
1.8V
250mA
VAUX
2.8V
250mA
VMEMORY
0.647V TO 1.34V
250mA
VCORE
0.647V TO 1.34V
1.6A
715k
787k
10pF 22µF
681k
316k
22µF
1µF
2.7µH
1M 4.7pF
768k
604k
1µF
1µF
1µF
4.7k 4.7k 47k
1µF
FREESCALE
i.MX51
10k
10k
VSOC
47k47k47k47k
LTC3589/LT |_TC3589-2 1”"flfifififiifififififij—i 1‘ UUUWUUUUU ‘UUUUM WW WUUUU flflflflfl Wmmmm
LTC3589/LTC3589-1/
LTC3589-2
48
3589fh
For more information www.linear.com/LTC3589
6.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
0.40 ± 0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 ±0.10
4.42 ±0.10
4.42 ±0.05
4.42 ±0.05
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
4.50 ±0.05
(4 SIDES)
5.10 ±0.05
6.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
package DescripTion
Please refer to http://www.linear.com/product/LTC3589#packaging for the most recent package drawings.
LTC3589— 1 / LTC3589—2 L7HEJWEGR 49
LTC3589/LTC3589-1/
LTC3589-2
49
3589fh
For more information www.linear.com/LTC3589
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 9/10 Removed 0V from LDO4 on Block Diagram 15
B 12/10 Updated Part Marking in Order Information section 3
C 02/11 LTC3589-1 part added. Changes reflected throughout the data sheet 1-46
D 01/12 Updated part numbers on iMx application processors
Updated Absolute Maximum Ratings and Pin Configuration sections
Added Reference Designs and Drivers section
Added Typical Application
Updated Typical Application
1, 42
3
43
44
45
E 03/12 Added LTC3589-2 throughout
Updated Table 1: LTC3589/-1/-2 Functional Differences
Clarified Enable and Power-On Sequencing section
Clarified I2C Command and Status Register sections
Enhanced Command Register Table
Added section on Back-Driving Outputs
1-50
17
31-32
37
38-39
45
F 02/13 Clarified Absolute Maximum Ratings
Clarified WAKE pin function operation
Clarified buck-boost inductor part numbers
Clarified EN pin operation
Clarified I2C timing diagram
Clarified Command Register Table
3
14
27
31
36
39, 41
G 07/15 Changed pin name on Typical Application
Changed pin names on Pin Configuration
Modified conditions and symbols
Changed pin name in the LDO Regulator 2 section
Changed Command Register [Bit] name in Table 2
Modified equation in the Operating Modes section
Modified equation variables
Updated Table number references
Modified Typical Application circuits
1
3
4-7
18
19
26
43
44
46, 47, 50
H 09/16 Corrected TJMAX from +125°C to +150°C 3
LTC3589/ LT LTC3589—2 50 L7 LJUW
LTC3589/LTC3589-1/
LTC3589-2
50
3589fh
For more information www.linear.com/LTC3589
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 2010
LT 0916 REV H • PRINTED IN USA
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC3589
relaTeD parTs
PART NUMBER DESCRIPTION COMMENTS
LTC3101 1.8V to USB, Multioutput DC/DC
Converter with Low Loss USB Power
Controller
Seamless Transition Between Multiple Input Power Sources, VIN Range: 1.8V to 5.5V,
Buck-Boost Converter VOUT Range: 1.5V to 5.25V, 3.3VOUT at 800mA for VIN ≥ 3V, Dual
350mA Buck Regulators, VOUT: 0.6V to VIN, 38μA Quiescent Current in Burst Mode
Operation, 24-Lead 4mm × 4mm × 0.75mm QFN Package
LTC3556 Switching USB Power Manager PMIC
with Li-Ion/Polymer Charger
Complete Multifunction PMIC: Switching Power Manager, 1A Buck-Boost + 2 Buck
Regulators + LDO, 4mm × 5mm QFN-28 Package
LTC3577/LTC3577-1/
LTC3577-3/LTC3577-4
Highly Integrated Portable/Navigation
PMIC
Complete Multifunction PMIC: Linear Power Manager and Three Buck Regulators,
10-LED Boost Reg, 4mm × 7mm QFN-44 Package, -1 and -4 Versions Have 4.1V
VFLOAT, -3 Version for SiRF Atlas IV Processors
LTC3586/LTC3586-1 Switching USB Power Manager PMIC
with Li-Ion/Polymer Charger
Complete Multifunction PMIC: Switching Power Manager, 1A Buck-Boost + 2 Bucks +
Boost + LDO, 4mm × 6mm QFN-38 Package, -1 Version Has 4.1V VFLOAT.
Typical applicaTion
Integrated Power IC for Mobile µProcessor System with USB/Automotive Battery Charger
10µF 10µF
VIN PVIN1 PVIN2 PVIN3 PVIN4
VBUS VCWALL ACPR
USB
TO µC
TO µC
C2
10µF
0805
C5
10µF
0805
C1
4.7µF
C6
68nF C4
22µF
C3
0.1µF
0603
R7
100k
R11
499k
R2
150k
42
3
7
3 7 9, 21 6
9
20 18 19 14
12
10
11
M5
11 1 6
8
5
10
13
R9
2.94k
R10
1k
M4
L1
3.3µH
L2
10µH
CLPROG PROG
LTC4098
LT3480
GND
SW
BATSENS
OVGATE
OVSENS
D0–D2
CHRG
NTCBIAS
NTC
2
1
15-17
8
4
5
VOUT
IDGATE
BAT
Li-Ion +
R8
100k
T
R6
40.2k
R12
100k
RT
VIN
RUN/SS
PG GNDVCBD SYNC
SW
FB
BOOST
VIN
C7
0.47µF
HVBUCK
OVGATE
RSTO
EN1
EN2
EN3
EN4
EN_LDO2
EN_LDO34
WAKE
PWR_ON
PGOOD
IRQ
LDO1_STDBY
LDO1_FB
1M
3.3V, 25mA
68k
VB1
VL2
VB3
VB2
VBB
68k
68k
316K
DVDD
SDA
SCL
VBB
VSTB
PBSTAT
ON
68k
68k
4.7k
4.7k
TO µP
1µH
10pF
VB1
1.2V
1.6A
VB2
1.8V
1A
VB3
1.2V
1A
VBB
3.3V
1A
VL2
1.2V
250mA
LTC3589
VL3
1.8V
250mA
VL4
2.8V
250mA
3589 TA04
604k
768k
47µF
1.5µH
10pF 715k
422k
22µF
1.5µH
10pF 681k
787k
22µF
4.7pF 1M
316k
22µF
604k
768k
1µF
1µF
1µF
1µF
10µF 10µF 10µF
25
7
37
36
35
8
10
11
13
14
9
18
23
20
29
17
31
30
28
22
21
32
6 24 27 15
39
33
26
34
16
40
12
19
1
2
38
5
3
4
41
2.7µH
SW1
SW2
BUCK1_FB
BUCK2_FB
BUCK3_FB
BB_OUT
SW3
BB_FB
SW4AB
SW4CD
VIN_LDO2
LDO2
LDO2_FB
LDO3
LDO4
GND
VBB
VB2
VIN_LDO34
AUTOMOTIVE,
FIREWIRE,
ETC. R5
10k
R1
1k
R3
33k
R4
10k
D1
MMBZ524-
0BLT1G
10V
M3
ZXMN10A08E6
M1
ZXMP10A18G
M2
ZXMP10A18G
HVIN

Products related to this Datasheet

IC DC/DC CONV 8-OUTPUT 40QFN
IC POWER MANAGEMENT
IC DC/DC CONV 8-OUTPUT 40QFN
IC POWER MANAGEMENT
IC DC/DC CONV 8-OUTPUT 40QFN
IC DC/DC CONV 8-OUTPUT 40QFN
IC POWER MANAGEMENT
IC POWER MANAGEMENT
IC CONV DC/DC 8-OUTPUT 40QFN
IC CONV DC/DC 8-OUTPUT 40QFN
BOARD DEMO FOR LTC3589EUJ
BOARD EVAL FOR LTC3589EUJ
IC DC/DC CONV 8-OUTPUT 40QFN
IC DC/DC CONV 8-OUTPUT 40QFN
IC DC/DC CONV 8-OUTPUT 40QFN
IC DC/DC CONV 8-OUTPUT 40QFN
IC CONV DC/DC 8-OUTPUT 40QFN
IC CONV DC/DC 8-OUTPUT 40QFN
IC CONV DC/DC 8-OUTPUT 40QFN
IC CONV DC/DC 8-OUTPUT 40QFN
IC POWER MANAGEMENT
IC POWER MANAGEMENT
IC POWER MANAGEMENT