Preliminary Specification, V 1.1, October 2004
TDA 5220
ASK/FSK Single Conversion Receiver
Version 1.1
Wireless Control
Components
Never stop thinking.
Edition 2004-10-20
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
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Preliminary Specification, V 1.1, October 2004
TDA 5220
ASK/FSK Single Conversion Receiver
Version 1.1
Wireless Control
Components
Never stop thinking.
TDA 5220
Revision History: 2004-10-20 V 1.1
Previous Version: none
Page Subjects (major changes since last revision)
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TDA 5220
Table of Contents Page
Preliminary Specification 5 V 1.1, 2004-10-20
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.2 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.5 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.9 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 ASK/FSK-Data Path Functional Description . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.3 AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.4 AC/DC Characteristics at TAMB= -40 to 105°C . . . . . . . . . . . . . . . . . . . . 40
4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TDA 5220
Product Description
Preliminary Specification 6 V 1.1, 2004-10-20
1 Product Description
1.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiver (SHR) for the frequency bands 810 to 870 MHz and 400 to 440 MHz. The IC
offers a high level of integration and needs only a few external components. The device
contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a
PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK
demodulator, a data filter, an advanced data comparator (slicer) with selection between
two threshold modes and a peak detector. Additionally there is a power down feature to
save current and extend battery life, and two selectable alternatives of generating the
data slicer threshold.
1.2 Features
Low supply current (Is = 5.7/5.9 mA typ. in FSK mode, Is = 5.0/5.2 mA typ. in ASK
mode for 434/868 MHz)
Supply voltage range 5V ±10%
Power down mode with very low supply current (50nA typ.)
FSK and ASK demodulation capability
Fully integrated VCO and PLL Synthesiser
ASK sensitivity better than -106 dBm over specified temperature range (- 40 to
+105°C)
FSK sensitivity better than -100 dBm over specified temperature range (- 40 to
+105°C)
Selectable frequency ranges 810-870 MHz and 400-440 MHz
Limiter with RSSI generation, operating at 10.7MHz
2nd order low pass data filter with external capacitors
Data slicer with selection between two threshold modes (see Section 2.4.8)
1.3 Application
Keyless Entry Systems
Remote Control Systems
Alarm Systems
Low Bitrate Communication Systems
_J_|__J_J_J_|__|__J_J_|__|__J_J_I_ [[[[.L[[[.L[[[[[
Preliminary Specification 7 V 1.1, 2004-10-20
TDA 5220
Functional Description
2 Functional Description
2.1 Pin Configuration
Figure 1 Pin Configuration
CRST2
PDWN
PDO
DATA
3VOUT
THRES
FFB
OPP
SLN
SLP
LIMX
LIM
SSEL
MSEL
CRST1
VCC
LNI
TAGC
AGND
LNO
VCC
MI
MIX
AGND
FSEL
IFO
DGND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TDA 5220
TDA 5220
Functional Description
Preliminary Specification 8 V 1.1, 2004-10-20
2.2 Pin Definition and Functions
Table 1 Pin Defintion and Function
Pin
No. Symbol Equivalent I/O Schematic Function
1 CRST1 External Crystal
Connector 1
2 VCC 5V Supply
3 LNI LNA Input
4.15V
50uA
1
57uA
4k
1k
3
500uA
Preliminary Specification 9 V 1.1, 2004-10-20
TDA 5220
Functional Description
4 TAGC AGC Time Constant
Control
5 AGND Analogue Ground
Return
6 LNO LNA Output
7 VCC 5V Supply
Pin
No. Symbol Equivalent I/O Schematic Function
1k
3uA
1.4uA
1.7V
4.3V
4
6
1k
5V
TDA 5220
Functional Description
Preliminary Specification 10 V 1.1, 2004-10-20
8
9
MI
MIX
Mixer Input
Complementary
Mixer Input
10 AGND Analogue Ground
Return
11 FSEL 868/434 MHz
Operating
Frequency Selector
12 IFO 10.7 MHz IF Mixer
Output
13 DGND Digital Ground
Return
Pin
No. Symbol Equivalent I/O Schematic Function
8
1.7V
9
400uA
2k 2k
750
2k
11
1.2V
2.2V
4.5k
60
12
300uA
Preliminary Specification 11 V 1.1, 2004-10-20
TDA 5220
Functional Description
14 VDD 5V Supply (PLL
Counter Circuity)
15 MSEL ASK/FSK
Modulation Format
Sector
16 SSEL Data Slicer
Reference Level
Sector
17
18
LIM
LIMX
Limiter Input
Complementary
Limiter Input
Pin
No. Symbol Equivalent I/O Schematic Function
1.2V
40k
15
1.2V
40k
16
330
15k
15k
18
17
2.4V
75uA
TDA 5220
Functional Description
Preliminary Specification 12 V 1.1, 2004-10-20
19 SLP Data Slicer Positive
Input
20 SLN Data Slicer
Negative Input
21 OPP OpAmp
Noninverting Input
22 FFB Data Filter
Feedback Pin
Pin
No. Symbol Equivalent I/O Schematic Function
19
80µA
15uA
3k
100
5uA
20
10k
21
200
5uA
100k
5uA
22
Preliminary Specification 13 V 1.1, 2004-10-20
TDA 5220
Functional Description
23 THRES AGC Threshold
Input
24 3VOUT 3V Reference
Output
25 DATA Data Output
26 PDO Peak Detector
Output
Pin
No. Symbol Equivalent I/O Schematic Function
10k
5uA
23
3.1V
24 20k
25
500
40k
26
446k
4T5
TDA 5220
Functional Description
Preliminary Specification 14 V 1.1, 2004-10-20
27 PDWN Power Down Input
28 CRST2 External Crystal
Connector 2
Pin
No. Symbol Equivalent I/O Schematic Function
27
220k
220k
4.15V
50uA
28
. . Inflqeon ma v—FH n—ui
Preliminary Specification 15 V 1.1, 2004-10-20
TDA 5220
Functional Description
2.3 Functional Block Diagram
Figure 2 Block Diagram
2.4 Functional Block Description
2.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain
figure is determined by the external matching networks situated ahead of LNA and
between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9).
The noise figure of the LNA is approximately 3dB, the current consumption is 500µA.
The gain can be reduced by approximately 18dB. The switching point of this AGC action
can be determined externally by applying a threshold voltage at the THRES pin (Pin 23).
This voltage is compared internally with the received signal (RSSI) level generated by
the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the
LNA gain is reduced and vice versa. The threshold voltage can be generated by
attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a
temperature stable 3V output generated from the internal bandgap voltage and the
THRES pin as described in Section 3.1. The time constant of the AGC action can be
determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operating case
and interference scenario to be expected during operation. The optimum choice of AGC
time constant and the threshold voltage is described in Section 3.1.
PDO
: 1
: 2 VCO : 64
Φ
DET CRYSTAL
OSC
DATA
Crystal
PDWN
FSEL
Loop
Filter
Bandgap
Reference
LNA
RF
TAGC
VCC
VCC AGND
AGC
Reference
THRES
3VOUT
FSK
PLL Demod
OTA
LNI
DGND
-
+
MIXLNO MI OPP
FFB SLP
VCC
LIM LIMX
IF
Filter
IFO SLN
MSEL
LIMITER
68912 1718 22 21 19 20
25
26
23
24
3
4
14
13
2,7 5,10
15
11 128 27
-
+
ASK
FSK
OP
+
-
SSEL
16
DATA-
SLICER
-
U
REF
-
+
+CM
CP
Logic
H=ASK
L=FSK
DETECTOR
PEAK
TDA 5220
eon
TDA 5220
Functional Description
Preliminary Specification 16 V 1.1, 2004-10-20
2.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 400-
440MHz/810-870MHz to the intermediate frequency (IF) at 10.7MHz with a vol-tage gain
of approximately 21dB by utilising either high- or low-side injection of the local oscillator
signal. In case the mixer is interfaced only single-ended, the unused mixer input has to
be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner
frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin).
The IF output is internally consisting of an emitter follower that has a source impedance
of approximately 330to facilitate interfacing the pin directly to a standard 10.7MHz
ceramic filter without additional matching circuitry.
2.4.3 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain,
a phase detector with charge pump and a loop filter and is fully implemented on-chip.
The VCO is including spiral inductors and varactor diodes. The tuning range of the VCO
guarantee over production spread and the specified temperature range is 820 and
860MHz. The oscillator signal is fed both to the synthesiser divider chain and to the
downconverting mixer. In case of operation in the 400 to 440MHz range the signal is
divided by two before it is fed to the Mixer. Depending on whether high- or low-side
injection of the local oscillator is used, the receiving frequency ranges are 810 to
840MHz and 840 to 870MHz or 400 to 420MHz and 420 to 440MHz - see also Section
3.4. To be able to switch between two different frequency channels a divider ratio of
either 32 or 32.25 can be selected via the FSEL-Pin.
Table 2 FSEL-Pin Operating States
2.4.4 Crystal Oscillator
The calculation of the value of the necessary crystal load capacitance is shown in
Section 3.3, the crystal frequency calculation is explained in Section 3.4.
2.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It
has a typical input impedance of 330 to allow for easy interfacing to a 10.7 MHz
ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator
(RSSI) generator which produces a DC voltage that is directly proportional to the input
FSEL RF
Open 400-440MHz
GND 810-870MHz
Preliminary Specification 17 V 1.1, 2004-10-20
TDA 5220
Functional Description
signal level as can be seen in Figure 4. This signal is used to demodulate ASK-
modulated receive signals in the subsequent baseband circuitry. The RSSI output is
applied to the modulation format switch, to the Peak Detector input and to the AGC
circuitry.
In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state as
described in the next chapter.
2.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear phase
detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain
is typically 200µV/kHz. The passive loop filter output that is comprised fully on chip is fed
to both the VCO and the modulation format switch described in more detail below. This
signal is representing the demodulated signal with low frequencies applied to the
demodulator demodulated to logic zero and high frequencies demodulated to logic ones.
However this is only valid in case the local oscillator is low-side injected to the mixer
which is applicable to receive frequencies above 840 or 420MHz. In case of receive
frequencies below 840 or 420MHz high frequencies are demodulated as logical zeroes
due to a sign inversion in the downconversion mixing process as the L0 is high-side
injected to the mixer. See also Section 3.4.
The modulation format switch is actually a switchable amplifier with an AC gain of 11 that
is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was
chosen to facilitate detection in the subsequent circuits. The DC gain is 1 in order not to
saturate the subsequent Data Filter wih the DC offset produced by the demodulator in
case of large frequency offsets of the IF signal. The resulting frequency characteristic
and details on the principle of operation of the switch are described in Section 3.6.
Table 3 MSEL Pin Operating States
The demodulator circuit is switched off in case of reception of ASK signals.
2.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage
follower and two 100kon-chip resistors. Along with two external capacitors a 2nd order
MSEL Modulation Format
Open ASK
Shorted to ground FSK
TDA 5220
Functional Description
Preliminary Specification 18 V 1.1, 2004-10-20
Sallen-Key low pass filter is formed. The selection of the capacitor values is described
in Section 3.2.
2.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a
maximum receive data rate of up to 100kBaud. The maximum achievable data rate also
depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs
are accessible. The output delivers a digital data signal (CMOS-like levels) for
subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RC-
term. In ASK-mode alternatively a scaled value of the voltage at the PDO-output (approx.
87%) can be used as the slicer-threshold as shown in Table 4. The data slicer threshold
generation alternatives are described in more detail in Section 3.5.
Table 4 SSEL Pin Operating States
2.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the
receive data signal. A capacitor is necessary. The input is connected to the output of the
RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This output
can be used as an indicator for the received signal strength to use in wake-up circuits
and as a reference for the data slicer in ASK mode. Note that the RSSI level is also
output in case of FSK mode.
2.4.10 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the
device. A power down mode is available to switch off all subcircuits which is controlled
by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in
this case is typically 50nA.
Table 5 PDWN Pin Operating States
SSEL MSEL Selected Slicing Level (SL)
X Low external SL on Pin 20 (RC-term, e.g.)
High High external SL on Pin 20 (RC-term, e.g.)
Low High 87% of PDO-output (approx.)
PDWN Operating State
Open or tied to ground Powerdown Mode
Tied to Vs Receiver On
w
Preliminary Specification 19 V 1.1, 2004-10-20
TDA 5220
Applications
3 Applications
3.1 Application Circuit
Figure 3 LNA Automatic Gain Control Circuity
The LNA automatic gain control circuitry consists of an operational transimpedance
amplifier that is used to compare the received signal strength signal (RSSI) generated
by the Limiter with an externally provided threshold voltage Uthres. As shown in the
following figure the threshold voltage can have any value between approximately 0.8 and
2.8V to provide a switching point within the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be
generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the internal
bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher
than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the
TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do
not have the same values in order to achieve a fast-attack and slow-release action of the
4
LNA
R S S I (0.8 - 2.8V )
VCC
Gain control
voltage
OTA
+ 3 .1 V
I
load
RSSI > U
threshold
: I
load
=4.2µA
RSSI < U
threshold
: I
load
= -1.5µA
U
C
C5
U
c
:< 2.6V : Gain high
U
c
:> 2 .6V : G a in low
U
cmax
= V
CC
- 0.7V
U
cmin
= 1.67V
R4 R5
3VOUT
24 23
U
threshold
20k
THRES
TAGC
C18
. . Inflqeon
TDA 5220
Applications
Preliminary Specification 20 V 1.1, 2004-10-20
AGC and are used to charge an external capacitor which finally generates the LNA gain
control voltage.
Figure 4 RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The
determination of the optimum point is described in the accompanying Application Note,
a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the
output of the 3VOUT pin is capable of driving up to 50µA, but that the THRES pin input
current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly
related to the receiver power consumption, the power divider resistors should have high
impedance values. The sum of R1 and R2 has to be 600k in order to yield 3V at the
3VOUT pin. R1 can thus be chosen as 240k, R2 as 360k to yield an overall 3VOUT
output current of 5µA1) and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to be
accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain
mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as
a short to the 3VOLT pin. In order to achieve low gain mode operation THRES has to be
connected to GND.
As stated above the capacitor connected to the TAGC pin is generating the gain control
voltage of the LNA due to the charging and discharging currents of the OTA and thus is
also responsible for the AGC time constant. As the charging and discharging currents
are not equal two different time constants will result. The time constant corresponding to
the charging process of the capacitor shall be chosen according to the data rate.
According to measurements performed at Infineon the capacitor value should be greater
than 47nF.
1) note the 20k resistor in series with the 3.1V internal voltage source
LNA always
in high gain mode
0
0.5
1
1.5
2
2.5
3
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30
Input Level at LNA Input [dBm]
U
THRES
Voltage Range
RSSI Level Range LNA always
in low gain mode
RSSI Level
. . Inflqeon \ S
Preliminary Specification 21 V 1.1, 2004-10-20
TDA 5220
Applications
3.2 Data Filter Design
Utilising the on-board voltage follower and the two 100k on-chip resistors a 2nd order
Sallen-Key low pass data filter can be constructed by adding 2 external capacitors
between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following
figure and described in the following formulas1).
Figure 5 Data Filter Design
with RF1int=RF2int=R
with
Q is the qualify factor of the poles where, in case of a Bessel filter a=1.3617, b=0.618
and thus Q=0.577
and in case of a Butter worth filter a=1.414, b=1
and thus Q=0.71
Example: Butter worth filter with f3dB=5kHz and R=100kΩ:
C14=450pF, C12=225pF
1) taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
22 21 19
R
F1 int
100k 100k
C14 C12
R
F2 int
SLPOPPFFB
dB
fR
bQ
C
3
2
2
14
π
=
dB
fQR
b
C
3
4
12
π
=
a
b
Q=
. . Inflqeon ID!
TDA 5220
Applications
Preliminary Specification 22 V 1.1, 2004-10-20
3.3 Crystal Load Capacitance Calculation
The value of the capacitor necessary to achieve that the crystal oscillator is operating at
the intended frequency is determined by the reactive part of the negative resistance of
the oscillator circuit as shown in Section 4.1.3 and by the crystal specifications given by
the crystal manufacturer.
Figure 6 Determination of Series Capacitance Vale for the Quartz Oscillator
The required series capacitor for a crystal with specified load capacitance CL can be
calculated as
CL is the nominal load capacitance specified by the crystal manufacturer.
Example:
13.4 MHz: CL = 12 pF XL=1010 CS = 5.9 pF
This value may be obtained by putting two capacitors in series to the crystal, such as
22pF and 8.2pF for 13.4MHz.
But please note that the calculated CS-value includes all parasitic.
3.4 Crystal Frequency Calculation
As described in Section 2.4.3 the operating range of the on-chip VCO is wide enough to
guarantee a receive frequency range between 810 and 870MHz or between 400 and
440MHz. The VCO signal is divided by 2 before applied to the mixer in case of operation
at 434MHz. This local oscillator signal can be used to downconvert the RF signals both
CS
Crystal Input
impedance
Z1-28 TDA521X
CRST2
28
CRST1
1
L
L
SXf
C
C
π
2
1
1
+
=
Preliminary Specification 23 V 1.1, 2004-10-20
TDA 5220
Applications
with high- or low-side injection at the mixer. High-side injection of the local oscillator has
to be used for receive frequencies between 810 and 840MHz or beteween 400 and
420MHz. In this case the local oscillator frequency is calculated by adding the IF
frequency (10.7 MHz) to the RF frequency. Thus the higher frequency of a FSK-
modulated signal is demodulated as a logical zero (low).
Low-side injection has to be used for receive frequencies above 840 MHz or above
420 MHz. The local oscillator frequency is calculated by subtracting the IF frequency
(10.7 MHz) from the RF frequency then. In this case no sign-inversion occurs and the
higher frequency of a FSK-modulated signal is demodulated as a logical one (high). The
overall division ratios in the PLL are 32 or 64 depending on whether the FSEL-pin is left
open or tied to ground.
Therefore the crystal frequency may be calculated by using the following formula:
with ƒRF receive frequency
ƒLO local oscillator (PLL) frequencyRF ± 10.7)
ƒQU quartz crystal oscillator frequency
r ratio of local oscillator (PLL) frequency and crystal frequency as
shown in the subsequent table
Table 6 Dependence of PLL Overall Division Ratio on FSEL
This yields the following examples:
FSEL is „Low“:
FSEL is „High“:
FSEL Ratio r=(fLO/fQU)
open 32
GND 64
r
f
fRF
QU 7.10±
=
MHz
MHzMHz
fQU 4015625.13
64
7.104.868 =
=
MHz
MHzMHz
fQU 234375.13
32
7.102.434 =
=
TDA 5220
Applications
Preliminary Specification 24 V 1.1, 2004-10-20
3.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C integrator as
shown in Figure 7.
The time constant TA of this circuit including also the internal resistors RF3int and RF4int
(see Figure 9) has to be significantly larger than the longest period of no signal change
TL within the data sequence.
In order to keep distortion low, the minimum value for R is 20k.
TA has to be calculated as
R1, RF3 int, RF4 int and C13 see also Figure 7 and .Figure 9
Figure 7 Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use the peak
detector in connection with an internal resistive divider and one capacitor as shown in
the following Figure 8. For selecting the peak detector as reference for the slicing level
a logic low as to be applied on the SSEL pin.
In case of MSEL is high (or open), which means that ASK-Mode is selected, a logic low
on the SSEL pin yields a logic high on the AND-output and thus the peak-detector is
selected (see Figure 9).
In case of FSK the MSEL-pin and furthermore the one input of the AND-gate is low, so
the peak detector can not be selected.
The capacitor value is depending on the coding scheme and the protocol used.
FSKforC
v
RRIIR
C
RRR
RR
T
and
ASKforCRRIIRC
RRR
RRR
T
FF
FF
F
A
FF
FF
FF
A
...13
)(1
13
1
1
...13)(113
1
)(1
int4int3
int4int3
int4
int4int3
int4int3
int4int3
+
=
++
=
+=
++
+
=
2019 25
U
threshold
data slicer
data
filter
CM
Preliminary Specification 25 V 1.1, 2004-10-20
TDA 5220
Applications
Figure 8 Data Slicer Threshold Generation Utilising the Peak Detector
3.6 ASK/FSK-Data Path Functional Description
The TDA5220 is containing an ASK/FSK switch which can be controlled via Pin 15
(MSEL). This switch is actually consisting of 2 operational amplifiers that are having a
gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in
order to achieve an appropriate demodulation gain characteristic. In order to
compensate for the DC-offset generated especially in case of the FSK PLL demodulator
there is a feedback connection between the threshold voltage of the bit slicer comparator
(Pin 20) to the negative input of the FSK switch amplifier.
In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87% of the
peak-detector output-voltage at Pin 26 (PDO) can be used as the slicer-reference level.
The slicing reference level is generated by an internal voltage divider (RT1int, RT2int),
which is applied on the peak detector output.
The selection between these modes is controlled by Pin 16 (SSEL), as described in
Section 3.5.
This is shown in the following Figure 9.
Pins: 25
U
threshold
data slicer
26
peak detector
C
56k
CP
390k
Infiqeon If
TDA 5220
Applications
Preliminary Specification 26 V 1.1, 2004-10-20
Figure 9 ASK/FSK mode datapath
3.7 FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown above
(highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by
the external RC-combination. The upper cutoff frequency f3 is determined by the data
filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 200µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic
gain of this circuit is 2.2mV/kHz within the bandpass. The gain for the DC content of FSK
signal remains at 200µV/kHz. The cut-off frequencies of the bandpass have to be chosen
such that the spectrum of the data signal is influenced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the effect of the
drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at
the negative input of the slicer comparator (Pin20) is used. The comparator has no
hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises the
voltage appearing at pin 20 (e.g. 1mV with R = 100k). In order to obtain benefit of this
R
F1 int
R
F2 int
v = 1
192122 20
30k
300k
DATA Out
AC DC
typ. 2 V
1.5 V......2.5 V
0.18 mV/kHz
from RSSI Gen
(ASK signal)
C14
C12
R1
C13
+
-
-
+
ASK
FSK
Comp
25
PDO
26
390k
R
T1 int
16
15
MSEL
+
-
-
+
CP
CM
1
H=ASK
L=FSK
H=CP
L=CM
SSEL
DETECTOR
PEAK
SLPOOPFFB SLN
FSK PLL Demodulator
Data Filter
ASK mode: v=1
FSK mode: v=11
ASK/FSK Switch
100n
F
C15
56k
R
T2
100k 100k
R
F3 int
R
F4 int
Preliminary Specification 27 V 1.1, 2004-10-20
TDA 5220
Applications
asymmetrical offset for the demodulation of long zeros the lower of the two FSK
frequencies should be chosen in the transmitter as the zero-symbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
Figure 10 Frequency characteristic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f3 is the 3dB cutoff frequency of the data filter - see Section 3.2.
Example:
R1 = 100kΩ, C13 = 47nF
This leads tof1 = 44Hz and f2 = 485Hz
v
0dB
3dB
v-3dB
f
20dB/dec -40dB/dec
f1 f2 f3
gain (pin19)
DC
0.18mV/kHz 2mV/kHz
13
3301
3301
2
1
1C
kR
kR
f×
+
×
=
π
112 11 ffvf ×=×=
dB
ff 33 =
“was“ !nfineon
TDA 5220
Applications
Preliminary Specification 28 V 1.1, 2004-10-20
3.8 ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is
dominated by the data filter alone, thus it is lowpass shaped.The cutoff frequency is
determined by the external capacitors C12 and C14 and the internal 100k resistors as
described in Section 3.2
Figure 11 Frequency characteristic in case of ASK mode
3.9 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network as
described in Section 3.5 it is necessary to use large values for the capacitor C attached
to the SLN pin (pin 20) in order to achieve long time constants. This results also from the
fact that the choice of the value for R1 connected between the SLP and SLN pins (pins
19 and 20) is limited by the 330k resistor appearing in parallel to R1 as can be seen in
Figure 9. Apart from this a resistor value of 100k leads to a voltage offset of 1mv at the
comparator input. The resulting startup time constant τ1 can be calculated with:
In case R1 is chosen to be 100k and C13 is chosen as 47nF this leads to
When the device is turned on this time constant dominates the time necessary for the
device to be able to demodulate data properly. In the powerdown mode the capacitor is
only discharged by leakage currents.
0dB
-3dB
f
-40dB/dec
f3dB
()
13330||1
1CkR ×=
τ
()
msnFknFkk 6.3477747330||100
1=×=×=
τ
Preliminary Specification 29 V 1.1, 2004-10-20
TDA 5220
Applications
In order to reduce the turn-on time in the presence of large values of C a precharge
circuit was included in the TDA5220 as shown in the following figure.
Figure 12 Principle of the precharge circuit
This circuit charges the capacitor C13 with an inrush current Iload of typically 220µA for a
duration of T2 until the voltage Uc appearing on the capacitor is equal to the voltage Us
at the input of the data filter. This voltage is limited to 2.5V. As soon as these voltages
are equal or the duration T2 is exceeded the precharge circuit is disabled.
τ2 is the time constant of the charging process of C18 which can be calculated as
as the sum of R4 and R5 is sufficiently large and thus can be neglected. T2 can then be
calculated according to the following formula:
I
load
+3.1V
20k
+
-
OTA
+2.4V
R4 R5
24 23
U
threshold
C13
0 / 240uA +
-
20 19
R1
Data Filter ASK/FSK Switch
C18
U2
Us
Uc
Uc<Us
Uc>Us
U2<2.4V : I=240uA
U2>2.4V : I=0
R4+R5=600k
220
2Ck ×
τ
6.1
3
4.2
1
1
ln 222 ×
=
ττ
V
V
T
TDA 5220
Applications
Preliminary Specification 30 V 1.1, 2004-10-20
The voltage transient during the charging of C2 is shown in the following figure:
Figure 13 Voltage appearing on C18 during precharging process
The voltage appearing on the capacitor C13 connected to pin 20 is shown in the following
figure. It can be seen that due to the fact that it is charged by a constant current source
it exhibits is a linear increase in voltage which is limited to USmax = 2.5V which is also the
approximate operating point of the data filter input. The time constant appearing in this
case can be denoted as T3, which can be calculated with:
U2
2
3V
2.4V
T2
13
220
5.2
220
13
max
3C
A
V
A
CU
TS×=
×
=
µµ
Preliminary Specification 31 V 1.1, 2004-10-20
TDA 5220
Applications
Figure 14 Voltage transient on capacitor C13 attached to pin 20
As an example the choice of C18 = 22nF and C13 = 47nF yields
τ2 = 0.44ms
T2 = 0.71ms
T3 = 0.53ms
This means that in this case the inrush current could flow for a duration of 0.64ms but
stops already after 0.49ms when the USmax limit has been reached. T3 should always be
chosen to be shorter than T2.
It has to be noted finally that during the turn-on duration T2 the overall device power
consumption is increased by the 220µA needed to charge C13.
The precharge circuit may be disabled if C18 is not equipped. This yields a T2 close to
zero. Note that the sum of R4 and R5 has to be 600k in order to produce 3V at the
THRES pin as this voltage is internally used also as the reference for the FSK
demodulator.
Us
T3
Uc
TDA 5220
Reference
Preliminary Specification 32 V 1.1, 2004-10-20
4 Reference
4.1 Electrical Data
4.1.1 Absolute Maximum Ratings
Attention: The maximum ratings may not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
may result. The AC/DC characteristic limits are not guaranteed.
Table 7 Absolute Maximum Ratings, Tamb = -40 °C … +105 °C
4.1.2 Operating Range
Within the operational range the IC operates as explained in the circuit description.
Currents flowing into the device are denoted as positive currents and vice versa. The
device parameters with are not part of the production test, but either verified by design
or measured in the Infineon Evalboard as described in Section 4.2.
Supply voltage: VCC = 4.5V .. 5.5V
#Parameter Symbol Limit Values Unit Remarks
min. max.
1 Supply Voltage Vs-0.3 5.5 V
2 Junction Temperature Tj-40 +125 °C
3 Storage Temperature Ts-40 +150 °C
4 Thermal Resistance RthJA 114 K/W
5 ESD integrity, all pins
excl. Pins 1,3, 6, 28
ESD integrity Pins
1,3,6,28
VESD +2
+1.5
kV
kV
HBM according to
MIL STD 883D,
method 3015.7
Preliminary Specification 33 V 1.1, 2004-10-20
TDA 5220
Reference
Table 8 Operating Range, Tamb = -40 °C … +105 °C
Not part of the production test - either verified by design or measured in the Infineon
Evalboard as described in Section 4.2.
4.1.3 AC/DC Characteristics at TAMB = 25°C
AC/DC characteristics involve the spread of values guaranteed within the specified
voltage and ambient temperature range. Typical characteristics are the median of the
production. Currents flowing into the device are denoted as po-sitive currents and vice
versa. The device performance parameters marked with are not part of the production
test - either verified by design or measured in the Infineon Evalboard as described in
Section 4.2.
#Parameter Symbol Limit Values Unit Test Conditions/
Notes L
min. max.
1 Supply Current ISF868
ISF434
ISA868
ISA434
3.9
3.7
3.2
3.0
7.9
7.7
7.2
7.0
mA
mA
mA
mA
fRF=868MHz, FSK Mode
fRF=434MHz, FSK Mode
fRF=868MHz, ASK Mode
fRF=434MHz, ASK Mode
2 Receiver Input Level
ASK
FSK, frequ. dev. ± 50kHz RFin -106
-100 -13
-13 dBm
dBm
@source impedance
50
BER 2E-3, average
power level, Manchester
encoded datarate 4kBit,
280KHz IF Bandwidth
3 LNI Input Frequency fRF 400/810 440/870 MHz
4 MI/X Input Frequency fMI 400/810 440/870 MHz
5 3dB IF Frequency Range
ASK
FSK fIF -3dB 5
10.4 23
11 MHz
6 Powerdown Mode On PWDNON 2V
SV
7 Powerdown Mode Off PWDNOFF 00.8V
8 Gain Control Voltage,
LNA high gain state VTHRES 2.8 VSV
9 Gain Control Voltage,
LNA low gain state VTHRES 00.7V
Ur} !nf|qeon
TDA 5220
Reference
Preliminary Specification 34 V 1.1, 2004-10-20
Table 9 AC/DC Characteristics with TA 25°C, VVCC=4.5 ... 5.5 V
#Parameter Symbol Limit Values Unit Test Conditions/
Notes L
min. typ. max.
SUPPLY
Supply Current
1 Supply current,
standby mode
IS PDWN 50 100 nA Pin 27 (PDWN)
open or tied to 0 V
2 Supply current, device
operating in 868 MHz
range, FSK mode
ISF 868 5.1 5.9 6.7 mA Pin 11 (FSEL) tied to
GND, Pin 15 (MSEL)
tied to GND
3 Supply current, device
operating in 434 MHz
range, FSK mode
ISA 434 4.9 5.7 6.5 mA Pin 11 (FSEL) open,
Pin 15 (MSEL) tied
to GND
4 Supply current, device
operating in 868 MHz
range, ASK mode
ISA 868 4.4 5.2 6 mA Pin 11 (FSEL) tied to
GND, Pin 15
(MSEL) open
5 Supply current, device
operating in 434 MHz
range, ASK mode
ISA 434 4.2 5. 5.8 mA Pin 11 (FSEL) open,
Pin 15 (MSEL) open
LNA
Signal Input LNI (PIN 3), VTHRES>2.8V, high gain mode
1 Average Power Level
at BER = 2E-3
(Sensitivity)
RFin -110 dBm Manchester
encoded datarate
4kBit, 280kHz IF
Bandwidth
2 Average Power Level
at BER = 2E-3
(Sensitivity) FSK
RFin -103 dBm Manchester enc.
datarate 4kBit,
280kHz IF Bandw., ±
50kHz pk. dev.
3 Input impedance,
fRF = 434 MHz
S11 LNA 0.873 / -34.7 deg
4 Input impedance,
fRF = 869 MHz
S11 LNA 0.738 / -73.5 deg
5 Input level @ 1dB
compression
P1dBLNA -15 dBm
Ur} !nf|qeon
Preliminary Specification 35 V 1.1, 2004-10-20
TDA 5220
Reference
6 Input 3rd order intercept
point fRF = 434 MHz
IIP3LNA -10 dBm matched input
7 Input 3rd order intercept
point fRF = 869 MHz
IIP3LNA -14 dBm matched input
8 LO signal feedthrough
at antenna port
LOLNI -73 dBm
Signal Output LNO (PIN 6), VTHRES>2.8V, high gain mode
1 Gain fRF = 434 MHz S21 LNA 1.509/ 138.2 deg
2 Gain fRF = 869 MHz S21 LNA 1.419/ 101.7 deg
3 Output impedance,
fRF = 434 MHz
S22 LNA 0.886 / -12.9 deg
4 Output impedance,
fRF = 869 MHz
S22 LNA 0.866 / -24.2 deg
5 Voltage Gain Antenna
to MI fRF = 434 MHz
GAntMI 42 dB
6 Voltage Gain Antenna
to MI fRF = 869 MHz
GAntMI 40 dB
Signal Input LNI, VTHRES=GND, lwo gain mode
1 Input impedance,
fRF = 434 MHz
S11 LNA 0.873 / -34.7 deg
2 Input impedance,
fRF = 869 MHz
S11 LNA 0.738 / -73.5 deg
3 Input level @ 1dB C. P.
fRF = 434 MHz
P1dBLNA -18 dBm matched input
4 Input level @ 1dB C. P.
fRF = 869 MHz
P1dBLNA -6 dBm matched input
5 Input 3rd order intercept
point fRF = 434 MHz
IIP3LNA -10 dBm matched input
6 Input 3rd order intercept
point fRF = 869 MHz
IIP3LNA -5 dBm matched input
Signal Output LNO, VTHRES=GND, lwo gain mode
1 Gain fRF = 434 MHz S21 LNA 0.183 / 140.6 deg
2 Gain fRF = 869 MHz S21 LNA 0.179 / 109.1 deg
3 Output impedance,
fRF = 434 MHz
S22 LNA 0.897 / -13.6 deg
#Parameter Symbol Limit Values Unit Test Conditions/
Notes L
min. typ. max.
TDA 5220
Reference
Preliminary Specification 36 V 1.1, 2004-10-20
4 Output impedance,
fRF = 869 MHz
S22 LNA 0.868 / -26.3 deg
5 Voltage Gain Antenna
to MI fRF = 434 MHz
GAntMI 22 dB
6 Voltage Gain Antenna
to MI fRF = 869 MHz
GAntMI 19 dB
Signal 3VOUT (PIN 24)
1 Output voltage V3VOUT 2.9 3.1 3.3 V 3VOUT Pin open
2 Current out I3VOUT -3 -5 -10 µA see Section 4.1
Signal THRES (PIN 23)
1 Input Voltage range VTHRES 0V
S-1 V see Section 4.1
2 LNA low gain mode VTHRES 0V
3 LNA high gain mode VTHRES 3V
S-1 V or shorted to Pin 24
4 Current in ITHRES_in 5nA
Signal TAGC (PIN 4)
1 Current out,
LNA low gain state
ITAGC_out -3.6 -4.2 -5.5 µA RSSI > VTHRES
2 Current in,
LNA high gain state
ITAGC_in 11.62.2µARSSI < V
THRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1 Input impedance,
fRF = 434 MHz
S11 MIX 0.942 / -14.4 deg
2 Input impedance,
fRF = 869 MHz
S11 MIX 0.918 / -28.1 deg
3 Input 3rd order intercept
point fRF = 434 MHz
IIP3MIX -28 dBm
4 Input 3rd order intercept
point fRF = 869 MHz
IIP3MIX -26 dBm
Signal Output IFO (PIN 12)
1 Output impedance ZIFO 330
2 Conversion Voltage
Gain fRF = 434 MHz
GMIX 19 dB
#Parameter Symbol Limit Values Unit Test Conditions/
Notes L
min. typ. max.
Preliminary Specification 37 V 1.1, 2004-10-20
TDA 5220
Reference
3 Conversion Voltage
Gain fRF = 869 MHz
GMIX 18 dB
LIMITER
Signal Input LIM/X (PINS 17/18)
1 Input Impedance ZLIM 264 330 396
2 RSSI dynamic range DRRSSI 70 dB
3 RSSI linearity LINRSSI ±1dB
4 Operating frequency
(3dB points)
fLIM 5 10.7 23 MHz
DATA FILTER
1 Useable bandwidth BWBB
FILT
100 kHz
2 RSSI Level at Data
Filter Output SLP,
RFIN=-103dBm
RSSIlow 1.1 V LNA in high gain
mode at 868 MHz
3 RSSI Level at Data
Filter Output SLP,
RFIN=-30dBm
RSSIhigh 2.65 V LNA in high gain
mode at 868 MHz
SLICER
Signal Output DATA (PIN 25)
1 Maximum Datarate DRmax 100 kBps NRZ, 20pF
capacitive loading
2 LOW output voltage VSLIC_L 00.1V
3 HIGH output voltage VSLIC_H VS-
1.3
VS-1 VS-
0.7
V output
current=200µA
Slicer, Negative Input (PIN 20)
1 Precharge Current Out IPCH_SLN -100 -220 -300 µA see Section 4.2.
#Parameter Symbol Limit Values Unit Test Conditions/
Notes L
min. typ. max.
Ur} !nf|qeon
TDA 5220
Reference
Preliminary Specification 38 V 1.1, 2004-10-20
PEAK DETECTOR
Signal Output PDO (PIN 26)
1 Load current Iload -500 µA static load current
must not exceed
-500µA
2 Internal resistive load R 357 446 535 k
CRYSTAL OSCILLATOR
Signals CRSTL 1, CRSTL 2 (PINS 1/28)
1 Operating frequency fCRSTL 6 14 MHz fundamental mode,
series resonance
2 Input Impedance
@ ~13MHz
Z1-28 -600 +
j 1010
3 Serial Capacity
@ ~13MHz
CS10=C1 5.9 pF
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1 ASK Mode VMSEL 1.4 4 V or open
2 FSK Mode VMSEL 00.2V
3 Input Bias Current
MSEL
IMSEL -11 19 µA MSEL tied to GND
FSK DEMODULATOR
1 Demodulation Gain GFMDEM 200 µV/
kHz
2 Useable IF Bandwidth BWIFPLL 10.2 10.7 11.2 MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1 Powerdown Mode On PWDNON 2.8 VSV
2 Powerdown Mode Off PWDNOff 00.8V
#Parameter Symbol Limit Values Unit Test Conditions/
Notes L
min. typ. max.
Preliminary Specification 39 V 1.1, 2004-10-20
TDA 5220
Reference
Not part of the production test - either verified by design or measured in the Infineon
Evalboard as described in Section 4.2.
3 Input bias current
PDWN
IPDWN 19 µA Power On Mode
4 Start-up Time until
valid IF signal is
detected
TSU <1 ms depends on the
used crystal
VCO MULTIPLEXER
Signal FSEL (PIN 11)
1f
RF range 434 MHz VFSEL 1.4 4 V or open
2f
RF range 869 MHz VFSEL 00.2V
3 Input bias current
FSEL
IFSEL -160 -200 -240 µA FSEL tied to GND
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1 Slicer-Reference is
voltage at Pin 20 (SLN)
VSSEL 1.4 4 V or open
2 Slicer-Reference is
approx. 87% of the
voltage at Pin 26
(PDO)
VSSEL 00.2V
3 Input bias current
SSEL
ISSEL -10 -19 µA SSEL tied to GND
#Parameter Symbol Limit Values Unit Test Conditions/
Notes L
min. typ. max.
Ur} !nf|qeon
TDA 5220
Reference
Preliminary Specification 40 V 1.1, 2004-10-20
4.1.4 AC/DC Characteristics at TAMB= -40 to 105°C
Currents flowing into the device are denoted as positive currents and vice versa.
Table 10 AC/DC Characteristics with TAMB = -40°C ...+105°C, VVCC=4.5 ... 5.5 V
#Parameter Symbol Limit Values Unit Test Conditions/
Notes
min. typ. max.
SUPPLY
Supply Current
1 Supply current,
standby mode
IS PDWN 50 400 nA Pin 27 (PDWN) open
or tied to 0 V
2 Supply current,
device operating in
868 MHz range, FSK
mode
ISF 868 3.9 5.9 7.9 mA Pin 11 (FSEL) tied to
GND, Pin 15 (MSEL)
tied to GND
3 Supply current,
device operating in
434 MHz range, FSK
mode
ISA 434 3.7 5.7 7.7 mA Pin 11 (FSEL) open,
Pin 15 (MSEL) tied
to GND
4 Supply current,
device operating in
868 MHz range, ASK
mode
ISA 868 3.2 5.2 7.2 mA Pin 11 (FSEL) tied to
GND, Pin 15
(MSEL) open
5 Supply current,
device operating in
434 MHz range, ASK
mode
ISA 434 3 5. 7 mA Pin 11 (FSEL) open,
Pin 15 (MSEL) open
Signal Input 3VOUT (PIN 24)
1 Output voltage V3VOUT 2.9 3.1 3.3 V 3VOUT Pin open
2 Current out I3VOUT -3 -5 -10 µA see Section 4.1
Signal THRES (PIN 23)
1 Input Voltage range VTHRES 0V
S-1 V see Section 4.1
2 LNA low gain mode VTHRES 0V
3 LNA high gain mode VTHRES 3V
S-1 V or shorted to Pin 24
4 Current in ITHRES_in 5nA
Signal TAGC (PIN 4)
1 Current out,
LNA low gain state
ITAGC_out -1 -4.2 -8 µA RSSI > VTHRES
Ur} !nf|qeon
Preliminary Specification 41 V 1.1, 2004-10-20
TDA 5220
Reference
2 Current in, LNA high
gain state
VTAGC_in 0.5 1.5 5 µA RSSI < VTHRES
MIXER
1 Conversion Voltage
Gain fRF = 434 MHz
GMIX +19 dB
2 Conversion Voltage
Gain fRF = 868 MHz
GMIX +18 dB
LIMITER
Signal Input LIM/X (PINS 17/18)
1 RSSI dynamic range DRRSSI 70 dB
2 RSSI Level at Data
Filter Output SLP,
RFIN= -103dBm
RSSIlow 1.1 V LNA in high gain
mode at 868 MHz
3 RSSI Level at Data
Filter Output SLP,
RFIN= -30dBm
RSSIhigh 2.65 V LNA in high gain
mode at 868 MHz
DATA FILTER
Slicer, Signal Output DATA (PIN 25)
1 Maximum Datarate DRmax 100 kBps NRZ, 20pF
capacitive loading
2 LOW output voltage VSLIC_L 00.1V
3 HIGH output voltage VSLIC_H VS-
1.5
VS-1 VS-
0.5
V output
current=200µA
Slicer, Negative Input (PIN 20)
1 Precharge Current
Out
IPCH_SLN -100 -220 -300 µA see Section 4.2
#Parameter Symbol Limit Values Unit Test Conditions/
Notes
min. typ. max.
Ur} !nf|qeon
TDA 5220
Reference
Preliminary Specification 42 V 1.1, 2004-10-20
PEAK DETECTOR
Signal Output PDO (PIN 26)
1 Load current Iload -400 µA static load current
must not exceed
-500µA
2 Internal resistive load R 356 446 575 k
CRYSTAL OSCILLATOR
Signals CRSTL 1, CRSTL 2 (PINS 1/28)
1 Operating frequency fCRSTL 6 14 MHz fundamental mode,
series resonance
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1 ASK Mode VMSEL 1.4 4 V or open
2 FSK Mode VMSEL 00.2V
3 Input bias current
MSEL
IMSEL -11 -20 µA MSEL tied to GND
FSK DEMODULATOR
1 Demodulation Gain GFMDEM 200 µV/
kHz
2 Useable IF
Bandwidth
BWIFPLL 10.2 10.7 11.2 MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1 Powerdown Mode On PWDNON 2.8 VSV
2 Powerdown Mode Off PWDNOff 00.8V
#Parameter Symbol Limit Values Unit Test Conditions/
Notes
min. typ. max.
Preliminary Specification 43 V 1.1, 2004-10-20
TDA 5220
Reference
Not part of the production test - either verified by design or measured in the Infineon
Evalboard as described in Section 4.2.
4.2 Test Circuit
The device performance parameters marked with in Section 4.1 were either verified
by design or measured on an Infineon evaluation board. This evaluation board can be
obtained together with evaluation boards of the accompanying transmitter device
TDK5110 in an evaluation kit that may be ordered on the INFINEON Webpage
www.infineon.com/Products. More information on the kit is available on request.
3 Start-up Time until
valid signal is
detected at IF
TSU <1 ms depends on the used
crystal
VCO MULTIPLEXER
Signal FSEL (PIN 11)
1f
RF range 434 MHz VFSEL 1.4 4 V or open
2f
RF range 869 MHz VFSEL 00.2V
3 Input bias current
FSEL
IFSEL -110 -200 -340 µA FSEL tied to GND
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1 Slicer-Reference is
voltage at Pin 20
(SLN)
VSSEL 1.4 4 V or open
2 Slicer-Reference is
approx. 87% of the
voltage at Pin 26
(PDO)
VSSEL 00.2V
3 Input bias current
SSEL
ISSEL -11 -20 µA SSEL tied to GND
#Parameter Symbol Limit Values Unit Test Conditions/
Notes
min. typ. max.
'6 Inflneon ........... Baum-em mm: , Daxanm' \ILJ I
TDA 5220
Reference
Preliminary Specification 44 V 1.1, 2004-10-20
Figure 15 Schematic of the Evaluation Board
4.3 Test Board Layouts
Figure 16 Top Side of the Evaluation Board
Preliminary Specification 45 V 1.1, 2004-10-20
TDA 5220
Reference
Figure 17 Bottom Side of the Evaluation Board
Figure 18 Component Placement on the Evaluation Board
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TDA 5220
Reference
Preliminary Specification 46 V 1.1, 2004-10-20
4.4 Bill of Materials
The following components are necessary for evaluation of the TDA5220.
Table 11 Bill of Materials (cont’d)
Ref. Value 434MHz Value 868MHz Specification
C1 1pF 1pF 0805, COG, +/-0.1pF
C2 4.7pF 3.9pF 0805, COG, +/-0.1pF
C3 6.8pF 5.6pF 0805, COG, +/-0.1pF
C4 100pF 100pF 0805, COG, +/-5%
C5 47nF 47nF 1206, X7R, +/-10%
C6 10nH 3.9pF Toko, PTL2012-F10N0G
C7 100pF 100pF 0805, COG, +/-5%
C8 33pF 22pF 0805, COG, +/-5%
C9 100pF 100pF 0805, COG, +/-5%
C10 10nF 10nF 0805, X7R, +/-10%
C11 10nF 10nF 0805, X7R, +/-10%
C12 220pF 220pF 0805, COG, +/-5%
C13 47nF 47nF 0805, X7R, +/-10%
C14 470pF 470pF 0805, COG, +/-5%
C15 47nF 47nF 0805, COG, +/-5%
C16 8.2pF 8.2pF 0805, COG, +/-0.1pF
C17 18pF 18pF 0805, COG, +/-1%
C18 22nF 22nF 0805, X7R, +/-5%
C21 100nF 100nF 1206, X7R, +/-10%
IC1 TDA5220 TDA5220 Infineon
L1 15nH 3.3nH Toko, PTL2012-F15N0G
L2 8.2pF 3.9pF 0805, COG, +/-0.1pF
Q1 13.234375 MHz 13.4015625 MHz 1053-922
Q2 SFE_10.7MA5-A SFE_10.7MA5-A Murata
R1 100k100k0805, +/-5%
R4 240k240k0805, +/-5%
R5 360k360k0805, +/-5%
Preliminary Specification 47 V 1.1, 2004-10-20
TDA 5220
Reference
Please note that in case of operation at 434MHz a capacitor has to be soldered in place
L2 and an inductor in place C6.
R6 10k10k0805, +/-5%
S1 STL_2POL STL_2POL 2-pole pin connector
S2 SOL_JUMP SOL_JUMP SOL_JUMP
S3 SOL_JUMP SOL_JUMP SOL_JUMP
S6 SOL_JUMP SOL_JUMP SOL_JUMP
X1 STL_2POL STL_2POL 2-pole pin connector
X2 A107-900A (1.6mm
gold plated) A107-900A (1.6mm
gold plated) INPUT OUTPUT
ENTERPRISE CORP
X3 A107-900A (1.6mm
gold plated) A107-900A (1.6mm
gold plated) INPUT OUTPUT
ENTERPRISE CORP
Ref. Value 434MHz Value 868MHz Specification
4.4m “ n32, H—L‘fl 0.222“- °'°“ +6 o.1®@6\2ex zgnnnnnnnnnnnn15-28x unnnuuuuuunnn I 14 9.7m” Index Marking 1) Does nut include plaslic or maul prmmsbn cl 0.15 max. per side 2) Does mt hclude dumber pvolnninn
TDA 5220
Package Outlines
Preliminary Specification 48 V 1.1, 2004-10-20
5 Package Outlines
Figure 19 <Dev_Package1>
Table 12 Order Information
Type Ordering Code Package
TDA 5220 Q67100-H2049 <Dev_Package1>
P_TSSOP_28.eps
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
TDA 5220
List of Tables Page
Preliminary Specification 49 V 1.1, 2004-10-20
Table 1 Pin Defintion and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2 FSEL-Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3 MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4 SSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6 Dependence of PLL Overall Division Ratio on FSEL. . . . . . . . . . . . . . 23
Table 7 Absolute Maximum Ratings, Tamb = -40 °C … +105 °C . . . . . . . . . . . . 32
Table 8 Operating Range, Tamb = -40 °C … +105 °C . . . . . . . . . . . . . . . . . . . . 33
Table 9 AC/DC Characteristics with TA 25°C, VVCC=8.5V /. . . . . . . . . . . . . . . . 34
Table 10 AC/DC Characteristics with TAMB = -40°C ...+105°C, VVCC=5.5V . . . . 40
Table 11 Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12 Order Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TDA 5220
List of Figures Page
Preliminary Specification 50 V 1.1, 2004-10-20
Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3 LNA Automatic Gain Control Circuity. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4 RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . 20
Figure 5 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6 Determination of Series Capacitance Vale for the Quartz Oscillator . . 22
Figure 7 Data Slicer Threshold Generation with External R-C Integrator . . . . . 24
Figure 8 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . 25
Figure 9 ASK/FSK mode datapath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10 Frequency characteristic in case of FSK mode . . . . . . . . . . . . . . . . . . 27
Figure 11 Frequency characteristic in case of ASK mode . . . . . . . . . . . . . . . . . . 28
Figure 12 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13 Voltage appearing on C18 during precharging process. . . . . . . . . . . . 30
Figure 14 Voltage transient on capacitor C13 attached to pin 20 . . . . . . . . . . . . 31
Figure 15 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . 45
Figure 19 P-TSSOP-28-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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