PI3EQX12908A2 Datasheet by Diodes Incorporated

View All Related Products | Download PDF Datasheet
mDES. \(DPER/CDM
1www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Features
High-speed serial link with linear equalizer
Support PCIe Gen 1/2/3 protocol, 10GbE, SATA3, SAS3
Supporting 8 differential channels
Independent channel configuration of receiver equalization,
output swing and flat gain
Per Channel Activity Detector with selectable input
termination between 50Ω to VDD and 200KΩ to VDD
Per Channel Output Termination Detector on power up with
selectable output termination between 50Ω to VDD and High
impedance
Very linear transfer function
Fully compliant to PCISIG Link Training
Single-ended mode receiver detection for PCIe
Input Threshold detection
Pin strap and I2C master/slave selectable device
programming with external EEPROM
4-bit selectable address bit for I2C
Supply Voltage: 3.3V±0.3V
Industrial Temperature Range: -40oC to 85oC
Packaging (Pb-free & Green):
54-contact TQFN (10mm x 5.5mm x 0.5mm pitch) -
flowthrough pinout
Description
The PI3EQX12908A2 is an 8-channel PCIe Gen 2, 10GbE, SATA3,
ReDriver™. The device provides programmable linear equaliza-
tion, output swing and gain, by either pin strapping option or
I2C Control, to optimize performance over a variety of physical
mediums by reducing Inter-symbol interference.
The PI3EQX12908A2 supports eight 100-Ohm Differential CML
data I/Os and extends the signals across other distant data path-
ways on the user’s platform.
The programmable settings can be applied easily via pins, soft-
ware (I2C) or loaded via an external EEPROM. When operating
in the EEPROM mode, the configuration information is auto-
matically loaded on power up, which eliminates the need for an
external microprocessor or software driver.
The PI3EQX12908A2 offers fully Linear Transfer function to ful-
ly comply with all PCIe 3 Link Training signals.
Eye Diagram
8-channel PCI Express Gen 3, 10GbE, SATA3 ReDriver™ with Linear Equalization
A product Line of
Diodes Incorporated
PI3EQX12908A2
Host Channel Loss
Pericom
ReDriver
Device
End Point
Equalizer, De-emphasis,
Swing, and Amplifier Gain
Long input trace,
cable, or connectors
+
-
+
-
+
-
Output trace
+
-
+
-
+
-
+
-
Input trace
+
-
Long output trace,
cable, or connectors
Before Channel Loss Before ReDriver After ReDriver
TX
TX
RX
RX
\ (E PER/00M UUUUULIULHJ cccccccccccccccccc :jjjjjzjjjjjzjjjjj
2
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Block Diagram
Pin Configuration - Top View (54-TQFN)
+
-
+
-
er
Voltage
mode
output
buffer
I+ +
Buff r
Conditional
Output Load:
100-Ohm diff.
or Hi-Z
ut
I+
-
Input Threshold
Detection
Swing
Control
Buffer
Flat gain
control
Flat gain
control (2-bits) Output Swing
control (1-bit)
CML Input
Buffer
V
DD
Linear
Amplifier
Equalizer
Power
Management
PRSNT#
Equalization
Control (4-bit)
Conditional
Input Load:
50-Ohm or
200K-ohm
Rx detect
I+
I-
Repeats for 8 Channel
I+
O+
I+
O-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21 22 23 24 25 26
28
29
30
31
32
33
34
35
39
38
37
36
B0RX-
B1RX+
B1RX-
B2RX+
B3RX+
B3RX-
A1RX+
A1RX-
A3RX+
A3RX-
GND
B0TX-
B0TX+
B2TX-
A0TX+
A0TX-
FGB1/AD0
RXDET
GND
SD_TH0
ENI2C
EQB1/AD2
FGA1/SCL
FGA0/SDA
B0RX+
B2RX-
VDD
A0RX+
A0RX-
VDD
A2RX+
A2RX-
EQA2
EQA1
EQA0
EQB2
SW0/I2C_RESET#
A3TX-
A3TX+
A2TX-
A2TX+
A1TX-
A1TX+
VDD
B3TX-
40
41
42
43
49
45
44
4748
B3TX+
B2TX+
VDD
B1TX-
5051525354
FGB0/AD1
PRSNT#
VDD
27
ALL_DONE
EQB0/AD3
46
B1TX+
GODES WIDE/3100M
3
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Pin Description
(Flow-Thru Pinout)
Pin # (54-TQFN) Pin Name Type Description
Data Signals
10
11
A0R X+
A0RX-
I
I
Differential inputs for Channel A0, with internal 50-Ohm pull-up and >200K-Ohm
otherwise.
35
34
A0TX+,
A0TX-
O
ODifferential outputs for Channel A0
12
13
A1R X+,
A1RX-
I
I
Differential inputs for Channel A1, with internal 50-Ohm pull-up and >200K-Ohm
otherwise.
33
32
A1TX+,
A1TX-
O
ODifferential outputs for Channel A1
15
16
A2RX+,
A2RX-
I
I
Differential inputs for Channel A2, with internal 50-Ohm pull-up and >200K-Ohm
otherwise.
31
30
A2TX+,
A2TX-
O
ODifferential outputs for Channel A2
17
18
A3R X+,
A3RX-
I
I
Differential inputs for Channel A3, with internal 50-Ohm pull-up and >200K-Ohm
otherwise.
29
28
A3TX+,
A3TX-
O
ODifferential outputs for Channel A3
1
2
B0R X+,
B0RX-
I
I
Differential inputs for Channel B0, with internal 50-Ohm pullup and >200KOhm
otherwise.
45
44
B0TX+,
B0TX-
O
ODifferential outputs for Channel B0
3
4
B1R X+,
B1RX-
I
I
Differential inputs for Channel B1, with internal 50-Ohm pullup and >200KOhm
otherwise.
43
42
B1TX+,
B1TX-
O
ODifferential outputs for Channel B1
5
6
B2RX+,
B2RX-
I
I
Differential inputs for Channel B2, with internal 50-Ohm pullup and >200KOhm
otherwise.
40
39
B2TX+,
B2TX-
O
ODifferential outputs for Channel B2
7
8
B3R X+,
B3RX-
I
I
Differential inputs for Channel B3, with internal 50-Ohm pullup and >200KOhm
otherwise.
38
37
B3TX+,
B3TX-
O
ODifferential outputs for Channel B3
GODES WIDE/3100M
4
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Pin # (54-TQFN) Pin Name Type Description
Control Signals
48 ENI2C I
I
2
C Enable Pin. When tied to Low, each channel is programmed by the external
pin voltage (Pin Mode). When tied to High, each channel is programmed by the
data stored in the I2C bus (Slave Mode). When FLOAT, data is accesses from
external EEPROM (Master Mode). ENI2C has pull-up / pull-down 90k-Ohm
resistance (Default = VDD / 2).
When ENI2C = 1 (I
2
C Mode)
50 SCL I/O I
2
C SCL clock input in I
2
C Slave Mode (ENI2C = High). This pin becomes clock
output when loading from EEPROM in I2C Master Mode (ENI2C = FLOAT).
49 SDA I/O I2C SDA data input/output in I2C Master or Slave Mode.
54, 53, 47, 46 AD[0:3] I
I
2
C programmable address bits in I
2
C Master or Slave Mode. AD[0:2] have pull-
up 90k-Ohm resistance. AD[3] have pull-up / pull-down 90k-Ohm resistance.
(Default = VDD/2)
25 I2C_RESET# IReset Pin for I2C. When Low, the registers are reset to default value.
I2C_RESET# has pull-up 90k-Ohm resistance
When ENI2C = 0 (Pin mode)
21, 20, 19 EQA[0:2] I
These pins set the level of Equalizer in Bank A channels when ENI2C is Low.
When ENI2C is High, the I2C registers provide independent control of each
channel. See Table 1: Equalizer Settings. EQA[1] has pull-up 90k-Ohm resistance.
EQA[0] and EQA[2] have pull-up / pull-down 90k-Ohm resistance (Default =
VDD / 2).
46, 47, 23 EQB[0:2] I
These pins set the level of Equalizer in Bank B channels when ENI2C is Low.
When ENI2C is High, the I2C registers provide independent control of each
channel, and the EQB[1:0] pins are converted to I2C AD[2:3] inputs. See Table 1:
Equalizer Settings. EQB[1] has pull-up 90k-Ohm resistance. EQB[0] and EQB[2]
have pull-up / pull-down 90k-Ohm resistance (Default = VDD / 2).
49, 50 FGA[0:1] I
These pins control the level of Flat Gain in Bank A channels when ENI2C is Low.
When ENI2C is High, the I2C registers provide independent control of each
channel, and the FGA[1:0] pins are converted to I2C SCL/SDA. See Table 2: Flat
Gain Settings.
53, 54 FGB[0:1] I
These pins control the level of Flat Gain in Bank B channels when ENI2C is Low.
When ENI2C is High, the I2C registers provide independent control of each
channel, and FGB[1:0] pins are converted to AD[0:1] inputs. See Table 2: Flat Gain
Settings. FGB[0] and FGB[1] have pull-up 90k-Ohm resistance.
25 SW0 I This pins sets the Output Voltage Swing level in all channels when ENI2C is Low.
SW0 has pull-up 90k-Ohm resistance.
26 SD_TH0 I
Internal Signal Detect Threshold. This pin should be tied to VDD for normal
operation. Refer to Table 4 for more options. SD_TH0 has pull-up 90k-Ohm
resistance.
In both I2C and Pin modes
22 RXDET I
Receiver Detection Control Pin. When High, receiver detection is enabled to
support PCIe Mode. When Low, receiver detection is disabled to support 10GbE
and SATA3 Modes and input is 50-Ohm to VDD. RXDET has pull-up 90k-Ohm
resistance.
Pin Description Cont.
GODES WIDE/3100M
5
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Pin # (54-TQFN) Pin Name Type Description
52 PRSNT# I
Cable Present Detect Input. When High, a cable is not present per PCIe Cabling
Specification 1.0, and the device is put in lower power mode. When Low, the
device is enabled and in normal operation. PRSNT# has pull-up 90k-Ohm resis-
tance.
Output
27 ALL_DONE OValid Register Load Status Output. When LOW, the external EEPROM load has
failed. When HIGH, the external EEPROM load is successful.
Power Pins
9, 14, 36, 41, 51 VDD PWR 3.3V ± 10% Supply Voltage
Center Pad, 24 GND PWR Supply GND
Pin Description Cont.
GODES WIDE/3100M
6
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Description of Operation
Output Receiver Detector:
On power up or when PRSNT# becomes low, the output resistance is set to high impedance, and the input resistance is set to 200K
ohms. The device continually looks to detect an external 50 ohm termination resistor on a per channel basis. If no 50 ohms is detected
in the first 40us of time, the channel is continually polled with 40us detection cycle until detection occurs. This operation can only be
reinitiated when PRSNT# or I2C_RESET# are toggled again.
Input Activity Detector:
When the input voltage on individual channel basis falls below Vth-, the output is driven to the common mode voltage so as to eliminate
output chatter. When the input voltage is higher than Vth+, the channel is resumed immediately.
Power Enable function:
One pin control or I2C control, when PRSNT# is set to high, the IC goes into power down mode, both input and output termination set
to 200K and high impedance respectively. Individual channel enabling is done through the I2C register programming.
Equalization Setting:
EQA[2:0] and EQB[2:0] are the selection pins for the equalization selection for each of the channels of A and B respectively.
Table 1. Equalization Setting
Equalizer setting (dB)
EQ2 EQ1 EQ0 EQ 4 Bits @ 1.25GHz @ 2.5GHz @ 3GHz @ 4GHz @ 5GHz @ 6GHz
0 0 0 0000 0 0.6 1.0 1.5 2.4 2.8
0 0 1 0001 0.15 1.2 1.7 2.4 3.5 4
0 1 0 0010 0.4 1.9 2.5 3.3 4.5 5
0 1 1 0011 0.6 2.5 3.2 4.2 5.3 5.8
1 0 0 0100 1.8 3.4 4.1 4.9 6.0 6.4
1 0 1 0101 2.1 3.9 4.7 5.6 6.7 7.1
1 1 0 0110 2.3 4.4 5.2 6.2 7.3 7.7
1110111 2.5 4.9 5.7 6.8 7.9 8.2
HIZ 0 0 1000 3.4 5.6 6.4 7.3 8.4 8.7
HIZ 0 1 1001 3.6 6.0 6.9 7.8 8.9 9.1
HIZ 1 0 1010 3.8 6.4 7.3 8.3 9.3 9.5
HIZ 1 1 1011 4.1 6.8 7.7 8.7 9.7 9.9
0 0 HIZ 1100 5.1 7.5 8.3 9.2 10.1 10.2
0 1 HIZ 1101 5.3 7.8 8.6 9.5 10.4 10.5
1 0 HIZ 1110 5.4 8.1 8.9 9.8 10.7 10.8
1 1 HIZ 1111 5.6 8.4 9.2 10.1 11 11.1
GODES WIDE/3100M
7
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Flat Gain Setting:
Flat Gain settings: FGA[0:1] and FGB[0:1] are the selection bits
for Flat Gain value for A and B channels.
Table 2. Flat Gain Setting
FGA1
FGB1
FGA0
FGB0 (dB)
0 0 -4
0 1 -2
1 0 0
1 1 2
Output Swing Setting:
SW0 is the selection bit for output swing for A and B channels.
Table 3. Output Swing Setting
SW0 mVp-p
0900
11,000
Signal Detect Threshold Level:
Table 4. Signal Detect Threshold Level Setting via I2C Bus Mode
SD_TH1 <I2C bit> SD_TH0 Threshold ON (mVppd) Threshold OFF (mVppd)
0 0 130 30
0 1 150 50
1 0 170 70
1 1 210 110
GODES WIDE/3100M
8
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
I2C Programming
Address assignment
A6 A5 A4 A3 A2 A1 A0 R/W
111AD3 AD2 AD1 AD0 1=R, 0=W
BYTE 0
Bit Type Power up condition Control affected Comment
7 R A3 Signal Detector Output
1= Activity 0=no
activity
6 R A2 Signal Detector Output
5 R A1 Signal Detector Output
4 R A0 Signal Detector Output
3 R B3 Signal Detector Output
2 R B2 Signal Detector Output
1 R B1 Signal Detector Output
0 R B0 Signal Detector Output
BYTE 1
Bit Type Power up condition Control affected Comment
7 R A3 RX Detector Output
1 = Far-end 50
-ohm detected
0 = Not detected
6 R A2 RX Detector Output
5 R A1 RX Detector Output
4 R A0 RX Detector Output
3 R B3 RX Detector Output
2 R B2 RX Detector Output
1 R B1 RX Detector Output
0 R B0 RX Detector Output
BYTE 2
Bit Type Power up condition Control affected Comment
7R/W 0 A3 Power down
1 = Power down
6R/W 0 A2 Power down
5R/W 0 A1 Power down
4R/W 0A0 Power down
3R/W 0 B3 Power down
2R/W 0 B2 Power down
1R/W 0 B1 Power down
0R/W 0 B0 Power down
GODES WIDE/3100M
9
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
BYTE 3
Bit Type Power up condition Control affected Comment
7R/W 0
Channel A0 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1
R/W 0Reserved Swing
See Table 3
0
R/W 0SW0
BYTE 4
Bit Type Power up condition Control affected Comment
7R/W 0
Channel A1 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1R/W 0Reserved Swing
See Table 3
0R/W 0SW0
BYTE 5
Bit Ty p e Power up condition Control affected Comment
7R/W 0
Channel A2 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1R/W 0Reserved Swing
See Table 3
0R/W 0SW0
I2C Programming Cont.
GODES WIDE/3100M
10
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
BYTE 6
Bit Ty p e Power up condition Control affected Comment
7R/W 0
Channel A3 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1R/W 0Reserved Swing
See Table 3
0R/W 0SW0
BYTE 7
Bit Ty p e Power up condition Control affected Comment
7R/W 0
Channel B0 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1R/W 0Reserved Swing
See Table 3
0R/W 0SW0
BYTE 8
Bit Ty p e Power up condition Control affected Comment
7R/W 0
Channel B1 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1R/W 0Reserved Swing
See Table 3
0R/W 0SW0
I2C Programming Cont.
GODES WIDE/3100M
11
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
BYTE 9
Bit Ty p e Power up condition Control affected Comment
7R/W 0
Channel B2 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1R/W 0Reserved Swing
See Table 3
0R/W 0SW0
BYTE 10
Bit Ty p e Power up condition Control affected Comment
7R/W 0
Channel B3 con-
figuration
EQ3
Equalizer
See Table 1
6R/W 0EQ2
5R/W 0EQ1
4R/W 0EQ0
3R/W 0FG1 Flat Gain
See Table 2
2R/W 0FG0
1R/W 0Reserved Swing
See Table 3
0R/W 0SW0
BYTE 11
Bit Ty p e Power up condition Control affected Comment
7R/W 0 A3 Signal Detector
1=Power Down
6R/W 0 A2 Signal Detector
5R/W 0 A1 Signal Detector
4R/W 0 A0 Signal Detector
3R/W 0 B3 Signal Detector
2R/W 0 B2 Signal Detector
1R/W 0 B1 Signal Detector
0R/W 0 B0 Signal Detector
I2C Programming Cont.
GODES WIDE/3100M
12
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
BYTE 12
Bit Ty p e Power up condition Control affected Comment
7R/W 0 A3 RX Detector
1=Power Down
6R/W 0 A2 RX Detector
5R/W 0 A1 RX Detector
4R/W 0 A0 RX Detector
3R/W 0 B3 RX Detector
2R/W 0B2 RX Detector
1=disable1R/W 0B1 RX Detector
0R/W 0B0 RX Detector
BYTE 13
Bit Ty p e Power up condition Control affected Comment
7R/W 0
Reserved
6R/W 0
5R/W 0
4R/W 0
3R/W 0
2R/W 0
1R/W 0SD_TH1 Signal Detector
Threshold
0R/W 0SD_TH0
BYTE 14 to 15 have '0' as Power-up condition
I2C Programming Cont.
GODES WIDE/3100M
13
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Reset and I2C Master Timing Diagram
SCL/SDA
I2C_RESET#
Trstpw
Master
Load
Trstd
ENI2C HIZ condition
I2C_RESET#
Recommended minimum reset pulse width Trstpw= 1μs
I2C master cycle start from I2C_RESET# pulse go high, Trstd = 200μs
ENI2C = HIZ to I2C_RESET#(high) (min), Ti2cm_rst = 1 uS.
I2C Operation
The integrated I2C interface operates as a master or slave device depending on the pin ENI2C being HIZ or HIGH respectively. Stan-
dard mode (100Kbps) is supported with 7-bit addressing. The data byte format is 8-bit bytes, and supports the format of indexing to be
compatible with other bus devices. In the Slave mode (ENI2C = HIGH), the device supports Read/Write. The bytes must be accessed in
sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred.
Address bits A3 to A0 are programmable to support multiple chips environment. The Data is loaded until a Stop sequence is issued.
In the master mode (ENI2C = HIZ), PI3EQX12908A2 supports up to 16 masters connected in daisy chain through connecting I2C_
DONE pin to I2C_RESET# pin of the next part.
Master EEPROM data starting address of the device address is indicated in the table below:
AD3, AD2,AD1,AD0 EEPROM Data Starting Location
0000
00h
0001
10h
0010
20h
0011
30h
0100
40h
0101
50h
0110
60h
0111
70h
1000
80h
1001 90h
1010 A0h
1011 B0h
1100 C0h
1101 D0h
1110
E0h
1111
F0h
1 (E PER/00M moo-or— 1000-00— woo-ur— 1000-0— 1000400000000 1000500000000 1000500000000 1000700000000 1000300000000 1000900000000 1000/\0000000 1000130000000 1000C0000000 1000D000000 100015000000 1000F000000 00000001 FF
14
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
When tying multiple PI3EQX12908A2 devices to the SDA and SCL bus, use the guidelines below to configure the devices. The user also
can refer the application notes for detail information.
• Use AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM.
Example below is for 4 devices. The first device in the sequence must be address 0x00h;
subsequent devices must follow the address order listed below.
– U1: AD[3:0] = 0000 = 0x00h,
– U2: AD[3:0] = 0001 = 0x10h,
– U3: AD[3:0] = 0010 = 0x20h,
– U4: AD[3:0] = 0011 = 0x30h
• For I2C Slave Mode operation, use a 2Kohms pull-up resistor on SDA and SCL pins. For I2C Master Mode operation, use a 1Kohm
pull-up resistor on SDA and SCL pins.
Daisy-chain I2C_RESET# and ALL_DONE from one device to the next device in the sequence so that they do not compete for the
EEPROM at the same time.
1. Tie ALL_DONE of U1 to I2C_RESET# of U2
2. Tie ALL_DONE of U2 to I2C_RESET# of U3
3. Tie ALL_DONE of U3 to I2C_RESET# of U4
4. Optional: Tie ALL_DONE output of U4 to a LED to show the devices has been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for 4pcs PI3EQX12908A2 device. Bold fonts in yellow are register
setting from Byte0 to Byte15 for each device in each line. Bold fonts in red is the EEPROM data location.
:10000000000000FF0000FFFFFFFFFF0000FF620194
:10001000000000FFFF0000FFFFFFFF0000FF620184
:10002000000000FFFFFF0000FFFFFF0000FF620174
:10003000000000FFFFFFFF0000FFFF0000FF620164
:1000400000000000000000000000000000000000B0
:1000500000000000000000000000000000000000A0
:100060000000000000000000000000000000000090
:100070000000000000000000000000000000000080
:100080000000000000000000000000000000000070
:100090000000000000000000000000000000000060
:1000A0000000000000000000000000000000000050
:1000B0000000000000000000000000000000000040
:1000C0000000000000000000000000000000000030
:1000D0000000000000000000000000000000000020
:1000E0000000000000000000000000000000000010
:1000F0000000000000000000000000000000000000
:00000001FF
2k bits (256 x 8-bit) EEPROM Date Example
Below is the sample of the I2C master reading waveform based on the setup above.
GODES WIDE/3100M
15
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the
most significant bit (MSB) first (see the I2C Data Transfer diagram). The PI3EQX12908A2 will never hold the clock line SCL LOW to
force the master into a wait state.
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge
clock pulse, the PI3EQX12908A2 will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during
the HIGH period of this clock pulse as indicated in the I2C Data Transfer diagram. The PI3EQX12908A2 will generate an acknowledge
after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI3EQX12908A2 will watch the next
byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the fol-
lowing clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit.
For a write cycle, the first data byte following the address byte is an index byte that is used by the PI3EQX12908A2. Data is transferred
with the most significant bit (MSB) first.
SCL
Macro A
Macro B
SCLO
(Before arbitration)
SCLO
(Before arbitration)
SCLO
(After arbitration)
SCLO
(After arbitration)
After SCL line has become “H”, take the
timing until the next state of SCLO = L
After SCL line has become “H”, take the
timing until the next state of SCLO = L
SCL Synchronization
When more than one I2C device becomes a master device and drives the SCL line, each device senses the state of SCL line and automati-
cally adjust the the drive timing by adjusting the timing to the timing to the slowest one.
GODES WIDE/3100M \H‘ \_ R/
16
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
1.Readsequence
start
R/W
ACK ACK ACK NOACK
stop
DEVSEL
DATAOUT DATAOUTN
ACK ACK ACK
DATAINN
DATAIN1
ACK
ACK
R/W
start
stop
2.Writesequence
3.Combinedsequence
INDEXBYTE ACK
ACK
R/W
start
DATAOUT1 ACK
ACK
R/W
start
ACK NOACK
DATAOUTN
stop
Notes:
1. only block read and block write from the lowest byte
are supported for this application.
2. for some I2C application, an offset address byte will be
presented at the second byte in write command, which
is called dummy byte here and will be simply ignored in
this application for correct interoperation.
I C Slave
2
DEVSEL INDEX BYTE
DEVSEL DEVSEL
I C Slave
2
I C Slave
2
I2C Data Transfer Sequence
SDA
SCL
SDA
SCL
S
START condition
P
STOP condition
I2C START and STOP conditions.
I2C Data Transfer
Start & Stop Conditions
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA
line while SCL is HIGH defines a STOP condition, as shown in the figure below. When a STOP condition is detected, index byte value
will be reset to 0.
GODES WIDE/3100M (VDD A VOH VDD VOL VDD A Vhys
17
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
LVCMOS I/O DC Specifications (VDD = 3.3 ± 10%, TA = -40 to 85°C)
Symbol Parameter Conditions Min. Typ. Max. Units
VIH DC input logic high VDD/2 +
0.7 VDD + 0.3 V
VIL DC input logic low -0.3 VDD/2 - 0.7 V
V
OH
DC output logic high At IOH = -200µA V
DD
- 0.2 V
V
OL
DC output logic low At IOL = +200µA 0.2 V
Vhys Hysteresis of Schmitt trigger input 0.8 V
SDA and SCL I/O for I2C-bus (VDD = 3.3 ± 10%, TA = -40 to 85°C)
Symbol Parameter Conditions Min. Typ. Max. Units
VIH DC input logic high VDD/2 +
0.7 VDD + 0.3 V
VIL DC input logic low -0.3 VDD/2 - 0.7 V
VOL DC output logic low IOL = 3mA 0.4 V
V
hys
Hysteresis of Schmitt trigger input 0.8 V
tof Output fall time from VIHmin to
VILmax
Bus capacity = 10 to
400pF 250 ns
fSCLK SCLK clock frequency 100 kHz
High Speed I/O AC/DC Specifications (VDD = 3.3 ± 10%, TA = -40 to 85°C)
Receiver Input (100Ω differential)
Symbol Parameter Conditions Min. Typ. Max. Units
CRX RX AC coupling capacitance 220 nF
S11 Input return loss
10MHz to 4GHz dif-
ferential 13
dB
1GHz to 4GHz common
mode 4
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Supply Voltage ................................ -0.5V to +4.0V
LVCMOS Input/Output Voltage ................. -0.5V to +4.0V
CML Input Voltage ........................-0.5V to (VDD+0.5)
CML Input Current .............................-30 to +30 mA
I2C pins ......................................... VDD+0.3 V
Storage Temperature ..........................65°C to +150°C
Max. Junction Temperature .............................125 °C
ESD HBM ..............................................2kV
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional op-
eration of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
GODES WIDE/3100M
18
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Symbol Parameter Conditions Min. Typ. Max. Units
S22 Output return loss
10MHz to 4GHz differ-
ential 21
dB
1GHz to 4GHz common
mode 4
RIN
DC single-ended input impedance 50 Ω
DC differential input impedance 100
ROUT
DC single-ended output impedance 50 Ω
DC differential output impedance 100
ZRX-HIZ
DC input CM input impedance during reset
or power down 200
VRX-DIFF-PP Differential Input Peak-to-peak Voltage Operational 1.2 Vppd
Input source common-mode noise DC – 200MHz 150 mVppd
TTX-IDLE-SET-TO-
IDLE
Max time to electrical idle after sending an
EIOS 4 8 ns
TTX-IDLE-TO-DIFF-
DATA
Max time to valid diff signal after leaving
electrical idle 4 8 ns
Vth + On threshold of signal detector Signal swing @ 4GHz 130 210 mVppd
Vth - Off threshold of signal detector Signal swing @ 100MHz 30 110 mVppd
VDD Power supply voltage 33.3 3.6 V
Pmax Max Supply power PRSNT#=0 1 W
Imax Max Supply current 330 mA
Pidle Supply power PRSNT#=1 36 mW
GP5GHZ
Peaking gain (Compensation at 5GHz, rela-
tive to 100MHz, 100mVp-p sine wave input)
SW<1:0>=01, FG<1:0>=10
EQ<3:0> = 1111
EQ<3:0> = 1000
EQ<3:0> = 0000
16.1
13.5
8.0 dB
Variation around typical -3 +3
GP6GHZ
Peaking gain (Compensation at 6GHz, rela-
tive to 100MHz, 100mVp-p sine wave input)
SW<1:0>=01, FG<1:0>=10
EQ<3:0> = 1111
EQ<3:0> = 1000
EQ<3:0> = 0000
17.2
14.8
9.0 dB
Variation around typical -3 +3
GF
Flat gain (100MHz, EQ<3:0> = 1000,
SW<1:0> = 01)
FG<1:0> = 11
FG<1:0> = 10
FG<1:0> = 01
FG<1:0> = 00
+2.0
-0.5
-2.0
-4.0
dB
Variation around typical -3 +3
V1dB_100M
-1dB compression point of output swing (at
100MHz)
SW0=1
SW0=0
1000
900 mVppd
V1dB_6G
-1dB compression point of output swing (at
6GHz) FG= 0dB, EQ = 0000 or 0(h)
SW0=1
SW0=0
600
540 mVppd
High Speed I/O AC/DC Specifications Cont.
\ (E PER/00M Latency From input to oulpm
19
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Symbol Parameter Conditions Min. Typ. Max. Units
VCoup Channel isolation 100MHz to 5GHz, Fig-
ure 1 (Note 1) 28 dB
Vnoise_input Input-referred noise
100MHz to 5GHz,
FG<1:0> = 11, EQ<3:0>
= 0000, Figure 2
0.5
mVRMS
100MHz to 5GHz,
FG<1:0> = 11, EQ<3:0>
= 1010, Figure 2
0.4
Vnoise_output Output-referred noise (Note 2)
100MHz to 5GHz,
FG<1:0> = 11, EQ<3:0>
= 0000, Figure 2
0.7
mVRMS
100MHz to 5GHz,
FG<1:0> = 11, EQ<3:0>
= 1010, Figure 2
0.8 1.6
Latency
t
pd
Latency
From input to output
0.2
ns
Jitter
Rj
Additive Random Jitter at 8Gb/s (worst
case)
PRBS31@24hrs
36” 5mils FR4
VID = 0.8mVp-p
DE = 0dB
EQ = 0100
0.0258 UI
Note 1: Measured using a vector-network analyzer (VNA) with -15dBm power level applied to the adjacent input. The VNA detects the signal at the output of the
victim channel. All other inputs and outputs are terminated with 50Ω.
Note 2: Guaranteed by design and characterization.
High Speed I/O AC/DC Specifications Cont.
GODES WIDE/3100M
20
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Characteristics of the SDA and SCl bus lines for Standard Mode I2C-bus devices(1)
Symbol Parameter Conditions Min. Typ. Max. Units
fSCL SCL clock frequency 100 _kHz
tHD;STA Hold time (repeated) START condition. After this period,
the first clock pulse is generated. 4.0 _
ms
tLOW LOW period of the SCL clock 4.7 _
tHIGH HIGH period of the SCL clock 4.0 _
tSU;STA Set-up time for a repeated START condition 4.7 _
tHD;DAT Data hold time 10 _ns
tSU;DAT Data set-up time 250 _
ns
trRise time of both SDA and SCL signals - 1000
tfFall time of both SDA and SCL signals 300
tSU;STO Set-up time for STOP condition 4.0 _ms
tBUF Bus free time between a STOP and STOP condition 4.7 _
CbCapacitive load for each bus line - 400 pF
Notes:
1. All values referred to VIH min and VIL max levels
GODES WIDE/3100M Wk % gmw % l 215 21 gWH F TIMH % FR4 DO L__|O $0
21
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
RX1+
RX1-
RX2+
RX2-
TX1+
TX1-
TX2+
TX2-
4-PORT VECTOR
NETWORK ANALYZER
N52454
PI3EQX12908A2
AGGRESSOR
SIGNAL
(0dBm)
VICTIM
INPUT
50Ω
50Ω
50Ω
50Ω
VICTIM
ONTPUT
Channel-Isolation Test Configuration
RX_+
RX_-
50Ω
50Ω
TX_+
TX_-
BALUN
PSPL 5315A
(200kHz TO 17GHz)
POWER METER
GIGATRONICS 8652A
WITH 80301A HEAD
(10MHz to 18GHz)
PI3EQX12908A2
Noise Test Configuration
AB C
FR4
Signal
Source
SmA
Connector
SmA
Connector
≤30IN
In Out
D.U.T.
AC Test Circuit Referenced in the Electrical Characteristic Table
22
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
SDA
SCL
tf
StHD;STA
tLOW
tHD;DAT
tSU;DAT
HIGH tSU;STA
tHD;STA
Sr tSU;STO PS
tftrtBUF
START STOP START
I2C Timing
VD+
Common Mode
Voltage
V_D+ - V_D-
0V
VCM VDIFF
VD-
VDIFFp-p
VDIFFp-p
Definition of Differential Voltage
and Differential Voltage Peak-to-Peak
\ (E PER/00M 4‘ 4‘ mi?
23
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Application Diagrams
Applications Information
GENERAL RECOMMENDATIONS
The PI3EQX12908A2 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the
details associated with high-speed design as well as providing a clean power supply. Refer to the information below and Revision 4 of
the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The Differential inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential impedance
of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of
vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side
of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return
currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the PI3EQX12908A2 is provided with an adequate power supply. First, the supply
(VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of theprinted circuit board. The layer
thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed
capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass
capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the PI3EQX12908A2. Smaller
body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 μF to
10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low
ESR ceramic.
Notes:
Hot Plug Detect feature operation is dependent on certain channel conditions, such as length.
For hot plug detect, reset will automatically go back to receiver detect (RXDET) cycle.
220nF
220nF
220nF
220nF
0-48in
0-48in
PI3EQX12908A2
AXRX+
AXRX-
AXTX+
AXTX-
50 ohm50 ohm
PRSNT#
SDA
SCL
AGND
SDA
SCL
3.3V
0V
VDD
GND
VDD
24
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Application Schematics
HOST Device o r
Connector
RX
TX
RX
TX
reserve for debug purpose
Cn
I2C SDA /
EEPROMSDA NC
I2C SCL /
EEPROMSCL
Connect to I2C SDA
R31=0ohm
R32=0ohm
SCL/DEMA1/FGA1
SDA/DEMA0/FGA0
R31=NC
ENI2C=High (I2C co ntrol)
R11=on, R19 =NC
SDA/DEMA0/FGA0
NCConnect to EEPROM SCL
SCL/DEMA1/FGA1
I2C SCL /
EEPROM
SCL
0AGF/0AMED/ADSmho0=23R
I2C SCL /
EEPROMSCL
Connect to I2C SCL
I2C SDA /
EEPROMSDA
R32=NC
R31=0ohm
SCL/DEMA1/FGA1
Connect to EEPROM SDA
I2C SDA /
EEPROM
SDA
ENI2C=NC(Master mode)
R11=NC, R19 =NC
ENI2C=Low (Pin strap c ontrol)
R11=NC , R19 =on
Cn
PI3EQX12908A2
8Gbps
0.1uF
10Gbps
Cn
IC Part
0.176uF~0.265uF
PI3EQX12908A2
Speed
Location
10GBASE-KR:
10GBASE-KX4:
4.7nF
Attention the IC part and differential TX AC coupling capacitor value.
ps. PI3EQX8908A/10908A pin 24
is GND(2016Mar22 )
D0RX_N
D1RX_P
D1RX_N
D2RX_P
D2RX_N
ALL_DONE#
EQA2 SD_TH
H0RX_N
H2RX_P
H2RX_N
H0RX_P
H1RX_P
ALL_DONE#
AD3/EQB0
H3RX_N
H1RX_N
H3RX_P
D2RX_N
D2RX_P
D0RX_P
RX_DET
H2TX_N
EQA2
FGB0/AD1
I2C_RST/SW0
EQA1
SD_TH
H0TX_N
ENI2C
H0TX_P
SDA/FGA0
ENI2C
H1TX_N
H3TX_P
FGB1/AD0
EQA0
H2TX_P
AD3/EQB0
EQB2
EQA0
SCL/FGA1
AD2/EQB1
H3TX_N
H1TX_P
EQB2
D0TX_P
D0TX_N
D1TX_P
D1TX_N
D2TX_P
D2TX_N
D3TX_P
D3TX_N
SDA/DEMA0/FGA0
SCL/DEMA1/FGA1
FGB1/AD0FGB0/AD1
0AGF/ADS1AGF/LCS
PRSNT#
PRSNT#
I2C_RST//SW 0
I2C SDA / EEPROM SDA
I2C SCL / EEPROM SCL
VDD_3.3V
VDD_3.3V
VDD_3.3V VDD_3.3VVDD_3.3V VDD_3.3V VDD_3.3VVDD_3.3V
VDD_3.3VVDD_3.3V
VDD_3.3VVDD_3.3V
VDD_3.3V VDD_3.3V
VDD_3.3V
VDD_3.3V
R8
0 ohm or NC
C6 0.176uF~0.265uF_0402
R140 ohm or NC
C5 0.176uF~0.265uF_0402
R3
0 ohm or NC
C10 0.176uF~0.265uF_0402
R25
0 ohm or NC
R320 ohm or NC
R10
2K ohm
C15 0.176uF~0.265uF_0402
R7
0 ohm or NC
C11 0.176uF~0.265uF_0402
C9 0.176uF~0.265uF_0402
R19
0 ohm or NC
R31
0 ohm
R18
0 ohm or NC
R24
0 ohm or NC
C4 0.176uF~0.265uF_0402
C1 0.176uF~0.265uF_0402
D1
LED_R
1 2
C12 0.176uF~0.265uF_0402
R310 ohm or NC
R9
0 ohm or NC
R5
0 ohm or NC
R4
0 ohm or NC
C18
0.1u_0402
C16 0.176uF~0.265uF_0402
R120 ohm or NC
U1
PI3EQX12908A2ZFE@TQFN54
19
20
45
44
9
10
43
42
11
12
40
39
13
14
38
37
15
16
54
21
22
18
23
24
53
32
33
5
41
52
34
35
4
3
50
49
36
8
2
1
48
7
6
47
25
26
17
28
29
46
30
31
27
51
EQA2
EQA1
B0TX+
B0TX-
VDD
A0RX+
B1TX+
B1TX-
A0RX-
A1RX+
B2TX+
B2TX-
A1RX-
VDD
B3TX+
B3TX-
A2RX+
A2RX-
FGB1/AD0
EQA0
RXDET
A3RX-
EQB2
GND
FGB0/AD1
A1TX-
A1TX+
B2RX+
VDD
PRSNT#
A0TX-
A0TX+
B1RX-
B1RX+
FGA1/SCL
FGA0/SDA
VDD
B3RX-
B0RX-
B0RX+
ENI2C
B3RX+
B2RX-
EQB1/AD2
I2C_Reset#/SW0
SD_TH
A3RX+
A3TX-
A3TX+
EQB0/AD3
A2TX-
A2TX+
ALL_DONE#
VDD
C13 0.176uF~0.265uF_0402
R10 ohm or NC
C3 0.176uF~0.265uF_0402
R6
0 ohm or NC
+
EC1
1.0uF_0805
C14 0.176uF~0.265uF_0402
R20
0 ohm or NC
C8 0.176uF~0.265uF_0402
R27
0 ohm or NC
R23
0 ohm or NC
C2 0.176uF~0.265uF_0402
R130 ohm or NC
C7 0.176uF~0.265uF_0402
R11
0 ohm or NC
R16
0 ohm or NC
R17
0 ohm or NC
R40
0 ohm or NC
C17
0.1u_0402
R15
0 ohm or NC
R28
0 ohm or NC
R33
0 ohm or NC
R2
0 ohm or NC
R26
0 ohm or NC
GODES (DPER/COM’ mm w u ‘ (D m m _ “mm ‘i5 50 m fi‘ 3 G) w a I UUUUUUUU‘UUUUUUUU a / ® 463a“) ‘4’, ,4 \r :x—w ‘ g 5 E; 3 C 7 777* 7; E273777WWW,7,€C7 w M 3 C \ ‘ 3 C4 ‘ 7a ‘ c ”r x m] m mnnnnmnnnnnnn m g ‘ "mg a TOP V‘EW conga 10 _ sommwgw am 750 7‘ Plus (5.x) 1m D DDDDDDD‘DDJD DD c. ‘ c. c. o 0 o T 94:; c. c. 9 a » El A El 7 32E7H+$+Higf c. c. c. $ c. E. o o o o o 93 E. c. c. iflDDDDDDDDEDDDDDDD A \Vosn asc RECOMMENDED uwn pmm map wEw) one: namsna ms PER/m H NOTE 1 ‘. E . . . . . . , . . n , m “mm m: w m ANGLES w amass _ . 2. cow-mm qus m m: mesa) VHEWAL me As wm ,5 M VERMNALS ”ESCR'PT'M' 5"°°"““- VE’Y “‘"‘ “"3” “3‘ "”33“ mm“ x mm mm Wm PACKAGE cons: ZF (mm . “4sz m suLnEmNc mu 5 chquNnEu um: PAWmN ‘5 ran REFERENCE ONLY DOCUMENY CONYROL 3" P941” REVISION' 0 15mm
25
A product Line of
Diodes Incorporated
PI3EQX12908A2
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2
Packaging Information 54-TQFN (ZF)
16-0180
Ordering Information
Ordering Number Package Code Package Description
PI3EQX12908A2ZFEX ZF 54-Contact, Very Thin Quad Flat No-Lead (TQFN)
Thermal Resistance - 54-contact ZF Package/72-contact ZL Package:
θJC .....................................................................................................11.5°C/W
θJA .....................................................No Airflow, 4 layer JEDEC 19.1°C/W
Notes:
• Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/
• E = Pb-free and Green
• Xsuffix=Tape/Reel
For latest package info.
please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/
GODES VDPERICDME
26
A product Line of
Diodes Incorporated
PI3EQX12908A2
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER
THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further no-
tice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or
any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer
or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all
the companies whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes
Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein
may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determi-
native format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval
of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge
and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated
products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by
Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
www.diodes.com November 2017
Diodes Incorporated
PI3EQX12908A2
Document Number DS40411 Rev 1-2

Products related to this Datasheet

PCIE EQX W-QFN55100-54 T&R 3.5K
PCIE EQX,W-QFN55100-54
PCIE EQX,W-QFN55100-54