PIC16(L)F18426,46 Datasheet by Microchip Technology

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6‘ MICRDCHIP
PIC16(L)F18426/46
14/20-Pin Full-Featured, Low Pin Count Microcontrollers
with XLP
Description
PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and
communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general
purpose and low-power applications. Features such as a 12-bit Analog-to-Digital Converter with
Computation (ADC2), Memory Access Partitioning (MAP), the Device Information Area (DIA), Power-
saving operating modes, and Peripheral Pin Select (PPS), offer flexible solutions for a wide variety of
custom applications.
Core Features
C Compiler Optimized RISC Architecture
Only 50 Instructions
Operating Speed:
DC – 32 MHz clock input
125 ns minimum instruction cycle
Interrupt Capability
16-Level Deep Hardware Stack
• Timers:
Up to two 24-bit timers
Up to four 8-bit timers
Up to four 16-bit timers
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
Variable prescaler selection
Variable window size selection
Configurable in hardware (Configuration Words) and/or software
Programmable Code Protection
Memory
Up to 28 KB Program Flash Memory
Up to 2 KB Data SRAM Memory
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 1
256B Data EEPROM
Direct, Indirect and Relative Addressing modes
Memory Access Partition (MAP):
– Write-protect
Customizable partition
Device Information Area (DIA)
Device Configuration Information (DCI)
Operating Characteristics
Operating Voltage Range:
1.8V to 3.6V (PIC16LF184XX)
2.3V to 5.5V (PIC16F184XX)
Temperature Range:
Industrial: -40°C to 85°C
Extended: -40°C to 125°C
Power-Saving Operation Modes
Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)
Idle: CPU Halted While Peripherals Operate
Sleep: Lowest Power Consumption
Peripheral Module Disable (PMD):
Ability to selectively disable hardware module to minimize active power consumption of unused
peripherals
Extreme Low-Power mode (XLP)
Sleep: 500 nA typical @ 1.8V
Sleep and Watchdog Timer: 900 nA typical @ 1.8V
eXtreme Low-Power (XLP) Features
Sleep mode: 50 nA @ 1.8, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
8 uA @ 32 kHz, 1.8V, typical
32 uA/MHz @ 1.8V, typical
Digital Peripherals
Configurable Logic Cell (CLC):
4 CLCs
Integrated combinational and sequential logic
Complementary Waveform Generator (CWG):
2 CWGs
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 2
Rising and falling edge dead-band control
Full-bridge, half-bridge, 1-channel drive
Multiple signal sources
Capture/Compare/PWM (CCP) modules:
4 CCPs
16-bit resolution for Capture/Compare modes
10-bit resolution for PWM mode
Pulse-Width Modulators (PWM):
2 10-bit PWMs
Numerically Controlled Oscillator (NCO):
Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input
clock
Input Clock: 0 Hz < fNCO < 32 MHz
Resolution: fNCO/220
Peripheral Pin Select (PPS):
I/O pin remapping of digital peripherals
Serial Communications:
– EUSART
1 EUSART(s)
RS-232, RS-485, LIN compatible
Auto-Baud Detect, Auto-wake-up on Start.
Master Synchronous Serial Port (MSSP)
2 MSSP(s)
• SPI
• I2C, SMBus and PMBus compatible
Data Signal Modulator (DSM)
Modulates a carrier signal with digital data to create custom carrier synchronized output
waveforms
Up to 18 I/O Pins:
Individually programmable pull-ups
Slew rate control
Interrupt-on-change with edge-select
Input level selection control (ST or TTL)
Digital open-drain enable
Timer modules:
– Timer0:
8/16-bit timer/counter
Synchronous or asynchronous operation
Programmable prescaler/postscaler
Time base for capture/compare function
Timer1/3/5 with gate control:
16-bit timer/counter
Programmable internal or external clock sources
Multiple gate sources
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 3
Multiple gate modes
Time base for capture/compare function
Timer2/4/6 with Hardware Limit Timer:
8-bit timers
Programmable prescaler/postscaler
Time base for PWM function
Hardware Limit (HLT) and one-shot extensions
Selectable clock sources
Signal Measurement Timer (SMT)
1 SMT(s)
24-bit timer/counter with programmable prescaler
Analog Peripherals
Analog-to-Digital Converter with Computation (ADC2):
12-bit with up to 17 external channels
Conversion available during Sleep
Automated post-processing
Automated math functions on input signals:
Averaging, filter calculations, oversampling and threshold comparison
Integrated charge pump for low-voltage operation
CVD support
Zero-Cross Detect (ZCD):
AC high voltage zero-crossing detection for simplifying TRIAC control
Synchronized switching control and timing
Temperature Sensor Circuit
• Comparator:
2 Comparators
Fixed Voltage Reference at (non)inverting input(s)
Comparator outputs externally accessible
Digital-to-Analog Converter (DAC):
5-bit resolution, rail-to-rail
Positive Reference Selection
Unbuffered I/O pin output
Internal connections to ADCs and comparators
Fixed Voltage Reference (FVR) module:
1.024V, 2.048V and 4.096V output levels
Flexible Oscillator Structure
High-Precision Internal Oscillator:
Software-selectable frequency range up to 32 MHz
±2% at calibration (nominal)
4x PLL for use with external sources
up to 32 MHz (4-8 MHz input)
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 4
2x PLL for use with the HFINTOSC
up to 32 MHz
Low-Power Internal 31 kHz Oscillator (LFINTOSC)
External 32.768 kHz Crystal Oscillator (SOCS)
External Oscillator Block with:
Three crystal/resonator modes up to 20 MHz
Three external clock modes up to 32 MHz
Fail-Safe Clock Monitor
Detects clock source failure
Oscillator Start-up Timer (OST)
Ensures stability of crystal oscillator sources
PIC16(L)F184XX Family Types
Table 1. Devices Included In This Data Sheet
Device
Program Flash Memory (Words)
Program Flash Memory (Kbytes)
Data Memory (EEPROM) (bytes)
Data SRAM (bytes)
I/O’s(2)
12-bit ADC2 (ch)
5-bit DAC
Comparators
CWG
Clock Ref
Timers (8/16-bit)
CCP
PWM
NCO
EUSART
MSSP (I2C/SPI)
CLC
DSM
PPS
XLP
PMD
Windowed Watchdog Timer
Memory Access Partition
Device Information Area
Debug(1)
PIC16(L)F18426 16384 28 256 2048 12 11 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I
PIC16(L)F18446 16384 28 256 2048 18 17 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I
Note: 
1. I - Debugging integrated on-chip.
2. One pin is input-only.
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 5
Table 2. Devices Not Included In This Data Sheet
Device
Program Flash Memory (Words)
Program Flash Memory (Kbytes)
Data Memory (EEPROM) (bytes)
Data SRAM (bytes)
I/O’s(2)
12-bit ADC2 (ch)
5-bit DAC
Comparators
CWG
Clock Ref
Timers (8/16-bit)
CCP
PWM
NCO
EUSART
MSSP (I2C/SPI)
CLC
DSM
PPS
XLP
PMD
Windowed Watchdog Timer
Memory Access Partition
Device Information Area
Debug(1)
PIC16(L)F18424 4096 7 256 512 12 11 1 2 2 1 4/4 4 2 1 1 1 4 1 Y Y Y Y Y Y I
PIC16(L)F18425 8192 14 256 1024 12 11 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I
PIC16(L)F18444 4096 7 256 512 18 17 1 2 2 1 4/4 4 2 1 1 1 4 1 Y Y Y Y Y Y I
PIC16(L)F18445 8192 14 256 1024 18 17 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I
PIC16(L)F18455 8192 14 256 1024 26 24 1 2 2 1 4/4 5 2 1 2 2 4 1 Y Y Y Y Y Y I
PIC16(L)F18456 16384 28 256 2048 26 24 1 2 2 1 4/4 5 2 1 2 2 4 1 Y Y Y Y Y Y I
Data Sheet Index:
1. DS40001985 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP
2. DS(TBD) Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP
3. DS(TBD) Data Sheet, 28-Pin Full-Featured, Low Pin Count Microcontrollers with XLP
Packages
Packages PDIP SOIC SSOP TSSOP UQFN
(4x4)
PIC16(L)F18426 ● ●
PIC16(L)F18446 ● ●
Note:  Pin details are subject to change.
Important:  For other small form-factor package availability and marking information, visit
www.microchip.com/ packaging or contact your local sales office.
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 6
.IZIZIIIZIZJ] [[[EEEE 16 15 14 13 DDDDDDDDD] DDDDDDDDDU
Pin Diagrams
1 14/16-Pin Diagrams
Figure 1. 14-Pin PDIP, SOIC, TSSOP
1
2
3
4
14
13
12
11
5
6
7
10
9
8
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2RC3
Rev. 00-000014A
6/21/2017
Figure 2. 16-Pin UQFN (4x4)
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
9
10
11
12
56
RC4
RC3
RC1
RC2
78
2
3
1
4
RA5
RA4
MCLR/VPP/RA3
RC5
15
16 13
14
NC
VDD
NC
VSS
Rev. 00-000016A
6/21/2017
Note:  It is recommended that the exposed bottom pad be connected to VSS.
Related Links
14/16-Pin Allocation Table
2 20-Pin Diagrams
Figure 3. 20-Pin PDIP, SOIC, SSOP
1
2
3
4
14
13
12
11
5
6
7
10
9
8
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
RC3
18
17
16
15
20
19
RC6
RC7
RB7
RB4
RB5
RB6
Rev. 00-000020A
6/21/2017
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 7
. 2019181716 678910
Figure 4. 20-Pin UQFN (4x4)
15 RA1/ICSPCLK
RA2
RC0
RC1
RC2
11
12
13
14
67
RC7
RB7
RB4
RB5
RB6
8910
2
3
1
18
19
20 1617
5
4
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
RC3
RC6
VSS
RA0/ICSPDAT
Rev. 00-000020B
6/21/2016
Note:  It is recommended that the exposed bottom pad be connected to VSS.
Related Links
20-Pin Allocation Table
Pin Allocation Tables
1 14/16-Pin Allocation Table
I/O
14-pin PDIP/SOIC/TSSOP
16-pin UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupts
Pull-up
Basic
RA0 13 12 ANA0 C1IN0+ DAC1OUT1 MDSRC(1) — SS2(1) IOCA0 Y
ICDDAT
ICSPDAT
RA1 12 11 ANA1 ADCVREF+
C1IN0
C2IN0-
DAC1VREF+ IOCA1 Y
ICDCLK
ICSPCLK
RA2 11 10 ANA2 ADCVREF- DAC1VREF- T0CKI(1) CCP3IN(1)
CWG1IN(1)
CWG2IN(1)
ZCD1 IOCA2 Y INT(1)
RA3 4 3 T6IN(1) IOCA3 Y
MCLR
VPP
RA4 3 2 ANA4
T1G(1)
SMT1WIN(1)
IOCA4 Y
CLKOUT
SOSCO
OSC2
RA5 2 1 ANA5
T1CKI(1)
T2IN(1)
SMT1SIG(1)
— CLCIN3(1) IOCA5 Y
CLKIN
SOSCI
OSC1
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 8
I/O
14-pin PDIP/SOIC/TSSOP
16-pin UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupts
Pull-up
Basic
RC0 10 9 ANC0 C2IN0+ T5CKI(1) — —
SCK1(1)
SCL1(1,3,4)
IOCC0 Y
RC1 9 8 ANC1
C1IN1-
C2IN1-
— T4IN(1) CCP4IN(1) — —
SDI1(1)
SDA1(1,3,4)
— CLCIN2(1) IOCC1 Y
RC2 8 7
ANC2
ADACT(1)
C1IN2-
C2IN2-
— MDCARL(1) IOCC2 Y
RC3 7 6 ANC3
C1IN3-
C2IN3-
— T5G(1) CCP2IN(1) — SS1(1) — CLCIN0(1) IOCC3 Y
RC4 6 5 ANC4 T3G(1) — —
SCK2(1,5)
SCL2(1,3,4,5)
— CK1(1,3) CLCIN1(1) IOCC4 Y
RC5 5 4 ANC5 MDCARH(1) T3CKI(1) CCP1IN(1) — —
SDI2(1,5)
SDA2(1,3,4,5)
RX1(1)
DT1(1,3)
IOCC5 Y
VDD 1 16 VDD
VSS 14 13 VSS
OUT(2)
— — ADCGRDA C1OUT NCO1OUT DSM1OUT TMR0OUT CCP1OUT PWM6OUT
CWG1A
CWG2A
SDO1
SDO2
— DT1(3) CLC1OUT CLKR
— — ADCGRDB C2OUT CCP2OUT PWM7OUT
CWG1B
CWG2B
SCK1
SCK2
— CK1(3) CLC2OUT —
— — CCP3OUT
CWG1C
CWG2C
SCL1(3)
SCL2(3)
TX1 CLC3OUT —
— — CCP4OUT
CWG1D
CWG2D
SDA1(3)
SDA2(3)
CLC4OUT —
Note: 
1. This is a PPS re-mappable input signal. The input function may be moved from the default location
shown to one of several other PORTx pins.
2. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to
output onto one of several PORTx pin options.
3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the
same pin in both the PPS input and PPS output registers.
4. These pins may be configured for I2C logic levels. PPS assignments to the other pins will operate, but
input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific
or SMBUS input buffer thresholds.
5. MSSP2 is not available on the PIC16(L)F18424 or PIC16(L)F18444 devices.
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 9
2 20-Pin Allocation Table
I/O
20-pin PDIP/SOIC/TSSOP
20-pin UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupts
Pull-up
Basic
RA0 19 16 ANA0 C1IN0+ DAC1OUT1 IOCA0 Y
ICDDAT/
ICSPDAT
RA1 18 15 ANA1 ADCVREF
+
C1IN0-
C2IN0-
DAC1VREF
+MDSRC(1) — SS2(1) IOCA1 Y
ICDCLK/
ICSPCLK
RA2 17 14 ANA2 ADCVREF- DAC1VREF- T0CKI(1) — —
CWG1IN(1)
CWG2IN(1)
ZCD1 — CLCIN0(1) IOCA2 Y INT(1)
RA3 4 1 IOCA3 Y
MCLR
VPP
RA4 3 20 ANA4
T1G(1)
SMT1WIN(1)
CCP4IN(1) IOCA4 Y
CLKOUT
SOSCO
OSC2
RA5 2 19 ANA5
T1CKI(1)
T2IN(1)
SMT1SIG(1)
IOCA5 Y
CLKIN
SOSCI
OSC1
RB4 13 10 ANB4 T5G(1) — —
SDI1(1)
SDA1(1,3,4)
— CLCIN2(1) IOCB4 Y
RB5 12 9 ANB5 CCP3IN(1) — —
SCK2(1,5)
SCL2(1,3,4,5)
RX1(1)
DT1(1,3)
CLCIN3(1) IOCB5 Y
RB6 11 8 ANB6
SCK1(1)
SCL1(1,3,4)
IOCB6 Y
RB7 10 7 ANB7 T6IN(1) — —
SDI2(1,5)
SDA2(1,3,4,5)
— CK1(1,3) IOCB7 Y
RC0 16 13 ANC0 C2IN0+
T3CKI(1)
T3G(1)
IOCC0 Y
RC1 15 12 ANC1
C1IN1-
C2IN1-
IOCC1 Y
RC2 14 11 ANC2 C1IN2- — MDCARL(1) T5CKI(1) IOCC2 Y
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 10
l‘) (1) (1) *W
I/O
20-pin PDIP/SOIC/TSSOP
20-pin UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupts
Pull-up
Basic
ADACT(1) C2IN2-
RC3 7 4 ANC3
C1IN3-
C2IN3-
— CCP2IN(1) — CLCIN1(1) IOCC3 Y
RC4 6 3 ANC4 IOCC4 Y
RC5 5 2 ANC5 MDCARH(1) T4IN(1) CCP1IN(1) IOCC5 Y
RC6 8 5 ANC6 SS1(1) IOCC6 Y
RC7 9 6 ANC7 IOCC7 Y
VDD 1 18 VDD
VSS 20 17 VSS
OUT(2)
ADCGRDA C1OUT NCO1OUT DSM1OUT TMR0OUT CCP1OUT PWM6OUT
CWG1A
CWG2A
SDO1
SDO2
— DT1(3) CLC1OUT CLKR
ADCGRDB C2OUT CCP2OUT PWM7OUT
CWG1B
CWG2B
SCK1
SCK2
— CK1(3) CLC2OUT —
— — CCP3OUT
CWG1C
CWG2C
SCL1(3)
SCL2(3)
TX1 CLC3OUT —
— — CCP4OUT
CWG1D
CWG2D
SDA1(3)
SDA2(3)
CLC4OUT —
Note: 
1. This is a PPS re-mappable input signal. The input function may be moved from the default location
shown to one of several other PORTx pins.
2. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to
output onto one of several PORTx pin options.
3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the
same pin in both the PPS input and PPS output registers.
4. These pins may be configured for I2C logic levels. PPS assignments to the other pins will operate, but
input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific
or SMBUS input buffer thresholds.
5. MSSP2 is not available on the PIC16(L)F18424 or PIC16(L)F18444 devices.
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 11
Table of Contents
Description.......................................................................................................................1
Core Features..................................................................................................................1
Memory............................................................................................................................1
Operating Characteristics................................................................................................2
Power-Saving Operation Modes......................................................................................2
eXtreme Low-Power (XLP) Features...............................................................................2
Digital Peripherals........................................................................................................... 2
Analog Peripherals.......................................................................................................... 4
Flexible Oscillator Structure.............................................................................................4
PIC16(L)F184XX Family Types.......................................................................................5
Packages.........................................................................................................................6
Pin Diagrams...................................................................................................................7
Pin Allocation Tables....................................................................................................... 8
1. Device Overview......................................................................................................15
2. Guidelines for Getting Started with PIC16(L)F18426/46 Microcontrollers...............21
3. Enhanced Mid-Range CPU..................................................................................... 26
4. Device Configuration............................................................................................... 28
5. Device Information Area.......................................................................................... 41
6. Device Configuration Information............................................................................ 44
7. Memory Organization.............................................................................................. 45
8. Resets..................................................................................................................... 82
9. Oscillator Module (with Fail-Safe Clock Monitor).....................................................96
10. Interrupts................................................................................................................119
11. Power-Saving Operation Modes............................................................................147
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 12
12. (WWDT) Windowed Watchdog Timer....................................................................157
13. (NVM) Nonvolatile Memory Control.......................................................................169
14. I/O Ports................................................................................................................ 191
15. (PPS) Peripheral Pin Select Module......................................................................220
16. (PMD) Peripheral Module Disable.........................................................................231
17. Interrupt-on-Change.............................................................................................. 241
18. (FVR) Fixed Voltage Reference.............................................................................253
19. Temperature Indicator Module...............................................................................258
20. (ADC2) Analog-to-Digital Converter with Computation Module............................. 262
21. (DAC) 5-Bit Digital-to-Analog Converter Module...................................................310
22. Numerically Controlled Oscillator (NCO) Module.................................................. 316
23. (CMP) Comparator Module................................................................................... 327
24. (ZCD) Zero-Cross Detection Module.....................................................................340
25. Timer0 Module.......................................................................................................348
26. Timer1 Module with Gate Control..........................................................................357
27. Timer2 Module.......................................................................................................377
28. CCP/PWM Timer Resource Selection...................................................................404
29. Capture/Compare/PWM Module........................................................................... 408
30. (PWM) Pulse-Width Modulation............................................................................ 423
31. (CWG) Complementary Waveform Generator Module..........................................431
32. (DSM) Data Signal Modulator Module...................................................................461
33. (CLC) Configurable Logic Cell...............................................................................474
34. Reference Clock Output Module........................................................................... 496
35. (MSSP) Master Synchronous Serial Port Module................................................. 502
36. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter
...............................................................................................................................567
37. (SMT) Signal Measurement Timer.........................................................................602
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 13
38. Register Summary.................................................................................................629
39. In-Circuit Serial Programming (ICSP) .............................................................660
40. Instruction Set Summary....................................................................................... 663
41. Development Support............................................................................................686
42. Electrical Specifications.........................................................................................691
43. DC and AC Characteristics Graphs and Tables.................................................... 728
44. Packaging Information...........................................................................................730
45. Revision A (12/2017).............................................................................................752
The Microchip Web Site.............................................................................................. 753
Customer Change Notification Service........................................................................753
Customer Support....................................................................................................... 753
Product Identification System......................................................................................754
Microchip Devices Code Protection Feature............................................................... 754
Legal Notice.................................................................................................................755
Trademarks................................................................................................................. 755
Quality Management System Certified by DNV...........................................................756
Worldwide Sales and Service......................................................................................757
PIC16(L)F18426/46
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 14
1. Device Overview
This document contains device specific information for the following devices:
• PIC16F18426 • PIC16LF18426
• PIC16F18446 • PIC16LF18446
1.1 New Core Features
1.1.1 XLP Technology
All of the devices in the PIC16(L)F184XX family incorporate a range of features that can significantly
reduce power consumption during operation. Key items include:
Alternate Run Modes: By clocking the controller from the secondary oscillator or the internal
oscillator block, power consumption during code execution can be reduced by as much as 90%.
Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still
active. In these states, power consumption can be reduced even further, to as little as 4% of normal
operation requirements.
On-the-fly Mode Switching: The power-managed modes are invoked by user code during
operation, allowing the user to incorporate power-saving ideas into their application’s software
design.
Peripheral Module Disable: Modules that are not being used in the code can be selectively
disabled using the PMD module. This further reduces the power consumption.
1.1.2 Multiple Oscillator Options and Features
All of the devices in the PIC16(L)F184XX family offer several different oscillator options. The
PIC16(L)F184XX family can be clocked from several different sources:
• HFINTOSC
1-32 MHz precision digitally controlled internal oscillator
• LFINTOSC
31 kHz internal oscillator
• EXTOSC
External clock (EC)
Low-power oscillator (LP)
Medium-power oscillator (XT)
High-power oscillator (HS)
• SOSC
Secondary oscillator circuit optimized for 32 kHz clock crystals
A Phase Lock Loop (PLL) frequency multiplier (2x/4x) is available to the External Oscillator modes
enabling clock speeds of up to 32 MHz
Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference
signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal
oscillator block, allowing for continued operation or a safe application shutdown.
PIC16(L)F18426/46
Device Overview
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 15
1.2 Other Special Features
12-bit A/D Converter with Computation: This module incorporates programmable acquisition time,
allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling
period and thus, reduce code overhead. It has a new module called ADC2 with computation
features, which provides a digital filter and threshold interrupt functions.
Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last
for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM.
Data retention without refresh is conservatively estimated to be greater than 40 years.
Self-programmability: These devices can write to their own program memory spaces under internal
software control. By using a boot loader routine located in the protected Boot Block at the top of
program memory, it becomes possible to create an application that can update itself in the field.
Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral
inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All
analog inputs and outputs remain fixed to their assigned pins.
Windowed Watchdog Timer (WWDT):
Timer monitoring of overflow and underflow events
Variable prescaler selection
Variable window size selection
All sources configurable in hardware or software
1.3 Details on Individual Family Members
The devices of the PIC16(L)F184XX family described in the current datasheet are available in 14/20-pin
packages. The block diagram for this device is shown in Figure 1-1.
The devices have the following differences:
1. Program Flash Memory
2. Data Memory SRAM
3. Data Memory EEPROM
4. A/D channels
5. I/O ports
6. Enhanced USART
7. Input Voltage Range/Power Consumption
All other features for devices in this family are identical. These are summarized in the following Device
Features table.
The pinouts for all devices are listed in the pin summary tables.
Table 1-1. Device Features
Features PIC16(L)F18426 PIC16(L)F18446
Program Memory (KBytes) 28 28
Program Memory (Instructions) 16384 16384
Data Memory (Bytes) 2048 2048
Data EEPROM Memory (Bytes) 256 256
PIC16(L)F18426/46
Device Overview
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 16
Features PIC16(L)F18426 PIC16(L)F18446
Packages
14 - PDIP
14 - SOIC (3.9 mm)
14 - TSSOP
16 - uQFN (4x4)
20 - PDIP
20 - SOIC (7.5 mm)
20 - SSOP
20 - uQFN (4x4)
I/O Ports A, C A, B, C
Capture/Compare/PWM Modules
(CCP) 4 4
Configurable Logic Cell (CLC) 4 4
10-Bit Pulse-Width Modulator (PWM) 2 2
12-Bit Analog-to-Digital Module
(ADC2) with Computation
Accelerator
11 channels 17 channels
5-Bit Digital-to-Analog Module (DAC) 1 1
Comparators 2 2
Numerical Contolled Oscillator
(NCO) 1 1
Interrupt Sources 40 40
Timers (16-/8-bit) 4 4
Serial Communications
2 MSSP
1 EUSART
2 MSSP
1 EUSART
Complementary Waveform
Generator (CWG) 2 2
Zero-Cross Detect (ZCD) 1 1
Data Signal Modulator (DSM) 1 1
Reference Clock Output Module 1 1
Peripheral Pin Select (PPS) YES YES
Peripheral Module Disable (PMD) YES YES
Programmable Brown-out Reset
(BOR) YES YES
Resets (and Delays)
POR, BOR, RESET Instruction,
Stack Overflow, Stack
Underflow (PWRT, OST),
MCLR, WDT
POR, BOR, RESET Instruction,
Stack Overflow, Stack
Underflow (PWRT, OST),
MCLR, WDT
Instruction Set 50 instructions 50 instructions
PIC16(L)F18426/46
Device Overview
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 17
iii W W fffffffffffffff J¢¢¢$¢¢¢¢$JJ$¢$$
Features PIC16(L)F18426 PIC16(L)F18446
16-levels hardware stack 16-levels hardware stack
Operating Frequency DC – 32 MHz DC – 32 MHz
Figure 1-1. PIC16(L)F18426/46 Device Block Diagram
Note: 
1. See applicable chapters for more information on peripherals.
2. PORTB available only on 20-pin or higher pin-count devices.
1.4 Register and Bit naming conventions
1.4.1 Register Names
When there are multiple instances of the same peripheral in a device, the peripheral control registers will
be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The
control registers section will show just one instance of all the register names with an ‘x’ in the place of the
peripheral instance number. This naming convention may also be applied to peripherals when there is
only one instance of that peripheral in the device to maintain compatibility with other devices in the family
that contain more than one.
1.4.2 Bit Names
There are two variants for bit names:
Short name: Bit function abbreviation
Long name: Peripheral abbreviation + short name
PIC16(L)F18426/46
Device Overview
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 18
1.4.2.1 Short Bit Names
Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with
the EN bit. The bit names shown in the registers are the short name variant.
Short bit names are useful when accessing bits in C programs. The general format for accessing bits by
the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the CM1CON0
register can be set in C programs with the instruction CM1CON0bits.EN = 1.
Short names are generally not useful in assembly programs because the same name may be used by
different peripherals in different bit positions. When this occurs, during the include file generation, all
instances of that short bit name are appended with an underscore plus the name of the register in which
the bit resides to avoid naming contentions.
1.4.2.2 Long Bit Names
Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit name unique. The long bit name for the COG1
enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique
bit name G1EN.
Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable
bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF
COG1CON0,G1EN instruction.
1.4.2.3 Bit Fields
Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only
possible in C programs. The following example demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name
appended with the number of the bit position within the field. For example, the Most Significant mode bit
has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to Push-Pull mode:
Example 1:
MOVLW ~(1<<G1MD1)
ANDWF COG1CON0,F
MOVLW 1<<G1MD2 | 1<<G1MD0
IORWF COG1CON0,F
Example 2:
BSF COG1CON0,G1MD2
BCF COG1CON0,G1MD1
BSF COG1CON0,G1MD0
1.4.3 Register and Bit Naming Exceptions
1.4.3.1 Status, Interrupt, and Mirror Bits
Status, interrupt enables, interrupt flags, and mirror bits are contained in registers that span more than
one peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant.
PIC16(L)F18426/46
Device Overview
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 19
1.4.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that
have existed for many years and are present in almost every device are the exceptions. These
exceptions were necessary to limit the adverse impact of the new conventions on legacy code.
Peripherals that do adhere to the new convention will include a table in the registers section indicating the
long name prefix for each peripheral instance. Peripherals that fall into the exception category will not
have this table. These peripherals include, but are not limited to the following:
• EUSART
• MSSP
1.4.4 Register Legend
The table below describes the conventions for bit types and bit reset values used in the current data
sheet.
Table 1-2. Register Legend
Value Description
RO Read-only bit
W Writable bit
U Unimplemented bit, read as ‘0
1 Bit is set
0 Bit is cleared
xBit is unknown
uBit is unchanged
-n/n Value at POR and BOR/Value at all other Resets
qReset Value is determined by hardware
fReset Value is determined by fuse setting
gReset Value at POR for PPS re-mappable signals
PIC16(L)F18426/46
Device Overview
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 20
“HT—#4 W “H
2. Guidelines for Getting Started with PIC16(L)F18426/46
Microcontrollers
2.1 Basic Connection Requirements
Getting started with the PIC16(L)F18426/46 family of 8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with development.
The following pins must always be connected:
All VDD and VSS pins (see Power Supply Pins)
MCLR pin (see Master Clear (MCLR) Pin)
These pins must also be connected if they are being used in the end application:
PGC/PGD pins used for In-Circuit Serial Programming (ICSP) and debugging purposes (see In-
Circuit Serial Programming ICSP Pins)
OSCI and OSCO pins when an external oscillator source is used (see External Oscillator Pins)
Additionally, the following may be required:
• VREF+/VREF- pins are used when external voltage reference for analog modules is implemented
The minimum mandatory connections are shown in the figure below.
Figure 2-1. Recommended Minimum Connections
Filename:
Title:
Last Edit:
First Used:
Note:
10-000249B.vsd
Getting Started on PIC18
6/27/2017
PIC16(L)F153xx
Generic figure showing the MCLR, VDD and VSS pin connections.
C1
R1
Rev. 10-000249B
6/27/2017
VDD
PIC16(L)Fxxxxx
R2
MCLR
C2
VDD
Vss
Vss
Key (all values are recommendations):
C1: 10 nF, 16V ceramic
C2: 0.1 uF, 16V ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
2.2 Power Supply Pins
2.2.1 Decoupling Capacitors
The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required.
Consider the following criteria when using decoupling capacitors:
Value and type of capacitor: A 0.1 μF (100 nF), 10-25V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
PIC16(L)F18426/46
Guidelines for Getting Started with PIC16(L)F18426...
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 21
WHH R1
Placement on the printed circuit board: The decoupling capacitors should be placed as close to the
pins as possible. It is recommended to place the capacitors on the same side of the board as the
device. If space is constricted, the capacitor can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch
(6 mm).
Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of
MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor.
The value of the second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second
capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as close to the power and ground pins as possible
(e.g., 0.1 μF in parallel with 0.001 μF).
Maximizing performance: On the board layout from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain. Equally important is to keep the trace length
between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.
2.2.2 Tank Capacitors
On boards with power traces running longer than six inches in length, it is suggested to use a tank
capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of
the tank capacitor should be determined based on the trace resistance that connects the power supply
source to the device, and the maximum current drawn by the device in the application. In other words,
select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range
from 4.7 μF to 47 μF.
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions: Device Reset, and Device Programming and
Debugging. If programming and debugging are not required in the end application, a direct connection to
VDD may be all that is required. The addition of other components, to help increase the application’s
resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in
Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements.
During programming and debugging, the resistance and capacitance that can be added to the pin must
be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging
operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations.
Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin.
Figure 2-2. Example of MCLR Pin Connections
Note 1: R1 10 k is recommendedPA suggested
starting value is 10 k P Ensure that the
MCLR pin VIH and VIL specifications are metP
2: R2 470 will limit any current flowing into
MCLR from the external capacitorOC1Oin the
event of MCLR pin breakdownO due to
Electrostatic Discharge DESD( or Electrical
Overstress DEOS(PEnsure that the MCLR pin
VIH and VIL specifications are metP
C1
R2
R1
VDD
JP
MCLR
Rev. 30-000058A
6/23/2017
Note: 
PIC16(L)F18426/46
Guidelines for Getting Started with PIC16(L)F18426...
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 22
1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH
and VIL specifications are met.
2. R2 ≤ 470Ω will limit any current flowing into MCLR from the extended capacitor, C1, in the event of
MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure
that the MCLR pin VIH and VIL specifications are met.
2.4 In-Circuit Serial Programming ICSP Pins
The ICSPCLK and ICSPDAT pins are used for In-Circuit Serial Programming (ICSP) and debugging
purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on
the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series
resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended
as they can interfere with the programmer/debugger communications to the device. If such discrete
components are an application requirement, they should be removed from the circuit during programming
and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in
the respective device Flash programming specification for information on capacitive loading limits, and
pin input voltage high (VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins),
programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/
emulator tool.
For more information on available Microchip development tools connection requirements, refer to the
“Development Support” section.
Related Links
Development Support
2.5 External Oscillator Pins
Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator.
The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should be placed next to the oscillator itself, on the same
side of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or
power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side
of the board where the crystal is placed.
Layout suggestions are shown in the following figure. In-line packages may be handled with a single-
sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always
possible to completely surround the pins and components. A suitable solution is to tie the broken guard
sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground.
PIC16(L)F18426/46
Guidelines for Getting Started with PIC16(L)F18426...
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 23
Figure 2-3. Suggested Placement of the Oscillator Circuit
GND
`
`
`
OSC1
OSC2
SOSCO
SOSCI
Copper Pour Primary Oscillator
Crystal
Secondary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
SOSC: C1 SOSC: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
(SOSC)
Rev. 30-000059A
4/6/2017
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall
times, and other similar noise).
For additional information and design guidance on oscillator circuits, refer to these Microchip Application
Notes, available at the corporate website (www.microchip.com):
AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC and PICmicro® Devices”
AN849, “Basic PICmicro® Oscillator Design”
AN943, “Practical PICmicro® Oscillator Analysis and Design”
AN949, “Making Your Oscillator Work”
Related Links
Oscillator Module (with Fail-Safe Clock Monitor)
PIC16(L)F18426/46
Guidelines for Getting Started with PIC16(L)F18426...
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 24
2.6 Unused I/Os
Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a
1kΩ to 10 kΩ resistor to VSS on unused pins to drive the output to logic low.
PIC16(L)F18426/46
Guidelines for Getting Started with PIC16(L)F18426...
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 25
3. Enhanced Mid-Range CPU
This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 50 instructions.
Interrupt capability includes automatic context saving. The hardware stack is 16-levels deep and has
Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available.
The two File Select Registers (FSRs) provide the ability to read program and data memory.
Figure 3-1. Core Data Path Diagram
Filename: 10-000055C.vsd
Title: CORE BLOCK DIAGRAM (DATA FLOW)
Last Edit: 11/30/2016
First Used: 16(L)F183XX
Notes:
Rev. 10-000055C
11/30/2016
15
15
15
15
8
8
8
12
14
7
5
3
Program Counter
MUX
Addr MUX
16-Level Stack
(15-bit)
Program Memory
Read (PMR)
Instruction Reg
Configuration
FSR0 Reg
FSR1 Reg
BSR Reg
STATUS Reg
RAM
W Reg
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Instruction
Decode and
Control
Timing
Generation
Internal
Oscillator
Block
ALU
Flash
Program
Memory
MUX
Data Bus
Program
Bus
Direct Addr
Indirect
Addr
RAM Addr
CLKIN
CLKOUT
VDD VSS
12
12
SOSCI
SOSCO
3.1 Automatic Interrupt Context Saving
During interrupts, certain registers are automatically saved in shadow registers and restored when
returning from the interrupt. This saves stack space and user code.
Related Links
Automatic Context Saving
PIC16(L)F18426/46
Enhanced Mid-Range CPU
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 26
3.2 16-Level Stack with Overflow and Underflow
These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON0 register, and if enabled, will
cause a software Reset.
Related Links
Stack
PCON0
3.3 File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory,
which allows one Data Pointer for all memory. When an FSR points to program memory, there is one
additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose
memory can also be addressed linearly, providing the ability to access contiguous data larger than 80
bytes.
Related Links
Indirect Addressing
3.4 Instruction Set
There are 50 instructions for the enhanced mid-range CPU to support the features of the CPU.
Related Links
Instruction Set Summary
PIC16(L)F18426/46
Enhanced Mid-Range CPU
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 27
4. Device Configuration
Device configuration consists of the Configuration Words, User ID, Device ID, Device Information Area
(DIA), and the Device Configuration Information (DCI) regions.
Related Links
Device Information Area
Device Configuration Information
4.1 Configuration Words
The devices have five Configuration Words starting at address 8007h through 800Bh. The Configuration
bits establish configuration values prior to the execution of any software; Configuration bits enable or
disable device-specific features.
In terms of programming, these important Configuration bits should be considered:
1. LVP: Low-Voltage Programming Enable Bit
1 = ON – Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE
Configuration bit is ignored.
0 = OFF – HV on MCLR/VPP must be used for programming.
2. CP: User Nonvolatile Memory (NVM) Program Memory Code Protection bit
1 = OFF – User NVM code protection disabled
0 = ON – User NVM code protection enabled
4.2 Code Protection
Code protection allows the device to be protected from unauthorized access. Program memory protection
and data memory protection are controlled independently. Internal access to the program memory is
unaffected by any code protection setting.
4.2.1 Program Memory Protection
The entire program memory space is protected from external reads and writes by the CP bit. When CP =
0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can
continue to read program memory, regardless of the protection bit settings. Self-writing the program
memory is dependent upon the write protection setting.
4.3 Write Protection
Write protection allows the device to be protected from unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other regions of the program memory to be modified.
The WRT bits define the size of the program memory block that is protected.
4.4 User ID
Four words in the memory space (8000h-8003h) are designated as ID locations where the user can store
checksum or other code identification numbers. These locations are readable and writable during normal
execution. See the “NVMREG Access to Device Information Area, Device Configuration Area, User ID,
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 28
Device ID, EEPROM, and Configuration Words” section for more information on accessing these memory
locations. For more information on checksum calculation, see the “PIC16(L)F184XX Memory
Programming Specification”, (DS40001970).
Related Links
NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and
Configuration Words
4.5 Device ID and Revision ID
The 14-bit device ID word is located at 0x8006 and the 14-bit revision ID is located at 0x8005. These
locations are read-only and cannot be erased or modified.
Development tools, such as device programmers and debuggers, may be used to read the Device ID,
Revision ID and Configuration Words. Refer to the “Nonvolatile Memory (NVM) Control” section for more
information on accessing these locations.
Related Links
(NVM) Nonvolatile Memory Control
4.6 Register Summary - Configuration Words
Offset Name Bit Pos.
0x8007 CONFIG1 7:0 RSTOSC[2:0] FEXTOSC[2:0]
13:8 FCMEN CSWEN CLKOUTEN
0x8008 CONFIG2 7:0 BOREN LPBOREN PWRTS[1:0] MCLRE
13:8 DEBUG STVREN PPS1WAY ZCDDIS BORV
0x8009 CONFIG3 7:0 WDTE[1:0] WDTCPS[4:0]
13:8 WDTCCS[2:0] WDTCWS[2:0]
0x800A CONFIG4 7:0 WRTAPP SAFEN BBEN BBSIZE[2:0]
13:8 LVP WRTSAF WRTD WRTC WRTB
0x800B CONFIG5 7:0 CP
13:8
4.7 Register Definitions: Configuration Words
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 29
4.7.1 CONFIG1
Name:  CONFIG1
Address:  0x8007
Configuration word 1
Oscillators
Bit 15 14 13 12 11 10 9 8
FCMEN CSWEN CLKOUTEN
Access R/P U R/P U U R/P
Reset 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
RSTOSC[2:0] FEXTOSC[2:0]
Access U R/P R/P R/P U R/P R/P R/P
Reset 1 1 1 1 1 1 1 1
Bit 13 – FCMEN Fail-Safe Clock Monitor Enable bit
Value Description
1 FSCM timer enabled
0 FSCM timer disabled
Bit 11 – CSWEN Clock Switch Enable bit
Value Description
1 Writing to NOSC and NDIV is allowed
0 The NOSC and NDIV bits cannot be changed by user software
Bit 8 – CLKOUTEN Clock Out Enable bit
Value Condition Description
1 If FEXTOSC = EC (high, mid or low) or Not
Enabled
CLKOUT function is disabled; I/O or oscillator
function on OSC2
0 If FEXTOSC = EC (high, mid or low) or Not
Enabled
CLKOUT function is enabled; FOSC/4 clock
appears at OSC2
Otherwise This bit is ignored.
Bits 6:4 – RSTOSC[2:0] Power-up Default Value for COSC bits
This value is the Reset default value for COSC and selects the oscillator first used by user software.
Refer to COSC operation.
Value Description
111 EXTOSC operating per FEXTOSC bits
110 HFINTOSC (1 MHz), with OSCFRQ = ‘010’ (4 MHz) and CDIV = ‘0010’ (4:1)
101 LFINTOSC
100 SOSC
011 Reserved
010 EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 30
Value Description
001 HFINTOSC with 2x PLL (32 MHz), with OSCFRQ = ‘101’ (16 MHz) and CDIV = ‘0000’ (1:1)
000 Reserved
Bits 2:0 – FEXTOSC[2:0] FEXTOSC External Oscillator Mode Selection bits
Value Description
111 ECH (External Clock) above 8 MHz
110 ECM (External Clock) for 500 kHz to 8 MHz
101 ECL (External Clock) below 500 kHz
100 Oscillator not enabled
011 Reserved (do not use)
010 HS (Crystal oscillator) above 4 MHz
001 XT (Crystal oscillator) above 100 kHz, below 4 MHz
000 LP (crystal oscillator) optimized for 32.768 kHz
Related Links
OSCFRQ
OSCCON2
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 31
4.7.2 CONFIG2
Name:  CONFIG2
Address:  0x8008
Configuration Word 2
Supervisor
Bit 15 14 13 12 11 10 9 8
DEBUG STVREN PPS1WAY ZCD BORV
Access R/P R/P R/P R/P R/P U
Reset 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
BOREN[1:0] LPBOREN PWRTS[1:0] MCLRE
Access R/P R/P R/P U U R/P R/P R/P
Reset 1 1 1 1 1 1 1 1
Bit 13 – DEBUG  Debugger Enable bit(1)
Value Description
1 Background debugger disabled
0 Background debugger enabled
Bit 12 – STVREN Stack Overflow/Underflow Reset Enable bit
Value Description
1 Stack Overflow or Underflow will cause a Reset
0 Stack Overflow or Underflow will not cause a Reset
Bit 11 – PPS1WAY PPSLOCKED bit One-Way Set Enable bit
Value Description
1 The PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after
one clear/set cycle
0 The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
Bit 10 – ZCD ZCD Control bit
Value Description
1 ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of the ZCDCON register.
0 ZCD always enabled, ZCDSEN bit is ignored
Bit 9 – BORV  Brown-out Reset Voltage Selection bit(2)
Value Description
1 Brown-out Reset voltage (VBOR) set to lower trip point level
0 Brown-out Reset voltage (VBOR) set to higher trip point level
Bits 7:6 – BOREN[1:0] Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by BORV bit
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 32
Value Description
11 Brown-out Reset enabled, SBOREN bit is ignored
10 Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored
01 Brown-out Reset enabled according to SBOREN
00 Brown-out Reset disabled
Bit 5 – LPBOREN Low-Power BOR Enable bit
Value Description
1 Low-Power Brown-out Reset is disabled
0 Low-Power Brown-out Reset is enabled
Bits 2:1 – PWRTS[1:0] Power-up Timer Selection bits
Value Description
11 PWRT disabled
10 PWRT set at 64 ms
01 PWRT set at 16 ms
00 PWRT set at 1 ms
Bit 0 – MCLRE  Master Clear (MCLR) Enable bit
Value Condition Description
If LVP = 1RE3 pin function is MCLR (it will reset the device when driven low)
1 If LVP = 0MCLR pin is MCLR (it will reset the device when driven low)
0 If LVP = 0MCLR pin function is port defined function
Note: 
1. The DEBUG bit in Configuration Words is managed automatically by device development tools
including debuggers and programmers. For normal device operation, this bit should be maintained
as a ‘1’.
2. See VBOR parameter in the “Electrical Specifications” chapter for specific trip point voltages.
Related Links
Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset
Specifications
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 33
4.7.3 CONFIG3
Name:  CONFIG3
Address:  0x8009
Configuration Word 3
Windowed Watchdog Timer
Bit 15 14 13 12 11 10 9 8
WDTCCS[2:0] WDTCWS[2:0]
Access R/P R/P R/P R/P R/P R/P
Reset 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
WDTE[1:0] WDTCPS[4:0]
Access U R/P R/P R/P R/P R/P R/P R/P
Reset 1 1 1 1 1 1 1 1
Bits 13:11 – WDTCCS[2:0] WDT Input Clock Selector bits
Value Description
111 Software Control
110 to
011
Reserved
010 Reserved (no clock)/32 kHz SOSC
001 WDT reference clock is the 31.25 kHz HFINTOSC (MFINTOSC) output
000 WDT reference clock is the 31.0 kHz LFINTOSC
Bits 10:8 – WDTCWS[2:0] WDT Window Select bits
WDTCWS
WDTCON1 [WINDOW] at POR
Software
control of
WINDOW?
Keyed access
required?
Value
Window delay
Percent of
time
Window
opening
Percent of
time
111 111 n/a 100 Yes No
110 110 n/a 100
No Yes
101 101 25 75
100 100 37.5 62.5
011 011 50 50
010 010 62.5 37.5
001 001 75 25
000 000 87.5 12.5
Bits 6:5 – WDTE[1:0] WDT Operating Mode bits
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 34
Value Description
11 WDT enabled regardless of Sleep; SEN is ignored
10 WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit is ignored
01 WDT enabled/disabled by SEN bit
00 WDT disabled, SEN bit is ignored
Bits 4:0 – WDTCPS[4:0] WDT Period Select bits
WDTCPS
WDTCON0[WDTPS] at POR
Software Control of WDTPS?
Value Divider Ratio Typical Time Out
(FIN = 31 kHz)
11111 01011 1:65536 216 2s Yes
11110
...
10011
11110
...
10011
1:32 251 ms No
10010 10010 1:8388608 223 256s
No
10001 10001 1:4194304 222 128s
10000 10000 1:2097152 221 64s
01111 01111 1:1048576 220 32s
01110 01110 1:524288 219 16s
01101 01101 1:262144 218 8s
01100 01100 1:131072 217 4s
01011 01011 1:65536 216 2s
01010 01010 1:32768 215 1s
01001 01001 1:16384 214 512 ms
01000 01000 1:8192 213 256 ms
00111 00111 1:4096 212 128 ms
00110 00110 1:2048 211 64 ms
00101 00101 1:1024 210 32 ms
00100 00100 1:512 2916 ms
00011 00011 1:256 288 ms
00010 00010 1:128 274 ms
00001 00001 1:64 262 ms
00000 00000 1:32 251 ms
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 35
4.7.4 CONFIG4
Name:  CONFIG4
Address:  0x800A
Configuration Word 4
Memory Write Protection
Bit 15 14 13 12 11 10 9 8
LVP WRTSAF WRTD WRTC WRTB
Access R/W U R/W R/W R/W R/W
Reset 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
WRTAPP SAFEN BBEN BBSIZE[2:0]
Access R/W U U R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 0 0 1
Bit 13 – LVP Low-Voltage Programming Enable bit
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose
of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or
accidentally eliminating LVP mode from the Configuration state.
The preconditioned (erased) state for this bit is critical.
Value Description
1 Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration
bit is ignored.
0 HV on MCLR/VPP must be used for programming
Bit 11 – WRTSAF  Storage Area Flash Write Protection bit(1)
Value Description
1 SAF NOT write-protected
0 SAF write-protected
Bit 10 – WRTD  Data EEPROM Write Protection bit(1)
Value Description
1 Data EEPROM NOT write-protected
0 Data EEPROM write-protected
Bit 9 – WRTC  Configuration Register Write Protection bit(1)
Value Description
1 Configuration Registers NOT write-protected
0 Configuration Registers write-protected
Bit 8 – WRTB  Boot Block Write Protection bit(1)
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 36
Value Description
1 Boot Block NOT write-protected
0 Boot Block write-protected
Bit 7 – WRTAPP  Application Block Write Protection bit(1)
Value Description
1 Application Block NOT write-protected
0 Application Block write-protected
Bit 4 – SAFEN  SAF Enable bit(1)
Value Description
1 SAF disabled
0 SAF enabled
Bit 3 – BBEN  Boot Block Enable bit(1)
Value Description
1 Boot Block disabled
0 Boot Block enabled
Bits 2:0 – BBSIZE[2:0]  Boot Block Size Selection bits
BBSIZE is used only when BBEN = 0
BBSIZE bits can only be written while BBEN = 1; after BBEN = 0, BBSIZ is write-protected.
Table 4-1. Boot Block Size Bits
BBEN BBSIZE
Actual Boot Block Size User
Program Memory Size (words) Last Boot Block
Memory Access
PIC16(L)F18426/46
1 xxx 0
0 111 512 01FFh
0 110 1024 03FFh
0 101 2048 07FFh
0 100 4096 0FFFh
0 011-000 8192 1FFFh
Note:  The maximum boot block size is half the user program memory size. All selections higher than
the maximum are set to half size. For example, all BBSIZE = 000 - 100 produce a boot block size of 4
kW on a 8 kW device.
Note: 
1. Bits are implemented as sticky bits. Once protection is enabled, it can only be reset through a Bulk
Erase.
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 37
4.7.5 CONFIG5
Name:  CONFIG5
Address:  0x800B
Configuration Word 5
Code Protection
Bit 15 14 13 12 11 10 9 8
Access U U U U U U
Reset 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
CP
Access U U U U U U U R/P
Reset 1 1 1 1 1 1 1 1
Bit 0 – CP Program Flash Memory Code Protection bit
Value Description
1 Program Flash Memory code protection disabled
0 Program Flash Memory code protection enabled
4.8 Register Summary - Device and Revision
Offset Name Bit Pos.
0x8005 REVISION ID 7:0 MJRREV[1:0] MNRREV[5:0]
13:8 1 0 MJRREV[5:2]
0x8006 DEVICE ID 7:0 DEV[7:0]
13:8 1 1 DEV[11:8]
4.9 Register Definitions: Device and Revision
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 38
4.9.1 DEVICE ID
Name:  DEVICE ID
Address:  0x8006
Device ID Register
Bit 15 14 13 12 11 10 9 8
1 1 DEV[11:8]
Access R R R R R R
Reset
Bit 7 6 5 4 3 2 1 0
DEV[7:0]
Access R R R R R R R R
Reset
Bit 13 – 1
These bit must be ‘1’ to be distinguishable from the previous Device ID scheme
Bit 12 – 1
These bit must be ‘1’ to be distinguishable from the previous Device ID scheme
Bits 11:0 – DEV[11:0]
Device ID bits
Device Device ID
PIC16F18426 30D2h
PIC16LF18426 30D3h
PIC16F18446 30D4h
PIC16LF18446 30D5h
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 39
4.9.2 REVISION ID
Name:  REVISION ID
Address:  0x8005
Revision ID Register
Bit 15 14 13 12 11 10 9 8
1 0 MJRREV[5:2]
Access R R R R R R
Reset 1 0
Bit 7 6 5 4 3 2 1 0
MJRREV[1:0] MNRREV[5:0]
Access R R R R R R R R
Reset
Bit 13 – 1 Read as ‘1’
These bits are fixed with value ‘1’ for all devices in this family.
Bit 12 – 0 Read as ‘0’
These bits are fixed with value ‘0’ for all devices in this family.
Bits 11:6 – MJRREV[5:0] Major Revision ID bits
These bits are used to identify a major revision.
Bits 5:0 – MNRREV[5:0] Minor Revision ID bits
These bits are used to identify a minor revision.
PIC16(L)F18426/46
Device Configuration
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 40
5. Device Information Area
The Device Information Area (DIA) is a dedicated region in the program memory space; it is a new
feature in the PIC16(L)F184XX family of devices. The DIA contains the calibration data for the internal
temperature indicator module, stores the Microchip Unique Identifier words, and the Fixed Voltage
Reference voltage readings measured in mV. The complete DIA table is shown below, followed by a
description of each region and its functionality. The data is mapped from 8100h to 811Fh in the
PIC16(L)F184XX family. These locations are read-only and cannot be erased or modified. The data is
programmed into the device during manufacturing.
Table 5-1. Device Information Area
Address Range Name of Region Standard Device Information
8100h-8108h
MUI0
Microchip Unique Identifier (9 Words)
MUI1
MUI2
MUI3
MUI4
MUI5
MUI6
MUI7
MUI8
8109h MUI9 1 Word Reserved
810Ah-8111h
EUI0
Unassigned (8 Words)
EUI1
EUI2
EUI3
EUI4
EUI5
EUI6
EUI7
8112h TSLR1 Unassigned (1 word)
8113h TSLR2 Temperature indicator ADC reading at 90°C (low range setting)
8114h TSLR3 Unassigned (1 word)
8115h TSHR1 Unassigned (1 word)
8116h TSHR2 Temperature indicator ADC reading at 90°C (high range setting)
8117h TSHR3 Unassigned (1 word)
PIC16(L)F18426/46
Device Information Area
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 41
Address Range Name of Region Standard Device Information
8118h FVRA1X ADC FVR1 Output voltage for 1x setting (in mV)
8119h FVRA2X ADC FVR1 Output Voltage for 2x setting (in mV)
811Ah FVRA4X(1) ADC FVR1 Output Voltage for 4x setting (in mV)
811Bh FVRC1X Comparator FVR2 output voltage for 1x setting (in mV)
811Ch FVRC2X Comparator FVR2 output voltage for 2x setting (in mV)
811Dh FVRC4X(1) Comparator FVR2 output voltage for 4x setting (in mV)
811Eh-811Fh Unassigned (2 Words)
Note: 
1. Value not present on LF devices.
5.1 Microchip Unique identifier (MUI)
The PIC16(L)F184XX devices are individually encoded during final manufacturing with a Microchip
Unique Identifier, or MUI. The MUI cannot be erased by a Bulk Erase command or any other user-
accessible means. This feature allows for manufacturing traceability of Microchip Technology devices in
applications where this is required. It may also be used by the application manufacturer for a number of
functions that require unverified unique identification, such as:
Tracking the device
Unique serial number
The MUI consists of nine program words and one reserved program word. When taken together, these
fields form a unique identifier. The MUI is stored in read-only locations, located between 8100h to 8109h
in the DIA space. The above table lists the addresses of the identifier words.
Important:  For applications that require verified unique identification, contact your Microchip
Technology sales office to create a Serialized Quick Turn Programming option.
5.2 External Unique Identifier (EUI)
The EUI data is stored at locations 810Ah to 8111h in the program memory region. This region is an
optional space for placing application specific information. The data is coded per customer requirements
during manufacturing. The EUI cannot be erased by a Bulk Erase command.
Important:  Data is stored in this address range on receiving a request from the customer. The
customer may contact the local sales representative or Field Applications Engineer, and provide
them the unique identifier information that is required to be stored in this region.
PIC16(L)F18426/46
Device Information Area
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 42
5.3 Analog-to-Digital Conversion Data of the Temperature Sensor
The purpose of the temperature indicator module is to provide a temperature-dependent voltage that can
be measured by an analog module. The “Temperature Indicator Module” chapter explains the operation of
the Temperature Indicator module and defines terms such as the low range and high range settings of the
sensor. The DIA table contains the internal ADC measurement values of the temperature sensor for low
and high range at fixed points of reference. The values are measured during test and are unique to each
device. The right-justified ADC readings are stored in the DIA memory region. The calibration data can be
used to plot the approximate sensor output voltage, VTSENSE vs. Temperature curve.
TSLR: Address 8112h to 8114h store the measurements for the low range setting of the
temperature sensor at VDD = 3V.
TSHR: Address 8115h to 8117h store the measurements for the high range setting of the
temperature sensor at VDD = 3V.
The stored measurements are made by the device ADC using the internal VREF = 2.048V.
Related Links
Temperature Indicator Module
5.4 Fixed Voltage Reference Data
The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference
voltage to the following:
ADC input channel
ADC positive reference
Comparator positive input
Digital-to-Analog Converter
For more information on the FVR, refer to the “Fixed Voltage Reference (FVR)” chapter (see related
links).
The DIA stores measured FVR voltages for this device in mV for the different buffer settings of 1x, 2x or
4x at program memory locations 8118h to 811Dh.
FVRA1X stores the value of ADC FVR1 Output voltage for 1x setting (in mV)
FVRA2X stores the value of ADC FVR1 Output Voltage for 2x setting (in mV)
FVRA4X stores the value of ADC FVR1 Output Voltage for 4x setting (in mV)
FVRC1X stores the value of Comparator FVR2 output voltage for 1x setting (in mV)
FVRC2X stores the value of Comparator FVR2 output voltage for 2x setting (in mV)
FVRC4X stores the value of Comparator FVR2 output voltage for 4x setting (in mV)
Related Links
(FVR) Fixed Voltage Reference
PIC16(L)F18426/46
Device Information Area
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 43
6. Device Configuration Information
The Device Configuration Information (DCI) is a dedicated region in the Program Flash Memory mapped
from 8200h to 821Fh. The data stored in the DCI memory is hard-coded into the device during
manufacturing. Refer to the table below for the complete DCI table address and description. The DCI
holds information about the device which is useful for programming and bootloader applications. These
locations are read-only and cannot be erased or modified.
Table 6-1. Device Configuration Information for Devices
ADDRESS Name DESCRIPTION PIC16(L)F18426/46 UNITS
8200h ERSIZ Erase Row Size 32 Words
8201h WLSIZ Number of write latches 32 Latches
8202h URSIZ Number of User Rows 512 Rows
8203h EESIZ EE Data memory size 256 Bytes
8204h PCNT Pin Count 14, 16, 20 Pins
6.1 DIA and DCI Access
The DIA and DCI data are read-only and cannot be erased or modified. See section “NVMREG Access to
Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and Configuration
Words” for more information on accessing these memory locations.
Development tools, such as device programmers and debuggers, may be used to read the DIA and DCI
regions, similar to the Device ID and Revision ID.
Related Links
NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM,
and Configuration Words
PIC16(L)F18426/46
Device Configuration Information
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 44
7. Memory Organization
These devices contain the following types of memory:
Program Memory
Configuration Words
Device ID
User ID
Program Flash Memory
Device Information Area (DIA)
Device Configuration Information (DCI)
Revision ID
Data Memory
Core Registers
Special Function Registers
General Purpose RAM
Common RAM
• EEPROM
The following features are associated with access and control of program memory and data memory:
PCL and PCLATH
• Stack
Indirect Addressing
NVMREG access
7.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program
memory space. The table below shows the memory sizes implemented. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see the following figure).
Table 7-1. Device Sizes And Addresses
Device Program Memory Size (Words) Last Program Memory Address
PIC16(L)F18426 16384 0x3FFF
PIC16(L)F18446 16384 0x3FFF
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 45
Figure 7-1. Program Memory and Stack
Filename: 10-000040J.vsd
Title: PROGRAM MEMORY MAP AND STACK
Last Edit: 3/3/2017
First Used: PIC16(L)F184XX
Notes:
Rev. 10-000040J
3/3/2017
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
0000h
0004h
0005h
07FFh
0800h
0FFFh
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
1000h
7FFFh
17FFh
1800h
1FFFh
2000h
3FFFh
4000h
Unimplemented
Page 0
PIC16(L)F18424/44
PIC16(L)F18425/45/55
PIC16(L)F18426/46/56
Related Links
CONFIG5
Memory Violation
7.1.1 Reading Program Memory as Data
There are three methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an FSR to point to the program memory. The third
method is to use the NVMREG interface to access the program memory.
Related Links
NVMREG Access
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 46
7.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access to tables of constants. The recommended way to
create such a table is shown in the following example.
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very simple to implement.
7.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by setting bit 7 of an FSRxH register and reading the
matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in
the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions
that read the program memory via the FSR require one extra instruction cycle to complete. The following
example demonstrates reading the program memory via an FSR.
The HIGH directive will set bit 7 if a label points to a location in the program memory. This applies to the
assembly code shown below.
constants
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 2[FSR1
;DATA2 IS IN W
7.2 Memory Access Partition (MAP)
User Flash is partitioned into:
Application Block
Boot Block, and
Storage Area Flash (SAF) Block
The user can allocate the memory usage by setting the BBEN bit, selecting the size of the partition
defined by BBSIZE bits and enabling the Storage Area Flash by the SAFEN bit of the Configuration Word.
Refer to the following links for the different user Flash memory partitions.
Related Links
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 47
CONFIG4
7.2.1 Application Block
Default settings of the Configuration bits (BBEN = 1 and SAFEN = 1) assign all memory in the user Flash
area to the Application Block.
7.2.2 Boot Block
If BBEN = 1, the Boot Block is enabled and a specific address range is allotted as the Boot Block based
on the value of the BBSIZE bits and the sizes provided in Configuration Word 4.
Related Links
CONFIG4
7.2.3 Storage Area Flash
Storage Area Flash (SAF) is enabled by clearing the SAFEN bit of the Configuration Word. If enabled, the
SAF block is placed at the end of memory and spans 128 words. If the Storage Area Flash (SAF) is
enabled, the SAF area is not available for program execution.
Related Links
CONFIG4
7.2.4 Memory Write Protection
All the memory blocks have corresponding write protection fuses WRTAPP, WRTB and WRTC bits in the
Configuration Word 4. If write-protected locations are written from NVMCON registers, memory is not
changed and the WRERR bit defined in NVMCON1 register is set as explained in the “WRERR Bit”
section.
Related Links
CONFIG4
NVMCON1
WRERR Bit
7.2.5 Memory Violation
A Memory Execution Violation Reset occurs while executing an instruction that has been fetched from
outside a valid execution area, clearing the MEMV bit. Refer to the “Memory Execution Violation” section
for the available valid program execution areas and the PCON1 register definition for MEMV bit
conditions.
Table 7-2. Memory Access Partition
REG Address
Partition
BBEN = 1
SAFEN = 1
BBEN = 1
SAFEN = 0
BBEN = 0
SAFEN = 1
BBEN = 0
SAFEN = 0
PFM 00 0000h ...
Last Block
APPLICATION
BLOCK(4)
APPLICATION
BLOCK(4) BOOT BLOCK(4) BOOT BLOCK(4)
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 48
REG Address
Partition
BBEN = 1
SAFEN = 1
BBEN = 1
SAFEN = 0
BBEN = 0
SAFEN = 1
BBEN = 0
SAFEN = 0
Memory
Address
Last Boot Block
Memory
Address
+ 1(1) ... Last
Program
Memory
Address - 80h APPLICATION
BLOCK(4)
APPLICATION
BLOCK(4)
Last Program
Memory
Address -
7Fh(2) ... Last
Program
Memory
Address
SAF(4) SAF(4)
CONFIG Config Memory
Address(3) CONFIG
Note: 
1. Last Boot Block Memory Address is based on BBSIZE given in “Configuration Word 4”.
2. Last Program Memory Address is the Flash size given in the “Program Memory Organization”.
3. Config Memory Address are the address locations of the Configuration Words given in the
“NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID,
EEPROM, and Configuration Words” section.
4. Each memory block has a corresponding write protection fuse defined by the WRTAPP, WRTB and
WRTC bits in the “Configuration Word 4”.
Related Links
Memory Execution Violation
PCON1
CONFIG4
Program Memory Organization
NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM,
and Configuration Words
7.3 Data Memory Organization
The data memory is partitioned into 64 memory banks with 128 bytes in each bank. Each bank consists
of:
12 core registers
Up to 100 Special Function Registers (SFR)
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 49
Specwa‘ Function Registers or General Purpose RAM
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
Figure 7-2. Banked Memory Partition
Typical Memory Bank7-bit Bank Offset
00h
0Bh
0Ch
1Fh
20h
6Fh
7Fh
70h
Core Registers
(12 bytes)
Special Function Registers
(up to 20 bytes maximum)
General Purpose RAM
Special Function Registers
or
(80 bytes maximum)
Common RAM
(16 bytes)
Rev. 10-000 041C
11/8/201 7
7.3.1 Bank Selection
The active bank is selected by writing the bank number into the Bank Select Register (BSR). All data
memory can be accessed either directly (via instructions that use the file registers) or indirectly via the
two File Select Registers (FSR). Data memory uses a 13-bit address. The upper six bits of the address
define the Bank address and the lower seven bits select the registers/RAM in that bank.
Related Links
Indirect Addressing
BSR
7.3.2 Core Registers
The core registers contain the registers that directly affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank (addresses n00h/n80h through n0Bh/n8Bh). These
registers are listed below.
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Table 7-3. Core Registers
Addresses in BANKx Core Registers
n00h or n80h INDF0
n01h or n81h INDF1
n02h or n82h PCL
n03 or n83h STATUS
n04h or n84h FSR0L
n05h or n85h FSR0H
n06h or n86h FSR1L
n07h or n87h FSR1H
n08h or n88h BSR
n09h or n89h WREG
n0Ah or n8Ah PCLATH
n0Bh or n8Bh INTCON
7.3.2.1 STATUS Register
The STATUS register contains:
the arithmetic status of the ALU
the Reset status
The STATUS register can be the destination for any instruction, like any other register. If the STATUS
register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three
bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD
bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may
be different than intended.
For example, CLRF STATUS will clear bits <4:3> and <1:0>, and set the Z bit. This leaves the STATUS
register as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not affect any Status bits. For other instructions not
affecting any Status bits, refer to the “Instruction Set Summary” section.
Important:  The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in
subtraction.
Related Links
STATUS
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7.3.3 Special Function Register
The Special Function Registers are registers used by the application to control the desired operation of
peripheral functions in the device. The Special Function Registers occupy the first 20 bytes of the data
banks 0-59 and the first 100 bytes of the data banks 60-63, after the core registers.
The SFRs associated with the operation of the peripherals are described in the appropriate peripheral
chapter of this data sheet.
7.3.4 General Purpose RAM
There are up to 80 bytes of GPR in each data memory bank.
7.3.4.1 Linear Access to GPR
The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify
access to large memory structures.
Related Links
Linear Data Memory
7.3.5 Common RAM
There are 16 bytes of common RAM accessible from all banks.
7.4 PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a
readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes
from PCLATH. On any Reset, the PC is cleared. The following figure shows the five situations for the
loading of the PC.
PIC16(L)F18426/46
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Figure 7-3. Loading of PC in Different Situations
Filename: 10-000042A.vsd
Title: LOADING OF PC IN DIFFERENT SITUATIONS
Last Edit: 7/30/2013
First Used: PIC16F1508/9
Note:
7 8
6
14
0
0
411
0
6 0
14
78
6 0
014
15
014
15
014
PCL
PCL
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PC
PC
PC
PC
PC
PCLATH
PCLATH
PCLATH
Instruction
with PCL as
Destination
GOTO,
CALL
CALLW
BRW
BRA
ALU result
OPCODE <10:0>
W
PC + W
PC + OPCODE <8:0>
Rev. 10-000042A
7/30/2013
7.4.1 Modifying PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the
entire contents of the program counter to be changed by writing the desired upper seven bits to the
PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program
counter will change to the values contained in the PCLATH register and those being written to the PCL
register.
7.4.2 Computed GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When
performing a table read using a computed GOTO method, care should be exercised if the table location
crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing
a Table Read” (DS00556).
7.4.3 Computed Function Calls
A computed function CALL allows programs to maintain tables of functions and provide another way to
execute state machines or look-up tables. When performing a table read using a computed function
CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte
block).
If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
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The CALLW instruction enables computed calls by combining PCLATH and W to form the destination
address. A computed CALLW is accomplished by loading the W register with the desired address and
executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.
7.4.4 Branching
The branching instructions add an offset to the PC. This allows relocatable code and code that crosses
page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either branching instruction, a PCL memory boundary may
be crossed.
If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 + the signed value of the operand of the BRA
instruction.
7.5 Stack
All devices have a 16-level by 15-bit wide hardware stack. The stack space is not part of either program
or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an
interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN configuration bit is programmed to ‘0‘. This means
that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is
enabled.
Important:  There are no instructions/mnemonics called PUSH or POP. These are actions that
occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the
vectoring to an interrupt address.
7.5.1 Accessing the Stack
The stack is accessible through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of
the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/
writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust
the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five
bits to allow detection of overflow and underflow.
Important:  Care should be taken when modifying the STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. STKPTR can be monitored to obtain to value of stack
PIC16(L)F18426/46
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memory left at any given time. The STKPTR always points at the currently used place on the stack.
Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload
the PC value from the stack and then decrement the STKPTR.
Reference the following figures for examples of accessing the stack.
Figure 7-4. Accessing the Stack Example 1
Filename: 10-000043A.vsd
Title: ACCESSING THE STACK EXAMPLE 1
Last Edit: 7/30/2013
First Used: PIC16F1508/9
Note:
STKPTR = 0x1F Stack Reset Disabled
(STVREN = 0)
Stack Reset Enabled
(STVREN = 1)
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’. If the
Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL register will
return the contents of stack address
0x0F.
0x0000 STKPTR = 0x1F
TOSH:TOSL 0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
0x1FTOSH:TOSL
Rev. 10-000043A
7/30/2013
PIC16(L)F18426/46
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Figure 7-5. Accessing the Stack Example 2
Filename: 10-000043B.vsd
Title: ACCESSING THE STACKS EXAMPLE 2
Last Edit: 7/30/2013
First Used: PIC16F1508/9
Note:
STKPTR = 0x00
Return Address
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00TOSH:TOSL
Rev. 10-000043B
7/30/2013
Figure 7-6. Accessing the Stack Example 3
Filename: 10-000043C.vsd
Title: ACCESSING THE STACK EXAMPLE 3
Last Edit: 7/30/2013
First Used: PIC16F1508/9
Note:
STKPTR = 0x06
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
repeatedly place the return addresses into
the Program Counter and pop the stack.
Return Address
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
TOSH:TOSL
Rev. 10-000043C
7/30/2013
PIC16(L)F18426/46
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Figure 7-7. Accessing the Stack Example 4
Filename: 10-000043D.vsd
Title: ACCESSING THE STACK EXAMPLE 4
Last Edit: 7/30/2013
First Used: PIC16F1508/9
Note:
STKPTR = 0x10
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
Return Address0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return AddressTOSH:TOSL
Rev. 10-000043D
7/30/2013
Related Links
TOS
7.5.2 Overflow/Underflow Reset
If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be Reset if the stack is
PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON register.
Related Links
CONFIG2
7.6 Indirect Addressing
The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually
accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status
bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These
locations are divided into three memory regions:
Traditional/Banked Data Memory
Linear Data Memory
Program Flash Memory
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Figure 7-8. Indirect Addressing PIC16(L)F18426/46
Filename: 10-000044F.vsd
Title: INDIRECT ADDRESSING
Last Edit: 1/13/2017
First Used: PIC16(L)F153XX
Note:
0x0000
PC value = 0x000
PC value = 0x7FF0x87FF
0x0000
0x1FFF
0x2000
0X2FEF
0X2FF0
0x7FFF
0x8000
Reserved
Traditional
Data Memory
Linear
Data Memory
Program
Flash Memory
FSR
Address
Range
Rev. 10-000044F
1/13/2017
Related Links
FSR0
7.6.1 Traditional/Banked Data Memory
The traditional or banked data memory is a region from FSR address 0x000 to FSR address 0x1FFF. The
addresses correspond to the absolute addresses of all SFR, GPR and common registers.
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1 1 Bank éewea‘
Figure 7-9. Traditional/Banked Data Memory Map
Direct Addressing
5 0
BSR 6 0
From Opcode
0
07 FSRxH
0 0
07 FSRxL
Indirect Addressing
000000 000001 000010 111111
Bank Select Location Select
0x00
0x7F
Bank Select Location Select
Bank 0 Bank 1 Bank 2 Bank 63
Rev. 10-000056B
12/14/2016
Filename: 10-000056B.vsd
Title: TRADITIONAL DATA MEMORY MAP
Last Edit: 12/14/2016
First Used: PIC16F153xx
Note:
7.6.2 Linear Data Memory
The linear data memory is the region from FSR address 0x2000 to FSR address 0X2FEF. This region is a
virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Refer to the
following figure for the Linear Data Memory Map.
Important:  The address range 0x2000 to 0x2FF0 represents the complete addressable Linear
Data Memory up to Bank 50. The actual implemented Linear Data Memory will differ from one
device to the other in a family. Confirm the memory limits on every device.
Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the
next bank.
The 16 bytes of common memory are not included in the linear data memory region.
PIC16(L)F18426/46
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Figure 7-10. Linear Data Memory Map
Filename: 10-000057B.vsd
Title: LINEAR DATA MEMORY MAP
Last Edit: 8/24/2016
First Used: PIC16F153xx
Note:
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Bank 2
0x16F
0x1920
Bank 50
0x196F
0 07 7FSRnH FSRnL
Location Select 0x2000
0x2FEF
Rev. 10-000057B
8/24/2016
7.6.3 Program Flash Memory
To make constant data access easier, the entire Program Flash Memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the lower eight bits of each memory location are
accessible via INDF. Writing to the Program Flash Memory cannot be accomplished via the FSR/INDF
interface. All instructions that access Program Flash Memory via the FSR/INDF interface will require one
additional instruction cycle to complete.
Figure 7-11. Program Flash Memory Map
Filename: 10-000058A.vsd
Title: PROGRAM FLASH MEMORY MAP
Last Edit: 7/31/2013
First Used: PIC16F1508/9
Note:
0x0000
Program
Flash
Memory
(low 8 bits)
0x7FFF
1
0 07 7FSRnH FSRnL
Location Select 0x8000
0xFFFF
Rev. 10-000058A
7/31/2013
7.7 Register Summary - Memory and Status
Offset Name Bit Pos.
0x00 INDF0 7:0 INDF[7:0]
0x01 INDF1 7:0 INDF[7:0]
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Offset Name Bit Pos.
0x02 PCL 7:0 PCL[7:0]
0x03 STATUS 7:0 TO PD Z DC C
0x04 FSR0 7:0 FSRL[7:0]
0x05 15:8 FSRH[7:0]
0x06 FSR1 7:0 FSRL[7:0]
0x07 15:8 FSRH[7:0]
0x08 BSR 7:0 BSR[5:0]
0x09 WREG 7:0 WREG[7:0]
0x0A PCLATH 7:0 PCLATH[6:0]
0x0B INTCON 7:0 GIE PEIE INTEDG
0x0C
...
0x0FEC
Reserved
0x0FED STKPTR 7:0 STKPTR[4:0]
0x0FEE TOS 7:0 TOSL[7:0]
0x0FEF 15:8 TOSH[7:0]
7.8 Register Definitions: Memory and Status
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7.8.1 INDF0
Name:  INDF0
Address:  0x00 + n*0x80 [n=0..63]
Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSR0 register is
the target for all operations involving the INDF0 register.
Bit 7 6 5 4 3 2 1 0
INDF0[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – INDF0[7:0]
Indirect data pointed to by the FSR0 register
Related Links
Core Registers
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7.8.2 INDF1
Name:  INDF1
Address:  0x01 + n*0x80 [n=0..63]
Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSR1 register is
the target for all operations involving the INDF1 register.
Bit 7 6 5 4 3 2 1 0
INDF1[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – INDF1[7:0]
Indirect data pointed to by the FSR1 register
Related Links
Core Registers
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7.8.3 PCL
Name:  PCL
Address:  0x02 + n*0x80 [n=0..63]
Low byte of the Program Counter
Bit 7 6 5 4 3 2 1 0
PCL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – PCL[7:0]
Provides direct read and write access to the Program Counter
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7.8.4 STATUS
Name:  STATUS
Address:  0x03 + n*0x80 [n=0..63]
Status Register
Bit 7 6 5 4 3 2 1 0
TO PD Z DC C
Access RO RO R/W R/W R/W
Reset 1 1 0 0 0
Bit 4 – TO Time-Out bit
Reset States: POR/BOR = 1
All Other Resets = q
Value Description
1 Set at power-up or by execution of CLRWDT or SLEEP instruction
0 A WDT time-out occurred
Bit 3 – PD Power-Down bit
Reset States: POR/BOR = 1
All Other Resets = q
Value Description
1 Set at power-up or by execution of CLRWDT instruction
0 Cleared by execution of the SLEEP instruction
Bit 2 – Z Zero bit
Reset States: POR/BOR = 0
All Other Resets = u
Value Description
1 The result of an arithmetic or logic operation is zero
0 The result of an arithmetic or logic operation is not zero
Bit 1 – DC  Digit Carry/Borrow bit(1)
ADDWF, ADDLW, SUBLW, SUBWF instructions
Reset States: POR/BOR = 0
All Other Resets = u
Value Description
1 A carry-out from the 4th low-order bit of the result occurred
0 No carry-out from the 4th low-order bit of the result
Bit 0 – C  Carry/Borrow bit(1)
ADDWF, ADDLW, SUBLW, SUBWF instructions
Reset States: POR/BOR = 0
All Other Resets = u
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Value Description
1 A carry-out from the Most Significant bit of the result occurred
0 No carry-out from the Most Significant bit of the result occurred
Note: 
1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or
low-order bit of the Source register.
Related Links
Core Registers
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7.8.5 FSR0
Name:  FSR0
Address:  0x04 + n*0x80 [n=0..63]
Indirect Address Register. The FSR value is the address of the data to which the INDF register points.
Bit 15 14 13 12 11 10 9 8
FSRH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FSRL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:8 – FSRH[7:0]
Most significant address of INDF data
Bits 7:0 – FSRL[7:0]
Least significant address of INDF data
Related Links
Core Registers
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7.8.6 FSR1
Name:  FSR1
Address:  0x06 + n*0x80 [n=0..63]
Indirect Address Register. The FSR value is the address of the data to which the INDF register points.
Bit 15 14 13 12 11 10 9 8
FSRH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FSRL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:8 – FSRH[7:0]
Most significant address of INDF data
Bits 7:0 – FSRL[7:0]
Least significant address of INDF data
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7.8.7 BSR
Name:  BSR
Address:  0x08 + n*0x80 [n=0..63]
Bank Select Register
The BSR indicates the data memory bank by writing the bank number into the register. All data memory
can be accessed directly via instructions, or indirectly via FSRs.
Bit 7 6 5 4 3 2 1 0
BSR[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 5:0 – BSR[5:0]
Six most significant bits of the data memory address
Related Links
Core Registers
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7.8.8 WREG
Name:  WREG
Address:  0x09 + n*0x80 [n=0..63]
Working Data Register
Bit 7 6 5 4 3 2 1 0
WREG[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – WREG[7:0]
Related Links
Core Registers
PIC16(L)F18426/46
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7.8.9 PCLATH
Name:  PCLATH
Address:  0x0A + n*0x80 [n=0..63]
Program Counter Latches.
Write Buffer for the upper 7 bits of the Program Counter
Bit 7 6 5 4 3 2 1 0
PCLATH[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 6:0 – PCLATH[6:0] High PC Latch register
Holding register for Program Counter bits <6:0>
Related Links
Core Registers
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7.8.10 INTCON
Name:  INTCON
Address:  0x0B + n*0x80 [n=0..63]
Interrupt Control Register
Bit 7 6 5 4 3 2 1 0
GIE PEIE INTEDG
Access R/W R/W R/W
Reset 0 0 1
Bit 7 – GIE Global Interrupt Enable bit
Value Description
1 Enables all active interrupts
0 Disables all interrupts
Bit 6 – PEIE Peripheral Interrupt Enable bit
Value Description
1 Enables all active peripheral interrupts
0 Disables all peripheral interrupts
Bit 0 – INTEDG External Interrupt Edge Select bit
Value Description
1 Interrupt on rising edge of INT pin
0 Interrupt on falling edge of INT pin
Important:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt
flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
Related Links
Core Registers
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 72
7.8.11 TOS
Name:  TOS
Address:  0xFEE
Top Of Stack Registers.
Contents of the stack pointed to by the STKPTR register. To access the stack, adjust the value of
STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL.
Bit 15 14 13 12 11 10 9 8
TOSH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TOSL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:8 – TOSH[7:0] High Byte of the TOS Register
Bits <15:8> of the TOS
Bits 7:0 – TOSL[7:0] Low Byte TOS Register
Bits <7:0> of the TOS
Related Links
Core Registers
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 73
7.8.12 STKPTR
Name:  STKPTR
Address:  0xFED
Stack Pointer Register
Bit 7 6 5 4 3 2 1 0
STKPTR[4:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 4:0 – STKPTR[4:0] Stack Pointer Location bits
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 74
7.9 Register Summary: Shadow Registers
Offset Name Bit Pos.
0x1FE4 STATUS_SHAD 7:0 TO PD Z DC C
0x1FE5 WREG_SHAD 7:0 WREG[7:0]
0x1FE6 BSR_SHAD 7:0 BSR[5:0]
0x1FE7 PCLATH_SHAD 7:0 PCLATH[6:0]
0x1FE8 FSR0_SHAD 7:0 FSRL[7:0]
15:8 FSRH[7:0]
0x1FEA FSR1_SHAD 7:0 FSRL[7:0]
15:8 FSRH[7:0]
7.10 Register Definitions: Shadow Registers
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 75
7.10.1 STATUS_SHAD
Name:  STATUS_SHAD
Address:  0x1FE4
Shaodow of Status Register
Bit 7 6 5 4 3 2 1 0
TO PD Z DC C
Access RO RO R/W R/W R/W
Reset x x x x x
Bit 4 – TO Time-Out bit
Reset States: POR/BOR = x
All Other Resets = u
Value Description
1 Set at power-up or by execution of CLRWDT or SLEEP instruction
0 A WDT time-out occurred
Bit 3 – PD Power-Down bit
Reset States: POR/BOR = x
All Other Resets = u
Value Description
1 Set at power-up or by execution of CLRWDT instruction
0 Cleared by execution of the SLEEP instruction
Bit 2 – Z Zero bit
Reset States: POR/BOR = x
All Other Resets = u
Value Description
1 The result of an arithmetic or logic operation is zero
0 The result of an arithmetic or logic operation is not zero
Bit 1 – DC  Digit Carry/Borrow bit(1)
ADDWF, ADDLW, SUBLW, SUBWF instructions
Reset States: POR/BOR = x
All Other Resets = u
Value Description
1 A carry-out from the 4th low-order bit of the result occurred
0 No carry-out from the 4th low-order bit of the result
Bit 0 – C  Carry/Borrow bit(1)
ADDWF, ADDLW, SUBLW, SUBWF instructions
Reset States: POR/BOR = x
All Other Resets = u
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Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 76
Value Description
1 A carry-out from the Most Significant bit of the result occurred
0 No carry-out from the Most Significant bit of the result occurred
Note: 
1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or
low-order bit of the Source register.
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 77
7.10.2 WREG_SHAD
Name:  WREG_SHAD
Address:  0x1FE5
Shadow of Working Data Register
Bit 7 6 5 4 3 2 1 0
WREG[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Bits 7:0 – WREG[7:0]
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 78
7.10.3 BSR_SHAD
Name:  BSR_SHAD
Address:  0x1FE6
Shadow of Bank Select Register
The BSR indicates the data memory bank by writing the bank number into the register. All data memory
can be accessed directly via instructions, or indirectly via FSRs.
Bit 7 6 5 4 3 2 1 0
BSR[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
Bits 5:0 – BSR[5:0]
Six Most Significant bits of the data memory address
Reset States: POR/BOR = xxxxxx
All Other Resets = uuuuuu
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 79
7.10.4 PCLATH_SHAD
Name:  PCLATH_SHAD
Address:  0x1FE7
Shadow of Program Counter Latches.
Write Buffer for the upper 7 bits of the Program Counter
Bit 7 6 5 4 3 2 1 0
PCLATH[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x
Bits 6:0 – PCLATH[6:0] High PC Latch register
Holding register for Program Counter bits <6:0>
Reset States: POR/BOR = xxxxxxx
All Other Resets = uuuuuuu
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 80
7.10.5 FSR_SHAD
Name:  FSRx_SHAD
Address:  0x1FE8,0x1FEA
Shadow of Indirect Address Register. The FSR value is the address of the data to which the INDF
register points.
Bit 15 14 13 12 11 10 9 8
FSRH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Bit 7 6 5 4 3 2 1 0
FSRL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Bits 15:8 – FSRH[7:0]
Most Significant address of INDF data
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Bits 7:0 – FSRL[7:0]
Least Significant address of INDF data
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
PIC16(L)F18426/46
Memory Organization
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 81
v /MCLR
8. Resets
There are multiple ways to reset this device:
Power-on Reset (POR)
Brown-out Reset (BOR)
Low-Power Brown-Out Reset (LPBOR)
MCLR Reset
WDT Reset
RESET instruction
Stack Overflow
Stack Underflow
Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a
BOR or POR event.
A simplified block diagram of the On-Chip Reset Circuit is shown in the block diagram below.
Figure 8-1. Simplified Block Diagram of On-Chip Reset Circuit
Device
Reset
Power-on
Reset
WWDT Time-out/
Window violation
Brown-out
Reset
LPBOR
Reset
RESET Instruction
MCLRE
PWRTS<1:0>
LFINTOSC
VDD
ICSP™ Programming Mode Exit
Stack Underflow
Stack Overflow
Power-up
Timer
Rev. 10-000006G
4/6/2017
VPP/MCLR
Memory Violation
2
Note:  See “BOR Operating Conditions” table for BOR active conditions.
Related Links
BOR Controlled by Software
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 82
8.1 Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum
operation. Slow rising VDD, fast operating speeds or analog performance may require greater than
minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all
device operation conditions have been met.
Related Links
BOR Controlled by Software
8.2 Brown-out Reset (BOR)
The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for execution protection can be implemented.
The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in
Configuration Words. The four operating modes are:
BOR is always on
BOR is off when in Sleep
BOR is controlled by software
BOR is always off
Refer to “BOR Operating Conditions” table for more information.
The Brown-out Reset voltage level is selectable by configuring the BORV<1:0> bits in Configuration
Words.
A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device will reset.
8.2.1 BOR is Always On
When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.
8.2.2 BOR is OFF in Sleep
When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.
8.2.3 BOR Controlled by Software
When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the
SBOREN bit. The device start-up is not delayed by the BOR ready condition or the VDD level.
BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in
the BORRDY bit.
BOR protection is unchanged by Sleep.
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 83
eeeee
Table 8-1. BOR Operating Conditions
BOREN<1:0> SBOREN Device
Mode BOR Mode Instruction Execution upon: Release of POR
or Wake-up from Sleep
11 X X Active Waits for release of BOR(1) (BORRDY = 1)
10 X Awake Active Waits for release of BOR (BORRDY = 1) Waits
for BOR Reset release
Sleep Disabled
01 1 X Active Waits for BOR Reset release (BORRDY = 1)
0 X Disabled Begins immediately (BORRDY = x)
00 X X Disabled
Note: 
1. In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The
BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions
because the BOR circuit is forced on by the BOREN<1:0> bits
Figure 8-2. Brown-out Situations
TPWRT(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset TPWRT(1)
< TPWRT
TPWRT(1)
VBOR
VDD
Internal
Reset
Rev. 30-000092A
4/12/2017
Note:  TPWRT delay only if PWRTS bit field is programmed to a value different from ‘11’.
8.2.4 BOR is Always Off
When the BOREN bits of the Configuration Words are programmed to ‘00’, the BOR is off at all times.
The device start-up is not delayed by the BOR ready condition or the VDD level.
8.3 Low-Power Brown-out Reset (LPBOR)
The Low-Power Brown-out Reset (LPBOR) provides an additional BOR circuit for low power operation.
Refer to the figure below to see how the BOR interacts with other modules.
The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is
held in Reset.
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 84
Any Rese‘ REARM F'OR Evem PDR PDR Even
Figure 8-3. LPBOR, BOR, POR Relationship
Reset
POR
logic
LPBOR
To PCON
indicator bit
BOR
BOR Event
REARM POR
Event
POR Event LPBOR Event
Any Reset
Rev. 30-000091B
6/21/2017
8.3.1 Enabling LPBOR
The LPBOR is controlled by the LPBOREN bit of Configuration Word 2. When the device is erased, the
LPBOR module defaults to disabled.
Related Links
CONFIG2
8.3.2 LPBOR Module Output
The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This
signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal,
which goes to the PCON0 register and to the power control block.
8.4 MCLR
The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of Configuration Words (see table below). The
RMCLR bit in the PCON0 register will be set to ‘0’ if a MCLR has occurred.
Table 8-2. MCLR Configuration
MCLRE LVP MCLR
x 1 Enabled
1 0 Enabled
0 0 Disabled
8.4.1 MCLR Enabled
When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected
to VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 85
Important:  An internal Reset event (RESET instruction, BOR, WWDT, POR, STKOVF,
STKUNF) does not drive the MCLR pin low.
Related Links
Master Clear (MCLR) Pin
8.4.2 MCLR Disabled
When MCLR is disabled, the MCLR becomes input-only and pin functions such as internal weak pull-ups
are under software control.
Related Links
I/O Priorities
8.5 Windowed Watchdog Timer (WWDT) Reset
The Windowed Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction
within the time-out period or window set. The TO and PD bits in the STATUS register and the RWDT bit
are changed to indicate a WDT Reset. The WDTWV bit indicates if the WDT Reset has occurred due to a
timeout or a window violation.
Related Links
STATUS
(WWDT) Windowed Watchdog Timer
8.6 RESET Instruction
A RESET instruction will cause a device Reset. The RI bit will be set to ‘0’. See “Reset Condition for
Special Registers” table for default conditions after a RESET instruction has occurred.
8.7 Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits register
indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration
Words.
Related Links
CONFIG2
Overflow/Underflow Reset
8.8 Programming Mode Exit
Upon exit of Programming mode, the device will behave as if a POR had just occurred.
8.9 Power-up Timer (PWRT)
The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically
used to allow VDD to stabilize before allowing the device to start running.
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Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 86
The Power-up Timer is controlled by the PWRTS bit field of the Configuration Words.
The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the
VDD to rise to an acceptable level. The Power-up Timer is enabled by setting a non-zero value in the
PWRTS bit field, in Configuration Words.
The Power-up Timer starts after the release of the POR and BOR.
For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00000607).
8.10 Start-up Sequence
Upon the release of a POR or BOR, the following must occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. Oscillator start-up timer runs to completion (if required for selected oscillator source).
3. MCLR must be released (if enabled).
The total time out will vary based on oscillator configuration and Power-up Timer configuration.
The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator Start-up Timer will expire. Upon bringing MCLR high, the
device will begin execution after 10 FOSC cycles (see figure below). This is useful for testing purposes or
to synchronize more than one device operating in parallel.
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 87
Figure 8-4. Reset Start-up Sequence
TOST
TMCLR
TPWRT
VDD
Internal POR
Power-up Timer
MCLR
Internal RESET
Oscillator Modes
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
External Crystal
Rev. 30-000093A
4/12/2017
Related Links
Oscillator Module (with Fail-Safe Clock Monitor)
8.11 Memory Execution Violation
A Memory Execution Violation Reset occurs if executing an instruction being fetched from outside the
valid execution area. The different valid execution areas are defined as follows:
Flash Memory: The “Device Sizes and Addresses” table shows the addresses available on the
PIC16(L)F18426/46 devices based on user Flash size. Execution outside this region generates a
memory execution violation.
Storage Area Flash (SAF): If Storage Area Flash (SAF) is enabled , the SAF area is not a valid
execution area.
Prefetched instructions that are not executed do not cause memory execution violations. For example, a
GOTO instruction in the last memory location will prefetch from an invalid location; this is not an error. If an
instruction from an invalid location tries to execute, the memory violation is generated immediately, and
any concurrent interrupt requests are ignored. When a memory execution violation is generated, the
device is reset and flag MEMV is cleared in PCON1 to signal the cause. The flag needs to be set in code
after a memory execution violation.
Related Links
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 88
Program Memory Organization
Storage Area Flash
Memory Violation
8.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of
the Reset. The following tables show the Reset conditions of these registers.
Table 8-3. Reset Status Bits and Their Significance
STOVF STKUNF RWDT RMCLR RI POR BOR TO PD MEMV Condition
0 0 1 1 1 0 x 1 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x u Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 u Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 u Brown-out Reset
u u 0 u u u u 0 u u WWDT Reset
u u u u u u u 0 0 u WWDT Wake-up from Sleep
u u u u u u u 1 0 u Interrupt Wake-up from Sleep
u u u 0 u u u u u 1 MCLR Reset during normal
operation
u u u 0 u u u 1 0 u MCLR Reset during Sleep
u u u u 0 u u u u u RESET Instruction Executed
1 u u u u u u u u u Stack Overflow Reset (STVREN
= 1)
u 1 u u u u u u u u Stack Underflow Reset
(STVREN = 1)
u u u u u u u u u 0 Memory violation Reset
Table 8-4. Reset Condition for Special Registers
Condition Program
Counter
STATUS
Register
PCON0
Register
PCON1
Register
Power-on Reset 0 ---1 1000 0011 110x ---- --1-
Brown-out Reset 0 ---1 1000 0011 11u0 ---- --u-
MCLR Reset during normal operation 0 -uuu uuuu uuuu 0uuu ---- --1-
MCLR Reset during Sleep 0 ---1 0uuu uuuu 0uuu ---- --u-
WWDT Time-out Reset 0 ---0 uuuu uuu0 uuuu ---- --u-
WWDT Wake-up from Sleep PC + 1 ---0 0uuu uuuu uuuu ---- --u-
WWDT Window Violation Reset 0 ---u uuuu uu0u uuuu ---- --u-
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Condition Program
Counter
STATUS
Register
PCON0
Register
PCON1
Register
Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uuuu uuuu ---- --u-
RESET Instruction Executed 0 ---u uuuu uuuu u0uu ---- --u-
Stack Overflow Reset (STVREN = 1) 0 ---u uuuu 1uuu uuuu ---- --u-
Stack Underflow Reset (STVREN = 1) 0 ---u uuuu u1uu uuuu ---- --u-
Memory Violation Reset (MEMV = 0) 0 -uuu uuuu uuuu uuuu ---- --0-
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.
Note: 
1. When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is
pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
Related Links
STATUS
8.13 Power Control (PCONx) Register
The Power Control (PCONx) registers contain flag bits to differentiate between a:
Brown-out Reset (BOR)
Power-on Reset (POR)
Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Watchdog Window Violation (WDTWV)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
Memory Violation Reset (MEMV)
Hardware will change the corresponding register bit during the Reset process; if the Reset was not
caused by the condition, the bit remains unchanged.
Software should reset the bit to the inactive state after restart (hardware will not reset the bit).
Software may also set any PCONx bit to the active state, so that user code may be tested, but no Reset
action will be generated.
Related Links
Determining the Cause of a Reset
PCON0
PCON1
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Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 90
8.14 Register Summary - BOR Control and Power Control
Offset Name Bit Pos.
0x0811 BORCON 7:0 SBOREN BORRDY
0x0812 Reserved
0x0813 PCON0 7:0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR
0x0814 PCON1 7:0 MEMV
8.15 Register Definitions: Power Control
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Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 91
8.15.1 BORCON
Name:  BORCON
Address:  0x811
Brown-out Reset Control Register
Bit 7 6 5 4 3 2 1 0
SBOREN BORRDY
Access R/W R
Reset 1 q
Bit 7 – SBOREN Software Brown-out Reset Enable bit
Reset States: POR/BOR = 1
All Other Resets = u
Value Condition Description
If BOREN≠01 SBOREN is read/write, but has no effect on the BOR.
1 If BOREN=01 BOR Enabled
0 If BOREN=01 BOR Disabled
Bit 0 – BORRDY Brown-out Reset Circuit Ready Status bit
Reset States: POR/BOR = q
All Other Resets = u
Value Description
1 The Brown-out Reset Circuit is active and armed
0 The Brown-out Reset Circuit is disabled or is warming up
Related Links
CONFIG2
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 92
8.15.2 PCON0
Name:  PCON0
Address:  0x813
Power Control Register 0
Bit 7 6 5 4 3 2 1 0
STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR
Access R/W/HS R/W/HS R/W/HC R/W/HC R/W/HC R/W/HC R/W/HC R/W/HC
Reset 0 0 1 1 1 1 0 q
Bit 7 – STKOVF Stack Overflow Flag bit
Reset States: POR/BOR = 0
All Other Resets = q
Value Description
1 A Stack Overflow occurred (more CALLs than fit on the stack)
0 A Stack Overflow has not occurred or set to ‘0’ by firmware
Bit 6 – STKUNF Stack Underflow Flag bit
Reset States: POR/BOR = 0
All Other Resets = q
Value Description
1 A Stack Underflow occurred (more RETURNs than CALLs)
0 A Stack Underflow has not occurred or set to ‘0’ by firmware
Bit 5 – WDTWV Watchdog Window Violation Flag bit
Reset States: POR/BOR = 1
All Other Resets = q
Value Description
1 A WDT window violation has not occurred or set to ‘1’ by firmware
0 A CLRWDT instruction was issued when the WDT Reset window was closed (set to ‘0’ in
hardware when a WDT window violation Reset occurs)
Bit 4 – RWDT WDT Reset Flag bit
Reset States: POR/BOR = 1
All Other Resets = q
Value Description
1 A WDT overflow/time-out Reset has not occurred or set to ‘1’ by firmware
0 A WDT overflow/time-out Reset has occurred (set to ‘0’ in hardware when a WDT Reset
occurs)
Bit 3 – RMCLR  MCLR Reset Flag bit
Reset States: POR/BOR = 1
All Other Resets = q
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 93
Value Description
1 A MCLR Reset has not occurred or set to ‘1’ by firmware
0 A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
Bit 2 – RI  RESET Instruction Flag bit
Reset States: POR/BOR = 1
All Other Resets = q
Value Description
1 A RESET instruction has not been executed or set to ‘1’ by firmware
0 A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET
instruction)
Bit 1 – POR Power-on Reset Status bit
Reset States: POR/BOR = 0
All Other Resets = u
Value Description
1 No Power-on Reset occurred or set to ‘1’ by firmware
0 A Power-on Reset occurred (set to ‘0’ in hardware when a Power-on Reset occurs)
Bit 0 – BOR Brown-out Reset Status bit
Reset States: POR/BOR = q
All Other Resets = u
Value Description
1 No Brown-out Reset occurred or set to ‘1’ by firmware
0 A Brown-out Reset occurred (set to ‘0’ in hardware when a Brown-out Reset occurs)
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 94
8.15.3 PCON1
Name:  PCON1
Address:  0x814
Power Control Register 1
Bit 7 6 5 4 3 2 1 0
MEMV
Access R/W/HC
Reset 1
Bit 1 – MEMV Memory Violation Flag bit
Reset States: POR/BOR = 1
All Other Resets = u
Value Description
1 No Memory Violation Reset occurred or set to ‘1’ by firmware.
0 A Memory Violation Reset occurred (set to ‘0’ in hardware when a Memory Violation occurs)
PIC16(L)F18426/46
Resets
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 95
9. Oscillator Module (with Fail-Safe Clock Monitor)
9.1 Overview
The oscillator module has multiple clock sources and selection features that allow it to be used in a wide
range of applications while maximizing performance and minimizing power consumption. The following
figure illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic
resonators. In addition, the system clock source can be supplied from one of two internal oscillators and
PLL circuits, with a choice of speeds selectable via software. Additional clock features include:
Selectable system clock source between external or internal sources via software.
Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT,
HS, ECH, ECM, ECL) and switch automatically to the internal oscillator.
Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources.
The RSTOSC bits of Configuration Word 1 determine the type of oscillator that will be used when the
device runs after Reset, including when it is first powered up.
The internal clock modes, LFINTOSC, HFINTOSC (set at 1 MHz), or HFINTOSC (set at 32 MHz) can be
set through the RSTOSC bits.
If an external clock source is selected, the FEXTOSC bits of Configuration Word 1 must be used in
conjunction with the RSTOSC bits to select the External Clock mode.
The external oscillator module can be configured in one of the following clock modes, by setting the
FEXTOSC bits of Configuration Word 1:
1. ECL – External Clock Low-Power mode
(≤ 500 kHz)
2. ECM – External Clock Medium Power mode
(≤ 8 MHz)
3. ECH – External Clock High-Power mode
(≤ 32 MHz)
4. LP – 32 kHz Low-Power Crystal mode.
5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (between 100 kHz and 4 MHz)
6. HS – High Gain Crystal or Ceramic Resonator mode (above 4 MHz)
The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source.
The LP, XT, and HS Clock modes require an external crystal or resonator to be connected to the device.
Each mode is optimized for a different frequency range. The internal oscillator block produces low and
high-frequency clock sources, designated LFINTOSC and HFINTOSC. Multiple device clock frequencies
may be derived from these clock sources.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 96
Figure 9-1. Simplified PIC® MCU Clock Source Block Diagram
PLL Block
Filename: 10-000208G.vsd
Title: Simplified Clock Source Block Diagram
Last Edit: 8/15/2016
First Used: PIC16(L)F15354/55
Notes:
Rev. 10-000208M
5/17/2017
HFFRQ<2:0>
HFINTOSC
Secondary
Oscillator
(SOSC)
External
Oscillator
(EXTOSC)
CLKIN/ OSC1
CLKOUT/ OSC2
SOSCIN/SOSCI
SOSCO
31kHz
Oscillator
4x PLL Mode
011
101
110
000
100
010
001
111
COSC<2:0>
LFINTOSC
1 – 32 MHz
Oscillator
9-bit Postscaler Divider
1000
1001
0000
0011
0010
0001
0100
0101
0110
0111
512
256
128
64
32
16
8
4
2
1
CDIV<3:0>
Sleep
Idle
Sleep
SYSCMD
System Clock
Peripheral Clock
FSCM
To Peripherals
To Peripherals
To Peripherals
2x PLL Mode
Related Links
CONFIG1
9.2 Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator
modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS
modes).
There is also a secondary oscillator block which is optimized for a 32.768 kHz external clock source,
which can be used as an alternate clock source.
There are two internal oscillator blocks:
• HFINTOSC
• LFINTOSC
The HFINTOSC can produce clock frequencies from 1-32 MHz, and is responsible for generating the two
MFINTOSC frequencies (500 kHz and 32 kHz) that can be used by some peripherals. The LFINTOSC
generates a 31 kHz clock frequency.
There is a 4x PLL that can be used by the external oscillator. Additionally, there is a PLL that can be used
by the HFINTOSC at certain frequencies.
Related Links
4x PLL
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 97
2x PLL
9.2.1 External Clock Sources
An external clock source can be used as the device system clock by performing one of the following
actions:
Program the RSTOSC bits in the Configuration Words to select an external clock source that will be
used as the default system clock upon a device Reset.
Write the NOSC and NDIV bits to switch the system clock source.
Related Links
Clock Switching
9.2.1.1 EC Mode
The External Clock (EC) mode allows an externally generated logic level signal to be the system clock
source. When operating in this mode, an external clock source is connected to the CLKIN/OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The following figure shows the pin
connections for EC mode.
EC mode has three power modes to select from through Configuration Words:
ECH – High power, ≤ 32 MHz
ECM – Medium power, ≤ 8 MHz
ECL – Low power, ≤ 0.1 MHz
The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay
in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the effect of halting the device while leaving all data
intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
Figure 9-2. External Clock (EC) Mode Operation
OSC1/CLKIN
OSC2/CLKOUT
Clock from
Ext. System
PIC®MCU
FOSC/4 or I/O(1)
Rev. 30-000060A
4/6/2017
Note: 
1. Output depends upon CLKOUTEN bit of the Configuration Words (CONFIG1H).
9.2.1.2 LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected
to OSC1 and OSC2 (Figure 9-3). The three modes select a low, medium or high gain setting of the
internal inverter-amplifier to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current
consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork
type crystals (watch crystals). but can operate up to 100 kHz.
XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current
consumption is the medium of the three modes. This mode is best suited to drive crystals and resonators
with a frequency range up to 4 MHz.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 98
HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current
consumption is the highest of the three modes. This mode is best suited for resonators that require
operating frequencies up to 20 MHz.
Figure 9-3 and Figure 9-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
Figure 9-3. Quartz Crystal Operation (LP, XT or HS Mode)
Filename: 10-000059A.vsd
Title: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
Last Edit: 7/30/2013
First Used: PIC16F1508/9
Note:
RS(1)
OSC1/CLKIN
PIC®MCU
OSC2/CLKOUT
Note 1: A series resistor (Rs) may be required for
quartz crystals with low drive level.
2: The value of RFvaries with the Oscillator mode
selected (typically between 2 MΩ and 10 MΩ).
RF(2)
C2
C1 To Internal
Logic
Sleep
Quartz
Crystal
Rev. 10-000059A
7/30/2013
Note: 
1. A series resistor (RS) may be required for quartz crystals with low drive level.
2. The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ).
Figure 9-4. Ceramic Resonator Operation
(XT or HS Mode)
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC®MCU
RP(3)
Resonator
OSC2/CLKOUT
Rev. 30-000062A
4/6/2017
Note: 
1. A series resistor (RS) may be required for ceramic resonators with low drive level.
2. The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ).
3. An additional parallel feedback resistor (RP) may be required for proper ceramic resonator
operation.
9.2.1.3 Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a Power-on Reset (POR), or a wake-up from Sleep.
The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has
started and is providing a stable system clock to the oscillator module.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 99
sssss
9.2.1.4 4x PLL
The oscillator module contains a 4x PLL that can be used with the external clock sources to provide a
system clock source. The input frequency for the PLL must fall within specifications.
The PLL can be enabled for use by one of two methods:
1. Program the RSTOSC bits in the Configuration Word 1 to ‘010’ (enable EXTOSC with 4x PLL).
2. Write the NOSC bits to ‘010’ (enable EXTOSC with 4x PLL).
Related Links
OSCCON1
PLL Specifications
9.2.1.5 Secondary Oscillator
The secondary oscillator is a separate oscillator block that can be used as an alternate system clock
source. The secondary oscillator is optimized for 32.768 kHz, and can be used with an external crystal
oscillator connected to the SOSCI and SOSCO device pins, or an external clock source connected to the
SOSCIN pin. The secondary oscillator can be selected during run-time using clock switching.
Figure 9-5. Quartz Crystal Operation (Secondary Oscillator)
C1
C2
32.768 kHz
SOSCI
To Internal
Logic
PIC®MCU
Crystal
SOSCO
Quartz
Rev. 30-000063A
4/6/2017
Note: 
1. Quartz crystal characteristics vary according to type, package and manufacturer. The user should
consult the manufacturer data sheets for specifications and recommended application.
2. Always verify oscillator performance over the VDD and temperature range that is expected for the
application.
3. For oscillator design assistance, reference the following Microchip Application Notes:
AN826, “Crystal Oscillator Basics and Crystal Selection for PIC® and PIC® Devices”
(DS00826)
AN849, “Basic PIC® Oscillator Design” (DS00849)
AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943)
AN949, “Making Your Oscillator Work” (DS00949)
TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a
PIC16F690/SS” (DS91097)
AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)
Related Links
Clock Switching
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 100
9.2.2 Internal Clock Sources
The device may be configured to use the internal oscillator block as the system clock by performing one
of the following actions:
Program the RSTOSC bits in Configuration Words to select the INTOSC clock source, which will be
used as the default system clock upon a device Reset.
Write the NOSC bits to switch the system clock source to the internal oscillator during run-time.
In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for
general purpose I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words.
The internal oscillator block has two independent oscillators that can produce two internal system clock
sources.
1. The HFINTOSC (High-Frequency Internal Oscillator) is factory-calibrated and operates up to 32
MHz. The frequency of HFINTOSC can be selected through the OSCFRQ Frequency Selection
register, and fine-tuning can be done via the OSCTUNE register.
2. The LFINTOSC (Low-Frequency Internal Oscillator) is factory-calibrated and operates at 31 kHz.
Related Links
Clock Switching
9.2.2.1 HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is a precision digitally-controlled internal clock
source that produces a stable clock up to 32 MHz. The HFINTOSC can be enabled through one of the
following methods:
Programming the RSTOSC bits in Configuration Word 1 to ‘110’ (FOSC = 1 MHz) or ‘000’ (FOSC =
32 MHz) to set the oscillator upon device Power-up or Reset.
Write to the NOSC bits during run-time.
The HFINTOSC frequency can be selected by setting the HFFRQ bits.
The NDIV bits allow for division of the HFINTOSC output from a range between 1:1 and 1:512.
Related Links
Clock Switching
OSCCON1
OSCFRQ
9.2.2.2 MFINTOSC
The module provides two (500 kHz and 31.25 kHz) constant clock outputs. These clocks are digital
divisors of the HFINTOSC clock. Dynamic divider logic is used to provide constant MFINTOSC clock
rates for all settings of HFINTOSC.
The MFINTOSC cannot be used to drive the system but it is used to clock certain modules such as the
Timers and WWDT.
9.2.2.3 2x PLL
The oscillator module contains a PLL that can be used with the HFINTOSC clock source to provide a
system clock source. The input frequency to the PLL is limited to 8, 12, or 16 MHz, which will yield a
system clock source of 16, 24, or 32 MHz, respectively.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 101
The PLL may be enabled for use by one of two methods:
1. Program the RSTOSC bits in the Configuration Word 1 to ‘001’ to enable the HFINTOSC (32 MHz).
This setting configures the HFFRQ bits to ‘101’ (16 MHz) and activates the 2x PLL.
2. Write ‘001’ the NOSC bits to enable the 2x PLL, and write the correct value into the HFFRQ to
select the desired system clock frequency.
Related Links
OSCCON1
OSCFRQ
9.2.2.4 Internal Oscillator Frequency Adjustment
The internal oscillator is factory-calibrated. This internal oscillator can be adjusted in software by writing
to the OSCTUNE register.
The default value of the OSCTUNE register is 00h. The value is a 6-bit two’s complement number. A
value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an
adjustment to the minimum frequency.
When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency.
Code execution continues during this shift. There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the
LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), WWDT, Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the change in frequency.
Related Links
OSCTUNE
9.2.2.5 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is a factory-calibrated 31 kHz internal clock source.
The LFINTOSC is the frequency for the Power-up Timer (PWRT), Windowed Watchdog Timer (WWDT)
and Fail-Safe Clock Monitor (FSCM).
The LFINTOSC is enabled through one of the following methods:
Programming the RSTOSC bits of Configuration Word 1 to enable LFINTOSC.
Write to the NOSC bits during run-time.
Related Links
Clock Switching
CONFIG1
OSCCON1
9.2.2.6 ADCRC (also referred to as FRC)
The ADCRC is an oscillator dedicated to the ADC2 module. The ADCRC oscillator can be manually
enabled using the ADOEN bit. The ADCRC runs at a fixed frequency of 600 kHz. ADCRC is automatically
enabled if it is selected as the clock source for the ADC2 module.
9.2.2.7 Oscillator Status and Manual Enable
The ‘ready’ status of each oscillator is displayed in the OSCSTAT register. The oscillators can also be
manually enabled through the OSCEN register. Manual enabling makes it possible to verify the operation
of the EXTOSC or SOSC crystal oscillators. This can be achieved by enabling the selected oscillator,
then watching the corresponding ‘ready’ state of the oscillator in the OSCSTAT register.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 102
Related Links
OSCSTAT
OSCEN
9.2.2.8 HFOR and MFOR Bits
The HFOR and MFOR bits indicate that the HFINTOSC and MFINTOSC is ready. These clocks are
always valid for use at all times, but only accurate after they are ready.
When a new value is loaded into the OSCFRQ register, the HFOR and MFOR bits will clear, and set
again when the oscillator is ready. During pending OSCFRQ changes the MFINTOSC clock will stall at a
high or a low state, until the HFINTOSC resumes operation.
9.3 Clock Switching
The system clock source can be switched between external and internal clock sources via software using
the New Oscillator Source (NOSC) and New Divider selection request (NDIV) bits. The following clock
sources can be selected:
External Oscillator (EXTOSC)
High-Frequency Internal Oscillator (HFINTOSC)
Low-Frequency Internal Oscillator (LFINTOSC)
Secondary Oscillator (SOSC)
EXTOSC with 4x PLL
HFINTOSC with 2x PLL
9.3.1 New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits
The New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits select the system
clock source and frequency that are used for the CPU and peripherals.
When new values of NOSC and NDIV are written to OSCCON1, the current oscillator selection will
continue to operate while waiting for the new clock source to indicate that it is stable and ready. In some
cases, the newly requested source may already be in use, and is ready immediately. In the case of a
divider-only change, the new and old sources are the same, so the old source will be ready immediately.
The device may enter Sleep while waiting for the switch.
When the new oscillator is ready, the New Oscillator Ready (NOSCR) bit is set and also the Clock Switch
Interrupt Flag (CSWIF) bit of PIR1 sets. If Clock Switch Interrupts are enabled (CSWIE = 1), an interrupt
will be generated at that time. The Oscillator Ready (ORDY) bit of OSCCON3 can also be polled to
determine when the oscillator is ready in lieu of an interrupt.
If the Clock Switch Hold (CSWHOLD) bit is clear, the oscillator switch will occur when the New Oscillator
is READY bit (NOSCR) is set, and the interrupt (if enabled) will be serviced at the new oscillator setting.
If CSWHOLD is set, the oscillator switch is suspended, while execution continues using the current (old)
clock source. When the NOSCR bit is set, software should:
Set CSWHOLD = 0 so the switch can complete, or
Copy COSC into NOSC to abandon the switch.
If DOZE is in effect, the switch occurs on the next clock cycle, whether or not the CPU is operating during
that cycle.
Changing the clock post-divider without changing the clock source (i.e., changing FOSC from 1 MHz to 2
MHz) is handled in the same manner as a clock source change, as described previously. The clock
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 103
source will already be active, so the switch is relatively quick. CSWHOLD must be clear (CSWHOLD = 0)
for the switch to complete.
The current COSC and CDIV are indicated in the OSCCON2 register up to the moment when the switch
actually occurs, at which time OSCCON2 is updated and ORDY is set. NOSCR is cleared by hardware to
indicate that the switch is complete.
Related Links
Clock Switch and Sleep
OSCCON1
OSCCON2
OSCCON3
9.3.2 PLL Input Switch
Switching between the PLL and any non-PLL source is managed as described above. The input to the
PLL is established when NOSC selects the PLL, and maintained by the COSC setting.
When NOSC and COSC select the PLL with different input sources, the system continues to run using
the COSC setting, and the new source is enabled per NOSC. When the new oscillator is ready (and
CSWHOLD = 0), system operation is suspended while the PLL input is switched and the PLL acquires
lock. This provides a truly glitch-free clock switch operation.
Important:  If the PLL fails to lock, the FSCM will trigger.
9.3.3 Clock Switch and Sleep
If OSCCON1 is written with a new value and the device is put to Sleep before the switch completes, the
switch will not take place and the device will enter Sleep mode.
When the device wakes from Sleep and the CSWHOLD bit is clear, the device will wake with the ‘new’
clock active, and the clock switch interrupt flag bit (CSWIF) will be set.
When the device wakes from Sleep and the CSWHOLD bit is set, the device will wake with the ‘old’ clock
active and the new clock will be requested again.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 104
osc :2 use In use an as: «1 osccom WRITTEN osccom wnmsu
Figure 9-6. Clock Switch (CSWHOLD = 0)
Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.
CSWHOLD
NOSCR
OSC #2
CSWIF
OSCCON1
WRITTEN
NOTE 1
USER
CLEAR
OSC #1
NOTE 2
ORDY
Rev. 30-000064A
4/7/2016
Note: 
1. CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2. The assertion of NOSCR is hidden from the user because it appears only for the duration of the
switch.
Figure 9-7. Clock Switch (CSWHOLD = 1)
Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.
CSWHOLD
NOSCR
OSC #1 OSC #2
CSWIF
OSCCON1
WRITTEN
NOTE 1
ORDY
USER
CLEAR
Rev. 30-000065A
4/6/2017
Note: 
1. CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing
CSWHOLD = 0.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 105
osccom WRITTEN
Figure 9-8. Clock Switch Abandoned
CSWHOLD
NOSCR
OSC #1
CSWIF
OSCCON1
WRITTEN
NOTE 1
OSCCON1
WRITTEN
NOTE 2
ORDY
Rev. 30-000066A
4/6/2017
Note: 
1. CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.
2. ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.
9.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator
fail. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable
to all external Oscillator modes (LP, XT, HS, ECL/M/H and Secondary Oscillator).
Figure 9-9. FSCM Block Diagram
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 us)
488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
Rev. 30-000067A
4/6/2017
9.4.1 Fail-Safe Detection
The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 9-9. Inside the fail
detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an
entire half-cycle of the sample clock elapses before the external clock goes low.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 106
9.4.2 Fail-Safe Operation
When the external clock fails, the FSCM overwrites the COSC bits to select HFINTOSC (3'b110). The
frequency of HFINTOSC would be determined by the previous state of the HFFRQ bits and the NDIV/
CDIV bits. The bit flag OSCFIF of the PIR1 register is set. Setting this flag will generate an interrupt if the
OSCFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the
problems that may arise from a failed clock. The system clock will continue to be sourced from the
internal clock source until the device firmware successfully restarts the external oscillator and switches
back to external operation, by writing to the NOSC and NDIV bits.
9.4.3 Fail-Safe Condition Clearing
The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the NOSC
and NDIV bits. When switching to the external oscillator or PLL, the OST is restarted. While the OST is
running, the device continues to operate from the INTOSC selected in OSCCON1. When the OST times
out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The
OSCFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still
exists, the OSCFIF flag will again become set by hardware.
9.4.4 Reset or Wake-up from Sleep
The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the
EC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed.
Figure 9-10. FSCM Timing Diagram
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
(Q)
Test Test Test
Clock Monitor Output
Rev. 30-000068A
4/6/2017
Note:  The system clock is normally at a much higher frequency than the sample clock. The relative
frequencies in this example have been chosen for clarity.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 107
9.5 Register Summary - OSC
Offset Name Bit Pos.
0x088D OSCCON1 7:0 NOSC[2:0] NDIV[3:0]
0x088E OSCCON2 7:0 COSC[2:0] CDIV[3:0]
0x088F OSCCON3 7:0 CSWHOLD SOSCPWR ORDY NOSCR
0x0890 OSCSTAT 7:0 EXTOR HFOR MFOR LFOR SOR ADOR PLLR
0x0891 OSCEN 7:0 EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN
0x0892 OSCTUNE 7:0 HFTUN[5:0]
0x0893 OSCFRQ 7:0 HFFRQ[2:0]
9.6 Register Definitions: Oscillator Control
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 108
9.6.1 OSCCON1
Name:  OSCCON1
Address:  0x88D
Oscillator Control Register1
Bit 7 6 5 4 3 2 1 0
NOSC[2:0] NDIV[3:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset f f f q q q q
Bits 6:4 – NOSC[2:0]  New Oscillator Source Request bits(1,2,3)
The setting requests a source oscillator and PLL combination per Table 9-1.
Table 9-1. NOSC Bit Settings
NOSC<2:0> Clock Source
111 EXTOSC(5)
110 HFINTOSC(6)
101 LFINTOSC
100 SOSC
011 Reserved
010 EXTOSC + 4x PLL(5)
001 HFINTOSC + 2x PLL(6)
000 Reserved
Bits 3:0 – NDIV[3:0]  New Divider Selection Request bits(2,3,4)
The setting determines the new postscaler division ratio per Table 9-2.
Table 9-2. NDIV Bit Settings
NDIV<3:0> Clock Divider
1111-1010 Reserved
1001 512
1000 256
0111 128
0110 64
0101 32
0100 16
0011 8
0010 4
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
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NDIV<3:0> Clock Divider
0001 2
0000 1
Note: 
1. The default value (f) is determined by the CONFIG1[RSTOSC] Configuration bits.
2. If NOSC is written with a reserved value, the operation is ignored and NOSC is not written.
3. When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR
value.
4. When NOSC = 110 (HFINTOSC 1 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all
other NOSC settings the NDIV bits will default to ‘0000’ upon Reset.
5. EXTOSC configured by CONFIG1[FEXTOSC].
6. HFINTOSC frequency is set with the FRQ bits of the OSCFRQ register.
Related Links
CONFIG1
PLL Specifications
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
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9.6.2 OSCCON2
Name:  OSCCON2
Address:  0x88E
Oscillator Control Register 2
Bit 7 6 5 4 3 2 1 0
COSC[2:0] CDIV[3:0]
Access RO RO RO RO RO RO RO
Reset n n n n n n n
Bits 6:4 – COSC[2:0]  Current Oscillator Source Select bits (read-only)(1,2)
Indicates the current source oscillator and PLL combination as shown in the following table.
Table 9-3. COSC Bit Settings
COSC/NOSC Clock Source
111 EXTOSC(3)
110 HFINTOSC(4)
101 LFINTOSC
100 SOSC
011 Reserved
010 EXTOSC + 4x PLL(3)
001 HFINTOSC + 2x PLL(4)
000 Reserved
Bits 3:0 – CDIV[3:0]  Current Divider Select bits (read-only)(1,2)
Indicates the current postscaler division ratio as shown in the following table.
Table 9-4. CDIV Bit Settings
CDIV/NDIV Clock Divider
1111-1010 Reserved
1001 512
1000 256
0111 128
0110 64
0101 32
0100 16
0011 8
0010 4
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
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CDIV/NDIV Clock Divider
0001 2
0000 1
Note: 
1. The POR value is the value present when user code execution begins.
2. The Reset value (n) is the same as the OSCCON1[NOSC/NDIV] bits.
3. EXTOSC configured by the CONFIG1[FEXTOSC] bits.
4. HFINTOSC frequency is configured with the FRQ bits of the OSCFRQ register
Related Links
CONFIG1
PLL Specifications
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
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9.6.3 OSCCON3
Name:  OSCCON3
Address:  0x88F
Oscillator Control Register 3
Bit 7 6 5 4 3 2 1 0
CSWHOLD SOSCPWR ORDY NOSCR
Access R/W/HC R/W RO RO
Reset 0 0 0 0
Bit 7 – CSWHOLD Clock Switch Hold bit
Value Description
1 Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready
0 Clock switch may proceed when the oscillator selected by NOSC is ready; when NOSCR
becomes ‘1’, the switch will occur
Bit 6 – SOSCPWR Secondary Oscillator Power Mode Select bit
Value Description
1 Secondary oscillator operating in High-Power mode
0 Secondary oscillator operating in Low-Power mode
Bit 4 – ORDY Oscillator Ready bit (read-only)
Value Description
1 OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0 A clock switch is in progress
Bit 3 – NOSCR  New Oscillator is Ready bit (read-only)(1)
Value Description
1 A clock switch is in progress and the oscillator selected by NOSC indicates a ready condition
0 A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready
Note: 
1. If CSWHOLD = 0, the user may not see this bit set because the bit is set for less than one
instruction cycle.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
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9.6.4 OSCSTAT
Name:  OSCSTAT
Address:  0x890
Oscillator Status Register 1
Bit 7 6 5 4 3 2 1 0
EXTOR HFOR MFOR LFOR SOR ADOR PLLR
Access RO RO RO RO RO RO RO
Reset q q q q q q q
Bit 7 – EXTOR EXTOSC (external) Oscillator Ready bit
Value Description
1 The oscillator is ready to be used
0 The oscillator is not enabled, or is not yet ready to be used
Bit 6 – HFOR HFINTOSC Oscillator Ready bit
Value Description
1 The oscillator is ready to be used
0 The oscillator is not enabled, or is not yet ready to be used
Bit 5 – MFOR MFINTOSC Oscillator Ready bit
Value Description
1 The oscillator is ready to be used
0 The oscillator is not enabled, or is not yet ready to be used
Bit 4 – LFOR LFINTOSC Oscillator Ready bit
Value Description
1 The oscillator is ready to be used
0 The oscillator is not enabled, or is not yet ready to be used
Bit 3 – SOR Secondary (Timer1) Oscillator Ready bit
Value Description
1 The oscillator is ready to be used
0 The oscillator is not enabled, or is not yet ready to be used
Bit 2 – ADOR ADC Oscillator Ready bit
Value Description
1 The oscillator is ready to be used
0 The oscillator is not enabled, or is not yet ready to be used
Bit 0 – PLLR PLL Ready bit
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 114
Value Description
1 The PLL is ready to be used
0 The PLL is not enabled, the required input source is not ready, or the PLL is not locked.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 115
9.6.5 OSCEN
Name:  OSCEN
Address:  0x891
Oscillator Manual Enable Register
Bit 7 6 5 4 3 2 1 0
EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 – EXTOEN External Oscillator Manual Request Enable bit
Value Description
1 EXTOSC is explicitly enabled, operating as specified by CONFIG1[FEXTOSC]
0 EXTOSC is only enabled if requested by a peripheral
Bit 6 – HFOEN HFINTOSC Oscillator Manual Request Enable bit
Value Description
1 HFINTOSC is explicitly enabled, operating as specified by OSCFRQ
0 HFINTOSC is only enabled if requested by a peripheral
Bit 5 – MFOEN MFINTOSC (500 kHz/31.25 kHz) Oscillator Manual Request Enable bit (Derived from
HFINTOSC)
Value Description
1 MFINTOSC is explicitly enabled
0 MFINTOSC is only enabled if requested by a peripheral
Bit 4 – LFOEN LFINTOSC (31 kHz) Oscillator Manual Request Enable bit
Value Description
1 LFINTOSC is explicitly enabled
0 LFINTOSC is only enabled if requested by a peripheral
Bit 3 – SOSCEN Secondary Oscillator Manual Request Enable bit
Value Description
1 Secondary Oscillator is explicitly enabled, operating as specified by SOSCPWR
0 Secondary Oscillator is only enabled if requested by a peripheral
Bit 2 – ADOEN ADC Oscillator Manual Request Enable bit
Value Description
1 ADC oscillator is explicitly enabled
0 ADC oscillator is only enabled if requested by a peripheral
Related Links
CONFIG1
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 116
9.6.6 OSCTUNE
Name:  OSCTUNE
Address:  0x892
HFINTOSC Tuning Register
Bit 7 6 5 4 3 2 1 0
HFTUN[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 5:0 – HFTUN[5:0] HFINTOSC Frequency Tuning bits
Value Description
01 1111 Maximum frequency
00 0000 Center frequency. Oscillator module is running at the calibrated frequency (default value).
10 0000 Minimum frequency
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 117
9.6.7 OSCFRQ
Name:  OSCFRQ
Address:  0x893
HFINTOSC Frequency Selection Register
Bit 7 6 5 4 3 2 1 0
HFFRQ[2:0]
Access R/W R/W R/W
Reset q q q
Bits 2:0 – HFFRQ[2:0] HFINTOSC Frequency Selection bits
FRQ<2:0>
Nominal Frequency
(MHz)
(NOSC = 110)
2x PLL Frequency
(MHz)
(NOSC = 001)
111 Reserved Reserved
110 32
101 16 32
100 12 24
011 8 16
010 4
Reserved001 2
000 1
Note: 
1. When RSTOSC = 110 (HFINTOSC 1 MHz), the FRQ bits will default to ‘010’ upon Reset; when
RSTOSC = 001 (HFINTOSC 32 MHz), the FRQ bits will default to ‘101’ upon Reset.
PIC16(L)F18426/46
Oscillator Module (with Fail-Safe Clock Monitor)
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 118
Wake-up m m S‘eep mo
10. Interrupts
The interrupt feature allows certain events to preempt normal program flow. Firmware is used to
determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the
MCU from Sleep mode.
This chapter contains the following information for Interrupts:
• Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
Many peripherals produce interrupts. Refer to the corresponding chapters for details.
A block diagram of the interrupt logic is shown below.
Figure 10-1. Interrupt Logic
Filename: 10-000010C.vsd
Title: Interrupt Logic
Last Edit: 10/12/2016
First Used: PIC16(L)F191XX (MVAJ)
TMR0IF
TMR0IE
INTF
INTE
IOCIF
IOCIE Interrupt
to CPU
Wake-up
(If in Sleep mode)
GIE
(ADIF) PIR1 <0>
PIRn
PEIE
(ADIE) PIE1 <0>
Peripheral Interrupts
PIEn
Rev. 10-000010C
10/12/2016
10.1 Operation
Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:
GIE bit of the INTCON register
Interrupt Enable bit(s) of the PIEx[y] registers for the specific interrupt event(s)
PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the
PIEx registers)
The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are 9 PIR registers.
The following events happen when an interrupt event occurs while the GIE bit is set:
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the stack
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Interrupts
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Critical registers are automatically saved to the shadow registers (see “Automatic Context Saving”)
PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by
polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid
repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will
be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE bit.
For additional information on a specific interrupts operation, refer to its peripheral chapter.
Important: 
1. Individual interrupt flag bits are set, regardless of the state of any other enable bits.
2. All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the
GIE bit is clear will be serviced when the GIE bit is set again.
Related Links
Automatic Context Saving
10.2 Interrupt Latency
Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at
the interrupt vector begins. The interrupt is sampled during Q1 of the instruction cycle. The actual
interrupt latency then depends on the instruction that is executing at the time the interrupt is detected.
See the following figures for more details.
Figure 10-2. Interrupt Latency
Filename: 10-000269E.vsd
Title: INT LATENCY - ONE CYCLE
Last Edit: 8/31/2016
First Used: PIC16(L)F18325/45 (MFAH)
Notes:
Rev. 10-000269E
8/31/2016
Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q2Q2Q2Q2Q2Q2 Q2Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q4Q4Q4Q4Q4Q4Q4
OSC1
CLKOUT
INT
pin
PC - 1 PC
Fetch
Execute PC - 2 PC - 1 PC
PC + 1
NOP NOP
PC = 0x0004
PC = 0x0004
PC = 0x0005
PC = 0x0005
PC = 0x0006
1 Cycle Instruction at PC
Latency
Valid Interrupt
window(1)
Indeterminate
Latency(2)
Note 1: An interrupt may occur at any time during the interrupt window.
2: Since an interrupt may occur any time during the interrupt window, the actual latency can vary.
Note: 
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Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 120
1. An interrupt may occur at any time during the interrupt window.
2. Since an interrupt may occur any time during the interrupt window, the actual latency can vary.
Figure 10-3. INT Pin Interrupt Timing
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
INT pin
INTF
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) Inst (0005h)
For ced NOP
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
For ced NOP
Inst (PC)
(1)
(2)
(4)
(5)
(1)
Rev. 30-000150A
6/27/2017
Note: 
1. INTF flag is sampled here (every Q1).
2. Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction
cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3. For minimum width of INT pulse, refer to AC specifications in the “Electrical Specifications” section.
4. INTF may be set any time during the Q4-Q1 cycles.
10.3 Interrupts During Sleep
Interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate
without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior
to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector.
Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction
directly after the SLEEP instruction will always be executed before branching to the ISR.
Related Links
Power-Saving Operation Modes
10.4 INT Pin
The INT pin can be used to generate an asynchronous edge-triggered interrupt. Refer to Figure 10-3.
This interrupt is enabled by setting the INTE bit of the PIE0 register. The INTEDG bit of the INTCON
register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge
will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF
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Interrupts
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bit of the PIR0 register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are
also set, the processor will redirect program execution to the interrupt vector.
10.5 Automatic Context Saving
Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following
registers are automatically saved in the shadow registers:
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If modifications to any of these registers are desired, the
corresponding shadow register should be modified and the value will be restored when exiting the ISR.
The shadow registers are available in Bank 63 and are readable and writable. Depending on the users
application, other registers may also need to be saved.
Related Links
Register Definitions: Shadow Registers
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Interrupts
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10.6 Register Summary - Interrupt Control
Offset Name Bit Pos.
0x070C PIR0 7:0 TMR0IF IOCIF INTF
0x070D PIR1 7:0 OSFIF CSWIF ADTIF ADIF
0x070E PIR2 7:0 ZCDIF C2IF C1IF
0x070F PIR3 7:0 RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF
0x0710 PIR4 7:0 TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF
0x0711 PIR5 7:0 CLC4IF CLC3IF CL24IF CLC1IF TMR5GIF TMR3GIF TMR1GIF
0x0712 PIR6 7:0 CCP4IF CCP3IF CCP2IF CCP1IF
0x0713 PIR7 7:0 NVMIF NCO1IF CWG2IF CWG1IF
0x0714 PIR8 7:0 SMT1PWAIF SMT1PRAIF SMT1IF
0x0715 Reserved
0x0716 PIE0 7:0 TMR0IE IOCIE INTE
0x0717 PIE1 7:0 OSFIE CSWIE ADTIE ADIE
0x0718 PIE2 7:0 ZCDIE C2IE C1IE
0x0719 PIE3 7:0 RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE
0x071A PIE4 7:0 TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE
0x071B PIE5 7:0 CLC4IE CLC3IE CLC2IE CLC1IE TMR5GIE TMR3GIE TMR1GIE
0x071C PIE6 7:0 CCP4IE CCP3IE CCP2IE CCP1IE
0x071D PIE7 7:0 NVMIE NCO1IE CWG2IE CWG1IE
0x071E PIE8 7:0 SMT1PWAIE SMT1PRAIE SMT1IE
10.7 Register Definitions: Interrupt Control
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Interrupts
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10.7.1 INTCON
Name:  INTCON
Address:  0x00B
Interrupt Control Register
Bit 7 6 5 4 3 2 1 0
GIE PEIE INTEDG
Access R/W R/W R/W
Reset 0 0 1
Bit 7 – GIE Global Interrupt Enable bit
Value Description
1 Enables all active interrupts
0 Disables all interrupts
Bit 6 – PEIE Peripheral Interrupt Enable bit
Value Description
1 Enables all active peripheral interrupts
0 Disables all peripheral interrupts
Bit 0 – INTEDG External Interrupt Edge Select bit
Value Description
1 Interrupt on rising edge of INT pin
0 Interrupt on falling edge of INT pin
Important:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt
flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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10.7.2 PIE0
Name:  PIE0
Address:  0x716
Peripheral Interrupt Enable Register 0
Bit 7 6 5 4 3 2 1 0
TMR0IE IOCIE INTE
Access R/W R/W R/W
Reset 0 0 0
Bit 5 – TMR0IE  Timer0 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 4 – IOCIE  Interrupt-on-Change Enable bit
Value Description
1 Enabled
0 Disabled
Bit 0 – INTE  External Interrupt Enable bit(1)
Value Description
1 Enabled
0 Disabled
Note: 
1. The External Interrupt INT pin is selected by INTPPS.
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by PIE1-
PIE8. Interrupt sources controlled by the PIE0 register do not require PEIE to be set in order to allow
interrupt vectoring (when GIE is set).
Related Links
xxxPPS
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10.7.3 PIE1
Name:  PIE1
Address:  0x717
Peripheral Interrupt Enable Register 1
Bit 7 6 5 4 3 2 1 0
OSFIE CSWIE ADTIE ADIE
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 – OSFIE Oscillator Fail Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 6 – CSWIE Clock-Switch Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 1 – ADTIE ADC Threshold Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 0 – ADIE ADC Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
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10.7.4 PIE2
Name:  PIE2
Address:  0x718
Peripheral Interrupt Enable Register 2
Bit 7 6 5 4 3 2 1 0
ZCDIE C2IE C1IE
Access R/W R/W R/W
Reset 0 0 0
Bit 6 – ZCDIE Zero-Cross Detect Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bits 0, 1 – CnIE Comparator ‘n’ Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
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Interrupts
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10.7.5 PIE3
Name:  PIE3
Address:  0x719
Peripheral Interrupt Enable Register 3
Bit 7 6 5 4 3 2 1 0
RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 5 – RCnIE EUSARTn Receive Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 4 – TXnIE EUSARTn Transmit Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bits 1, 3 – BCLnIE MSSPn Bus Collision Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bits 0, 2 – SSPnIE Synchronous Serial Port ‘n’ Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
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10.7.6 PIE4
Name:  PIE4
Address:  0x71A
Peripheral Interrupt Enable Register 4
Bit 7 6 5 4 3 2 1 0
TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 5 – TMR6IE TMR6 to PR6 Match Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 4 – TMR5IE TMR5 Overflow Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 3 – TMR4IE TMR4 to PR4 Match Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 2 – TMR3IE TMR3 Overflow Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 1 – TMR2IE TMR2 to PR2 Match Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 0 – TMR1IE TMR1 Overflow Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
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10.7.7 PIE5
Name:  PIE5
Address:  0x71B
Peripheral Interrupt Enable Register 5
Bit 7 6 5 4 3 2 1 0
CLC4IE CLC3IE CLC2IE CLC1IE TMR5GIE TMR3GIE TMR1GIE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – CLC4IE CLC4 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 6 – CLC3IE CLC3 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 5 – CLC2IE CLC2 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 4 – CLC1IE CLC1 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 2 – TMR5GIE TMR5 Gate Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 1 – TMR3GIE TMR3 Gate Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 0 – TMR1GIE TMR1 Gate Interrupt Enable bit
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Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
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10.7.8 PIE6
Name:  PIE6
Address:  0x71C
Peripheral Interrupt Enable Register 6
Bit 7 6 5 4 3 2 1 0
CCP4IE CCP3IE CCP2IE CCP1IE
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – CCP4IE CCP4 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 2 – CCP3IE CCP3 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 1 – CCP2IE CCP2 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 0 – CCP1IE CCP1 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 132
10.7.9 PIE7
Name:  PIE7
Address:  0x71D
Peripheral Interrupt Enable Register 7
Bit 7 6 5 4 3 2 1 0
NVMIE NCO1IE CWG2IE CWG1IE
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – NVMIE NVM Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 4 – NCO1IE NCO Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 1 – CWG2IE CWG2 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 0 – CWG1IE CWG1 Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 133
10.7.10 PIE8
Name:  PIE8
Address:  0x71E
Peripheral Interrupt Enable Register 8
Bit 7 6 5 4 3 2 1 0
SMT1PWAIE SMT1PRAIE SMT1IE
Access R/W R/W R/W
Reset 0 0 0
Bit 2 – SMT1PWAIE SMT1 Pulse-width Acquisition Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 1 – SMT1PRAIE SMT1 Period Acquisition Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Bit 0 – SMT1IE SMT1 Counter Overflow Interrupt Enable bit
Value Description
1 Enabled
0 Disabled
Note:  Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by
registers PIE1-PIE8.
PIC16(L)F18426/46
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 134
10.7.11 PIR0
Name:  PIR0
Address:  0x70C
Peripheral Interrupt Request (Flag) Register 0
Bit 7 6 5 4 3 2 1 0
TMR0IF IOCIF INTF
Access R/W/HS RO R/W/HS
Reset 0 0 0
Bit 5 – TMR0IF  Timer0 Interrupt Flag bit
Value Description
1 TMR0 register has overflowed (must be cleared by software)
0 TMR0 register has not overflowed
Bit 4 – IOCIF  Interrupt-on-Change Flag bit(2)
Value Description
1 One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge
was detected by the IOC module.
0 None of the IOCAF-IOCEF register bits are currently set
Bit 0 – INTF  External Interrupt Flag bit(1)
Value Description
1 External Interrupt has occurred
0 External Interrupt has not occurred
Note: 
1. The External Interrupt INT pin is selected by INTPPS.
2. The IOCIF bit is the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag,
application firmware must clear all of the lower level IOCAF-IOCEF register bits.
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
Related Links
xxxPPS
PIC16(L)F18426/46
Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 135
10.7.12 PIR1
Name:  PIR1
Address:  0x70D
Peripheral Interrupt Request (Flag) Register 1
Bit 7 6 5 4 3 2 1 0
OSFIF CSWIF ADTIF ADIF
Access R/W/HS R/W/HS R/W/HS R/W/HS
Reset 0 0 0 0
Bit 7 – OSFIF Oscillator Fail Interrupt Flag bit
Value Description
1 Oscillator fail-safe interrupt has occurred (must be cleared in software)
0 No oscillator fail-safe interrupt
Bit 6 – CSWIF  Clock-Switch Complete Interrupt Flag bit
Value Description
1 The clock switch module indicates an interrupt condition and is ready to complete the clock
switch operation (must be cleared in software)
0 The clock switch does not indicate an interrupt condition
Bit 1 – ADTIF ADC Threshold Interrupt Flag bit
Value Description
1 An A/D conversion or complex operation has completed (must be cleared in software)
0 An A/D conversion or complex operation is not complete
Bit 0 – ADIF ADC Interrupt Flag bit
Value Description
1 An A/D conversion or complex operation has completed (must be cleared in software)
0 An A/D conversion or complex operation is not complete
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 136
10.7.13 PIR2
Name:  PIR2
Address:  0x70E
Peripheral Interrupt Request (Flag) Register 2
Bit 7 6 5 4 3 2 1 0
ZCDIF C2IF C1IF
Access R/W/HS R/W/HS R/W/HS
Reset 0 0 0
Bit 6 – ZCDIF Zero-Cross Detect Interrupt Flag bit
Value Description
1 An enabled rising and/or falling ZCD1 event has been detected (must be cleared in software)
0 No ZCD1 event has occurred
Bits 0, 1 – CnIF Comparator ‘n’ Interrupt Flag bit
Value Description
1 Comparator Cn interrupt asserted (must be cleared in software)
0 Comparator Cn interrupt not asserted
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
PIC16(L)F18426/46
Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 137
10.7.14 PIR3
Name:  PIR3
Address:  0x70F
Peripheral Interrupt Request (Flag) Register 3
Bit 7 6 5 4 3 2 1 0
RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF
Access RO/HS RO/HS R/W/HS R/W/HS R/W/HS R/W/HS
Reset 0 0 0 0 0 0
Bit 5 – RCnIF  EUSARTn Receive Interrupt Flag bit(1)
Value Description
1 The EUSARTn receive buffer is not empty (contains at least one byte)
0 The EUSARTn receive buffer is empty
Bit 4 – TXnIF  EUSARTn Transmit Interrupt Flag bit(2)
Value Description
1 The EUSARTn transmit buffer contains at least one unoccupied space
0 The EUSARTn transmit buffer is currently full. The application firmware should not write to
TXnREG again, until more room becomes available in the transmit buffer.
Bits 1, 3 – BCLnIF MSSPn Bus Collision Interrupt Flag bit
Value Description
1 A bus collision was detected (must be cleared in software)
0 No bus collision was detected
Bits 0, 2 – SSPnIF Synchronous Serial Port ‘n’ Interrupt Flag bit
Value Description
1 The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 Waiting for the Transmission/Reception/Bus Condition in progress
Note: 
1. The RCnIF flag is a read-only bit. To clear the RCnIF flag, the firmware must read from RCnREG
enough times to remove all bytes from the receive buffer.
2. The TXnIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TXnIF
flag, the firmware must write enough data to TXnREG to completely fill all available bytes in the
buffer. The TXnIF flag does not indicate transmit completion (use TRMT for this purpose instead).
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
PIC16(L)F18426/46
Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 138
10.7.15 PIR4
Name:  PIR4
Address:  0x710
Peripheral Interrupt Request (Flag) Register 4
Bit 7 6 5 4 3 2 1 0
TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF
Access R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS
Reset 0 0 0 0 0 0
Bit 5 – TMR6IF TMR6 to PR6 Match Interrupt Flag bit
Value Description
1 The TMR6 postscaler overflowed, or in 1:1 mode, a TMR6 to PR6 match occurred (must be
cleared in software)
0 No TMR6 event has occurred
Bit 4 – TMR5IF TMR5 Overflow Interrupt Flag bit
Value Description
1 TMR5 register overflowed (must be cleared in software)
0 TMR5 register did not overflow
Bit 3 – TMR4IF TMR4 to PR4 Match Interrupt Flag bit
Value Description
1 The TMR4 postscaler overflowed, or in 1:1 mode, a TMR4 to PR4 match occurred (must be
cleared in software)
0 No TMR4 event has occurred
Bit 2 – TMR3IF TMR3 Overflow Interrupt Flag bit
Value Description
1 TMR3 register overflowed (must be cleared in software)
0 TMR3 register did not overflow
Bit 1 – TMR2IF TMR2 to PR2 Match Interrupt Flag bit
Value Description
1 The TMR2 postscaler overflowed, or in 1:1 mode, a TMR2 to PR2 match occurred (must be
cleared in software)
0 No TMR2 event has occurred
Bit 0 – TMR1IF TMR1 Overflow Interrupt Flag bit
Value Description
1 TMR1 register overflowed (must be cleared in software)
0 TMR1 register did not overflow
PIC16(L)F18426/46
Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 139
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
PIC16(L)F18426/46
Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 140
10.7.16 PIR5
Name:  PIR5
Address:  0x711
Peripheral Interrupt Request (Flag) Register 5
Bit 7 6 5 4 3 2 1 0
CLC4IF CLC3IF CL24IF CLC1IF TMR5GIF TMR3GIF TMR1GIF
Access R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS
Reset 0 0 0 0 0 0 0
Bit 7 – CLC4IF CLC4 Interrupt Flag bit
Value Description
1 A CLC4OUT interrupt condition has occurred (must be cleared in software)
0 No CLC4 interrupt event has occurred
Bit 6 – CLC3IF CLC3 Interrupt Flag bit
Value Description
1 A CLC3OUT interrupt condition has occurred (must be cleared in software)
0 No CLC3 interrupt event has occurred
Bit 5 – CL24IF CLC2 Interrupt Flag bit
Value Description
1 A CLC2OUT interrupt condition has occurred (must be cleared in software)
0 No CLC2 interrupt event has occurred
Bit 4 – CLC1IF CLC1 Interrupt Flag bit
Value Description
1 A CLC1OUT interrupt condition has occurred (must be cleared in software)
0 No CLC1 interrupt event has occurred
Bit 2 – TMR5GIF TMR5 Gate Interrupt Flag bit
Value Description
1 The Timer5 Gate has gone inactive (the acquisition is complete)
0 The Timer5 Gate has not gone inactive
Bit 1 – TMR3GIF TMR3 Gate Interrupt Flag bit
Value Description
1 The Timer3 Gate has gone inactive (the acquisition is complete)
0 The Timer3 Gate has not gone inactive
Bit 0 – TMR1GIF TMR1 Gate Interrupt Flag bit
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Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 141
Value Description
1 The Timer1 Gate has gone inactive (the acquisition is complete)
0 The Timer1 Gate has not gone inactive
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
PIC16(L)F18426/46
Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 142
10.7.17 PIR6
Name:  PIR6
Address:  0x712
PIR6 Peripheral Interrupt Request (Flag) Register 6
Bit 7 6 5 4 3 2 1 0
CCP4IF CCP3IF CCP2IF CCP1IF
Access R/W/HS R/W/HS R/W/HS R/W/HS
Reset 0 0 0 0
Bit 3 – CCP4IF CCP4 Interrupt Flag bit
Value Condition Description
1 Capture mode Capture occurred (must be cleared in software)
0 Capture mode Capture did not occur
1 Compare mode Compare match occurred (must be cleared in software)
0 Compare mode Compare match did not occur
1 PWM mode Output trailing edge occurred (must be cleared in software)
0 PWM mode Output trailing edge did not occur
Bit 2 – CCP3IF CCP3 Interrupt Flag bit
Value Condition Description
1 Capture mode Capture occurred (must be cleared in software)
0 Capture mode Capture did not occur
1 Compare mode Compare match occurred (must be cleared in software)
0 Compare mode Compare match did not occur
1 PWM mode Output trailing edge occurred (must be cleared in software)
0 PWM mode Output trailing edge did not occur
Bit 1 – CCP2IF CCP2 Interrupt Flag bit
Value Condition Description
1 Capture mode Capture occurred (must be cleared in software)
0 Capture mode Capture did not occur
1 Compare mode Compare match occurred (must be cleared in software)
0 Compare mode Compare match did not occur
1 PWM mode Output trailing edge occurred (must be cleared in software)
0 PWM mode Output trailing edge did not occur
Bit 0 – CCP1IF CCP1 Interrupt Flag bit
Value Condition Description
1 Capture mode Capture occurred (must be cleared in software)
0 Capture mode Capture did not occur
1 Compare mode Compare match occurred (must be cleared in software)
0 Compare mode Compare match did not occur
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Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 143
Value Condition Description
1 PWM mode Output trailing edge occurred (must be cleared in software)
0 PWM mode Output trailing edge did not occur
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
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Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 144
10.7.18 PIR7
Name:  PIR7
Address:  0x713
Peripheral Interrupt Request (Flag) Register 7
Bit 7 6 5 4 3 2 1 0
NVMIF NCO1IF CWG2IF CWG1IF
Access R/W/HS R/W/HS R/W/HS R/W/HS
Reset 0 0 0 0
Bit 5 – NVMIF NVM Interrupt Flag bit
Value Description
1 The requested NVM operation has completed
0 NVM interrupt not asserted
Bit 4 – NCO1IF Numerically Controlled Oscillator (NCO) Interrupt Flag bit
Value Description
1 The NCO has rolled over
0 No NCO interrupt event has occurred
Bit 1 – CWG2IF CWG2 Interrupt Flag bit
Value Description
1 CWG2 has gone into shutdown
0 CWG2 is operating normally, or interrupt cleared
Bit 0 – CWG1IF CWG1 Interrupt Flag bit
Value Description
1 CWG1 has gone into shutdown
0 CWG1 is operating normally, or interrupt cleared
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
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Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 145
10.7.19 PIR8
Name:  PIR8
Address:  0x714
Peripheral Interrupt Request (Flag) Register 8
Bit 7 6 5 4 3 2 1 0
SMT1PWAIF SMT1PRAIF SMT1IF
Access R/W/HS R/W/HS R/W/HS
Reset 0 0 0
Bit 2 – SMT1PWAIF SMT1 Pulse-Width Acquisition Interrupt Flag bit
Value Description
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred
Bit 1 – SMT1PRAIF SMT1 Period Acquisition Interrupt Flag bit
Value Description
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred
Bit 0 – SMT1IF SMT1 Interrupt Flag bit
Value Description
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred
Note:  Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are
clear prior to enabling an interrupt.
PIC16(L)F18426/46
Interrupts
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 146
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11. Power-Saving Operation Modes
The purpose of the Power-Down modes is to reduce power consumption. There are three Power-Down
modes:
Doze mode
Sleep mode
Idle mode
11.1 Doze Mode
Doze mode allows for power saving by reducing CPU operation and program memory (PFM) access,
without affecting peripheral operation. Doze mode differs from Sleep mode because the bandgap and
system oscillators continue to operate, while only the CPU and PFM are affected. The reduced execution
saves power by eliminating unnecessary operations within the CPU and memory.
When the Doze Enable bit is set (DOZEN = 1), the CPU executes only one instruction cycle out of every
N cycles as defined by the DOZE bits. For example, if DOZE = 001, the instruction cycle ratio is 1:4. The
CPU and memory execute for one instruction cycle and then lay idle for three instruction cycles. During
the unused cycles, the peripherals continue to operate at the system clock speed.
Related Links
CPUDOZE
11.1.1 Doze Operation
The Doze operation is illustrated in Figure 11-1. For this example:
Doze enabled (DOZEN = 1)
DOZE = 001 (1:4) ratio
Recover-on-Interrupt enabled (ROI = 1)
As with normal operation, the PFM fetches for the next instruction cycle. The Q-clocks to the peripherals
continue throughout.
Figure 11-1. DOZE MODE OPERATION EXAMPLE (DOZE<2:0> = 001, 1:4)
Rev. 3000089A
4/11/2017
11.1.2 Interrupts During Doze
System behavior if an interrupt occurs during DOZE can be configured using the Recover-On-Interrupt
(ROI) bit and the Doze-On-Exit (DOE) bit. Refer to the table below for details about system behavior in all
cases for a transition from Main to ISR back to Main.
PIC16(L)F18426/46
Power-Saving Operation Modes
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 147
Table 11-1. Interrupts During DOZE
DOZEN ROI
Code Flow
Main ISR(1) Return to Main
0 0 Normal
Operation
Normal operation and
DOE = DOZEN (in
hardware) DOZEN = 0
(unchanged)
If DOE = 1 when return
from interrupt: DOZE
operation and DOZEN =
1 (in hardware)
If DOE = 0 when return
from interrupt: Normal
operation and DOZEN =
0 (in hardware)
0 1 Normal
Operation
Normal operation and
DOE = DOZEN (in
hardware) DOZEN = 0
(unchanged)
1 0 DOZE
operation
DOZE operation and
DOE = DOZEN (in
hardware) DOZEN = 1
(unchanged)
1 1 DOZE
operation
Normal operation and
DOE = DOZEN (in
hardware) DOZEN = 0
(unchanged)
Note: 
1. User software can change DOE bit in the ISR.
11.2 Sleep Mode
Sleep mode is entered by executing the SLEEP instruction, while the Idle Enable (IDLEN) bit of the
CPUDOZE register is clear (IDLEN = 0).
Upon entering Sleep mode, the following conditions exist:
1. WDT will be cleared but keeps running if enabled for operation during Sleep
2. The PD bit of the STATUS register is cleared
3. The TO bit of the STATUS register is set
4. The CPU clock is disabled
5. LFINTOSC, SOSC, HFINTOSC and ADCRC are unaffected and peripherals using them may
continue operation in Sleep.
6. I/O ports maintain the status they had before Sleep was executed (driving high, low, or high-
impedance)
7. Resets other than WDT are not affected by Sleep mode
Refer to individual chapters for more details on peripheral operation during Sleep.
To minimize current consumption, the following conditions should be considered:
I/O pins should not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
PIC16(L)F18426/46
Power-Saving Operation Modes
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 148
Current draw from pins with internal weak pull-ups
Modules using any oscillator
I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR
modules.
Related Links
Low-Power Sleep Mode
STATUS
(FVR) Fixed Voltage Reference
(DAC) 5-Bit Digital-to-Analog Converter Module
11.2.1 Wake-up from Sleep
The device can wake-up from Sleep through one of the following events:
1. External Reset input on MCLR pin, if enabled.
2. BOR Reset, if enabled.
3. POR Reset.
4. Windowed Watchdog Timer, if enabled.
5. Any external interrupt.
6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more
information).
The first three events will cause a device Reset. The last three events are considered a continuation of
program execution. To determine whether a device Reset or wake-up event occurred, refer to the
“Memory Execution Violation” section.
When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device
to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up
will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution
at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction
after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the
execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP
instruction.
The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up.
Related Links
Memory Execution Violation
11.2.2 Wake-up Using Interrupts
When global interrupts are disabled (GIE cleared) and any interrupt source, with the exception of the
clock switch interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will
occur:
If the interrupt occurs before the execution of a SLEEP instruction
SLEEP instruction will execute as a NOP
WDT and WDT prescaler will not be cleared
TO bit of the STATUS register will not be set
PIC16(L)F18426/46
Power-Saving Operation Modes
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 149
1 “““ ,3 , , , , , , , , , , c , - , m , - , - , , , , , , , , , , , , , ,
PD bit of the STATUS register will not be cleared
If the interrupt occurs during or after the execution of a SLEEP instruction
SLEEP instruction will be completely executed
Device will immediately wake-up from Sleep
WDT and WDT prescaler will be cleared
TO bit of the STATUS register will be set
PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
Figure 11-2. WAKE-UP FROM SLEEP THROUGH INTERRUPT
CLKIN(1)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(4)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Forced NOP
PC + 2 0004h 0005h
Forced NOP
TOST(3)
PC + 2
Rev. 3000090A
4/12/2017
Note: 
1. External clock. High, Medium, Low mode assumed.
2. CLKOUT is shown here for timing reference.
3. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.
4. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0,
execution will continue in-line.
11.2.3 Low-Power Sleep Mode
The PIC16(L)F18426/46 devices contain an internal Low Dropout (LDO) voltage regulator, which allows
the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower
voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep
mode.
The PIC16(L)F18426/46 devices allow the user to optimize the operating current in Sleep, depending on
the application requirements.
Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register.
Depending on the configuration of these bits, the LDO and reference circuitry are placed in a low-power
state when the device is in Sleep.
11.2.3.1 Sleep Current vs. Wake-up Time
In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep
mode, when waking-up from Sleep, an extra delay time is required for these circuits to return to the
normal configuration and stabilize.
PIC16(L)F18426/46
Power-Saving Operation Modes
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 150
£9
The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.
11.2.3.2 Peripheral Usage in Sleep
Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep
mode selected. The Low-Power Sleep mode is intended for use with these peripherals:
Brown-out Reset (BOR)
Windowed Watchdog Timer (WWDT)
External interrupt pin/Interrupt-On-Change pins
Timer1 (with external clock source)
It is the responsibility of the end user to determine what is acceptable for their application when setting
the VREGPM settings in order to ensure operation in Sleep.
Important:  The LF devices do not have a configurable Low-Power Sleep mode. LFs are
unregulated devices and are always in the lowest power state when in Sleep, with no wake-up
time penalty. These devices have a lower maximum VDD and I/O voltage than the F devices.
11.3 Idle Mode
When the Idle Enable (IDLEN) bit is clear (IDLEN = 0), the SLEEP instruction will put the device into full
Sleep mode. When IDLEN is set (IDLEN = 1), the SLEEP instruction will put the device into IDLE mode.
In IDLE mode, the CPU and memory operations are halted, but the peripheral clocks continue to run. This
mode is similar to DOZE mode, except that in IDLE both the CPU and program memory are shut off.
Important:  Peripherals using FOSC will continue running while in Idle (but not in Sleep).
Peripherals using HFINTOSC:LFINTOSC will continue running in both Idle and Sleep.
Important:  If CLKOUTEN is enabled (CLKOUTEN = 0, Configuration Word 1), the output will
continue operating while in Idle.
11.3.1 Idle and Interrupts
IDLE mode ends when an interrupt occurs (even if GIE = 0), but IDLEN is not changed. The device can
re-enter IDLE by executing the SLEEP instruction.
If Recover-On-Interrupt is enabled (ROI = 1), the interrupt that brings the device out of Idle also restores
full-speed CPU execution when doze is also enabled.
11.3.2 Idle and WWDT
When in Idle, the WWDT Reset is blocked and will instead wake the device. The WWDT wake-up is not
an interrupt, therefore ROI does not apply.
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Power-Saving Operation Modes
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 151
Important:  The WWDT can bring the device out of Idle, in the same way it brings the device
out of Sleep. The DOZEN bit is not affected.
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11.4 Register Summary - Power Savings Control
Offset Name Bit Pos.
0x0812 VREGCON 7:0 VREGPM
0x0813
...
0x088B
Reserved
0x088C CPUDOZE 7:0 IDLEN DOZEN ROI DOE DOZE[2:0]
11.5 Register Definitions: Power Savings Control
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11.5.1 VREGCON
Name:  VREGCON
Address:  0x812
Voltage Regulator Control Register
Bit 7 6 5 4 3 2 1 0
VREGPM
Access R/W
Reset 0
Bit 1 – VREGPM Voltage Regulator Power Mode Selection bit
This register is available only for F devices.
Value Description
1 Low-Power Sleep mode enabled in Sleep. Draws lowest current in Sleep, slower wake-up
0 Normal Power mode enabled in Sleep. Draws higher current in Sleep, faster wake-up
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11.5.2 CPUDOZE
Name:  CPUDOZE
Address:  0x88C
Doze and Idle Register
Bit 7 6 5 4 3 2 1 0
IDLEN DOZEN ROI DOE DOZE[2:0]
Access R/W R/W/HC/HS R/W R/W/HC/HS R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – IDLEN Idle Enable bit
Value Description
1 A SLEEP instruction places device into IDLE mode
0 A SLEEP instruction places the device into Sleep mode
Bit 6 – DOZEN  Doze Enable bit(1)
Value Description
1 Places devices into DOZE setting
0 Places devices into Normal mode
Bit 5 – ROI  Recover-On-Interrupt bit(1)
Value Description
1 Entering the Interrupt Service Routine (ISR) makes DOZEN = 0
0 Entering the Interrupt Service Routine (ISR) does not change DOZEN
Bit 4 – DOE  Doze-On-Exit bit(1)
Value Description
1 Executing the ISR makes DOZEN = 1
0 Exiting the ISR does not change DOZEN
Bits 2:0 – DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles
Value Description
111 1:256
110 1:128
101 1:64
100 1:32
011 1:16
010 1:8
001 1:4
000 1:2
Note: 
1. See the link below for more details.
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Power-Saving Operation Modes
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Related Links
Interrupts During Doze
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Power-Saving Operation Modes
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 156
12. (WWDT) Windowed Watchdog Timer
The Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a
CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the
system from unexpected events. The Windowed Watchdog Timer (WWDT) differs in that CLRWDT
instructions are only accepted when they are performed within a specific window during the time-out
period.
The WWDT has the following features:
Selectable clock source
Multiple operating modes
WWDT is always on
WWDT is off when in Sleep
WWDT is controlled by software
WWDT is always off
Configurable time-out period is from 1 ms to 256s (nominal)
Configurable window size from 12.5% to 100% of the time-out period
Multiple Reset conditions
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 157
HVU e
Figure 12-1. Windowed Watchdog Timer Block Diagram
Filename: 10-000162A.vsd
Title: Windowed Watchdog Timer Timer Block Diagram
Last Edit: 1/2/2014
First Used: PIC16(L)F1613 (LECQ)
Notes:
Rev. 10-000 162A
1/2/201 4
WINDOW
CLRWDT
RESET
WDT Time-out
WDT
Window
Violation
PS
5-bit
WDT Counter
Overflow
Latch
18-bit Prescale
Counter
000
011
010
001
100
101
110
111Reserved
Reserved
Reserved
Reserved
Reserved
SOSC
MFINTOSC/16
LFINTOSC
R
R
CS
WWDT
Armed
Window
Sizes Comparator
Window Closed
E
WDTE<1:0> = 01
WDTE<1:0> = 11
WDTE<1:0> = 10
SEN
Sleep
12.1 Independent Clock Source
The WWDT can derive its time base from either the 31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal
oscillators, depending on the value of WDTE Configuration bits.
If WDTE = 'b1x, then the clock source will be enabled depending on the WDTCCS Configuration bits.
If WDTE = 'b01, the SEN bit should be set by software to enable WWDT, and the clock source is
enabled by the WDTCS bits.
Time intervals in this chapter are based on a minimum nominal interval of 1 ms. See “Electrical
Specifications” for LFINTOSC and MFINTOSC tolerances.
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(WWDT) Windowed Watchdog Timer
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 158
Related Links
CONFIG3
Internal Oscillator Parameters(1)
12.2 WWDT Operating Modes
The Windowed Watchdog Timer module has four operating modes controlled by the WDTE bits in
Configuration Words. See Table 12-1.
12.2.1 WWDT Is Always On
When the WDTE bits of Configuration Words are set to ‘11’, the WWDT is always on.
WWDT protection is active during Sleep.
12.2.2 WWDT Is Off in Sleep
When the WDTE bits of Configuration Words are set to ‘10’, the WWDT is on, except in Sleep.
WWDT protection is not active during Sleep.
12.2.3 WWDT Controlled by Software
When the WDTE bits of Configuration Words are set to ‘01’, the WWDT is controlled by the SEN bit.
WWDT protection is unchanged by Sleep. See the following table for more details.
Table 12-1. WWDT Operating Modes
WDTE<1:0> SEN Device Mode WWDT Mode
11 X X Active
10 X Awake Active
Sleep Disabled
01 1 X Active
0 X Disabled
00 X X Disabled
12.3 Time-out Period
If the WDTCPS Configuration bits default to 0’b11111, then the WDTPS bits set the time-out period
from 1 ms to 256 seconds (nominal). If any value other than the default value is assigned to WDTCPS
Configuration bits, then the timer period will be based on the WDTCPS bits in the CONFIG3 register. After
a Reset, the default time-out period is 2s.
Related Links
CONFIG3
12.4 Watchdog Window
The Windowed Watchdog Timer has an optional Windowed mode that is controlled by the WDTCWS
Configuration bits and WINDOW bits. In the Windowed mode, the CLRWDT instruction must occur within
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(WWDT) Windowed Watchdog Timer
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 159
the allowed window of the WDT period. Any CLRWDT instruction that occurs outside of this window will
trigger a window violation and will cause a WWDT Reset, similar to a WWDT time out. See Figure 12-2
for an example.
The window size is controlled by the WINDOW Configuration bits, or the WINDOW bits, if WDTCWS =
111.
The five Most Significant bits of the WDTTMR register are used to determine whether the window is open,
as defined by the WINDOW bits.
In the event of a window violation, a Reset will be generated and the WDTWV bit of the PCON0 register
will be cleared. This bit is set by a POR or can be set in firmware.
Related Links
PCON0
12.5 Clearing the WWDT
The WWDT is cleared when any of the following conditions occur:
Any Reset
Valid CLRWDT instruction is executed
Device enters Sleep
Exit Sleep by Interrupt
WWDT is disabled
Oscillator Start-up Timer (OST) is running
Any write to the WDTCON0 or WDTCON1 registers
12.5.1 CLRWDT Considerations (Windowed Mode)
When in Windowed mode, the WWDT must be armed before a CLRWDT instruction will clear the timer.
This is performed by reading the WDTCON0 register. Executing a CLRWDT instruction without performing
such an arming action will trigger a window violation regardless of whether the window is open or not.
See Table 12-2 for more information.
12.6 Operation During Sleep
When the device enters Sleep, the WWDT is cleared. If the WWDT is enabled during Sleep, the WWDT
resumes counting. When the device exits Sleep, the WWDT is cleared again.
The WWDT remains clear until the Oscillator Start-up Timer (OST) completes, if enabled.
When a WWDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate
the event. The RWDT bit in the PCON0 register can also be used.
Table 12-2. WWDT Clearing Conditions
Conditions WWDT
WDTE = 00 Cleared
WDTE = 01 and SEN = 0
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(WWDT) Windowed Watchdog Timer
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 160
Conditions WWDT
WDTE = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected
Figure 12-2. Window Period and Delay
Filename: 10-000163A.vsd
Title: WDT WINDOW PERIOD AND DELAY
Last Edit: 8/15/2016
First Used: PIC16(L)F1613 (LECQ)
Notes:
Rev. 10-000163A
8/15/2016
Window Period
CLRWDT Instruction
(or other WDT Reset)
Window Delay
(window violation can occur)
Window Closed Window Open
Time-out Event
Related Links
Oscillator Start-up Timer (OST)
STATUS
PCON0
Memory Organization
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 161
12.7 Register Summary - WDT Control
Offset Name Bit Pos.
0x080C WDTCON0 7:0 WDTPS[4:0] SEN
0x080D WDTCON1 7:0 WDTCS[2:0] WINDOW[2:0]
0x080E WDTPSL 7:0 PSCNTL[7:0]
0x080F WDTPSH 7:0 PSCNTH[7:0]
0x0810 WDTTMR 7:0 WDTTMR[4:0] STATE PSCNT[1:0]
12.8 Register Definitions: Windowed Watchdog Timer Control
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 162
23 22 21 20 19 16 17
12.8.1 WDTCON0
Name:  WDTCON0
Address:  0x80C
Watchdog Timer Control Register 0
Bit 7 6 5 4 3 2 1 0
WDTPS[4:0] SEN
Access R/W R/W R/W R/W R/W R/W
Reset q q q q q 0
Bits 5:1 – WDTPS[4:0]  Watchdog Timer Prescale Select bits(1)
Bit Value = Prescale Rate
Value Description
11111 to
10011
Reserved. Results in minimum interval (1 ms)
10010 1:8388608 (223) (Interval 256s nominal)
10001 1:4194304 (222) (Interval 128s nominal)
10000 1:2097152 (221) (Interval 64s nominal)
01111 1:1048576 (220) (Interval 32s nominal)
01110 1:524288 (219) (Interval 16s nominal)
01101 1:262144 (218) (Interval 8s nominal)
01100 1:131072 (217) (Interval 4s nominal)
01011 1:65536 (Interval 2s nominal) (Reset value)
01010 1:32768 (Interval 1s nominal)
01001 1:16384 (Interval 512 ms nominal)
01000 1:8192 (Interval 256 ms nominal)
00111 1:4096 (Interval 128 ms nominal)
00110 1:2048 (Interval 64 ms nominal)
00101 1:1024 (Interval 32 ms nominal)
00100 1:512 (Interval 16 ms nominal)
00011 1:256 (Interval 8 ms nominal)
00010 1:128 (Interval 4 ms nominal)
00001 1:64 (Interval 2 ms nominal)
00000 1:32 (Interval 1 ms nominal)
Bit 0 – SEN Software Enable/Disable for Watchdog Timer bit
Value Condition Description
If WDTE = 1x This bit is ignored
1 If WDTE = 01 WDT is turned on
0 If WDTE = 01 WDT is turned off
If WDTE = 00 This bit is ignored
Note: 
1. Times are approximate. WDT time is based on 31 kHz LFINTOSC.
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2. When WDTCPS in CONFIG3 = 11111, the Reset value (q) of WDTPS is ‘01011’. Otherwise, the
Reset value of WDTPS is equal to WDTCPS in CONFIG3.
3. When WDTCPS in CONFIG3L ≠ 11111, these bits are read-only.
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12.8.2 WDTCON1
Name:  WDTCON1
Address:  0x80D
Watchdog Timer Control Register 1
Bit 7 6 5 4 3 2 1 0
WDTCS[2:0] WINDOW[2:0]
Access R/W R/W R/W R/W R/W R/W
Reset q q q q q q
Bits 6:4 – WDTCS[2:0] Watchdog Timer Clock Select bits
Value Description
111 to
010
Reserved
001 MFINTOSC 31.25 kHz
000 LFINTOSC 31 kHz
Bits 2:0 – WINDOW[2:0] Watchdog Timer Window Select bits
WINDOW Window delay Percent of time Window opening Percent of time
111 N/A 100
110 12.5 87.5
101 25 75
100 37.5 62.5
011 50 50
010 62.5 37.5
001 75 25
000 87.5 12.5
Note: 
1. If WDTCCS in CONFIG3 = 111, the Reset value of WDTCS is ‘000’.
2. The Reset value (q) of WINDOW is determined by the value of WDTCWS in the CONFIG3 register.
3. If WDTCCS in CONFIG3 ≠ 111, these bits are read-only.
4. If WDTCWS in CONFIG3 ≠ 111, these bits are read-only.
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(WWDT) Windowed Watchdog Timer
© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 165
12.8.3 WDTPSH
Name:  WDTPSH
Address:  0x80F
WWDT Prescale Select High Register (Read-Only)
Bit 7 6 5 4 3 2 1 0
PSCNTH[7:0]
Access RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – PSCNTH[7:0]  Prescale Select High Byte bits(1)
Note: 
1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits
of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read
during normal operation.
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12.8.4 WDTPSL
Name:  WDTPSL
Address:  0x80E
WWDT Prescale Select Low Register (Read-Only)
Bit 7 6 5 4 3 2 1 0
PSCNTL[7:0]
Access RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – PSCNTL[7:0]  Prescale Select Low Byte bits(1)
Note: 
1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits
of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read
during normal operation.
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© 2017 Microchip Technology Inc. Datasheet Preliminary DS40001985A-page 167
12.8.5 WDTTMR
Name:  WDTTMR
Address:  0x810
WDT Timer Register (Read-Only)
Bit 7 6 5 4 3 2 1 0
WDTTMR[4:0] STATE PSCNT[1:0]
Access RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0
Bits 7:3 – WDTTMR[4:0] Watchdog Window Value bits
WINDOW WDT Window State Open Percent
Closed Open
111 N/A 00000-11111 100
110 00000-00011 00100-11111 87.5
101 00000-00111 01000-11111 75
100 00000-01011 01100-11111 62.5
011 00000-01111 10000-11111 50
010 00000-10011 10100-11111 37.5
001 00000-10111 11000-11111 25
000 00000-11011 11100-11111 12.5
Bit 2 – STATE WDT Armed Status bit
Value Description
1 WDT is armed
0 WDT is not armed
Bits 1:0 – PSCNT[1:0]  Prescale Select Upper Byte bits(1)
Note: 
1. The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits
of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read
during normal operation.
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13. (NVM) Nonvolatile Memory Control
Nonvolatile Memory (NVM) is separated into two types: Program Flash Memory (PFM) and Data
EEPROM Memory.
NVM is accessible by using both the FSR and INDF registers