EFR32MG12 Family Datasheet by Silicon Labs

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EFR32MG12 Mighty Gecko Multi-Protocol
Wireless SoC Family Data Sheet
The Mighty Gecko multi-protocol family of SoCs is part of the
Wireless Gecko portfolio. Mighty Gecko SoCs are ideal for ena-
bling energy-friendly multi-protocol, multi-band networking for IoT
devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, and no-compromise MCU features.
Mighty Gecko applications include:
KEY FEATURES
32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
Up to 1 MB of flash and 256 kB of RAM
Pin-compatible across EFR32MG families
(exceptions apply for 5V-tolerant pins)
12-channel Peripheral Reflex System,
Low-Energy Sensor Interface & Multi-
channel Capacitive Sense Interface
Autonomous Hardware Crypto Accelerator
and True Random Number Generator
Integrated PA with up to 19 dBm (2.4
GHz) or 20 dBm (Sub-GHz) TX power
Integrated balun for 2.4 GHz
Robust peripheral set and up to 65 GPIO
IoT Multi-Protocol Devices
Connected Home
• Lighting
Health and Wellness
• Metering
Home and Building Automation and Security
Timers and Triggers
Real Time
Counter and
Calendar
Cryotimer
Timer/Counter
Low Energy
Timer
Pulse Counter
Watchdog Timer
Protocol Timer
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports Analog I/F
Lowest power mode with peripheral operational:
USART
Low Energy
UARTTM
I2C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
ADC
VDAC
Analog
Comparator
EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active
Core / Memory
ARM CortexTM M4 processor
with DSP extensions and FPU
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Other
CRYPTO
CRC
Clock Management
High Frequency
Crystal
Oscillator
Low Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
High Frequency
RC Oscillator
Ultra Low
Frequency RC
Oscillator
Auxiliary High
Frequency RC
Oscillator
Flash Program
Memory RAM Memory Debug Interface
with ETM
LDMA
Controller
Memory
Protection Unit
Capacitive Sense
Low Energy
Sensor Interface Op-Amp
IDAC
True Random
Number Generator
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
RFSENSE
MOD
FRC
RAC
Frequency
Synthesizer
PGA
PA
I
Q
RF Frontend
LNA
RFSENSE
PA
I
Q
RF Frontend
LNA
To 2.4 GHz receive
I/Q mixers and PA
To Sub GHz
receive I/Q
mixers and PA
To Sub GHz
and 2.4 GHz PA
Sub GHz
2.4 GHz
BALUN
SMU
silabs.com | Building a more connected world. Rev. 1.4
1. Feature List
The EFR32MG12 highlighted features are listed below.
Low Power Wireless System-on-Chip
High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing
Embedded Trace Macrocell (ETM) for advanced debugging
1024 kB flash program memory
256 kB RAM data memory
2.4 GHz and Sub-GHz radio operation
Transmit power:
2.4 GHz radio: Up to 19 dBm
Sub-GHz radio: Up to 20 dBm
Low Energy Consumption
11 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz
10.0 mA RX current at 1 Mbps, GFSK, 2.4 GHz
8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz
8.5 mA TX current at 0 dBm output power at 2.4 GHz
35.3 mA TX current at 14 dBm output power at 868 MHz
70 μA/MHz in Active Mode (EM0)
1.5 μA EM2 DeepSleep current (16 kB RAM retention and
RTCC running from LFRCO)
High Receiver Performance
-94.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz
-91.3 dBm sensitivity at 2 Mbit/s GFSK, 2.4 GHz
-102.7 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz
-126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz
-120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz
-107.4 dBm sensitivity at 4.8 kbps, OOK, 433 MHz
-112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz
Supported Modulation Formats
2/4 (G)FSK with fully configurable shaping
BPSK / DBPSK TX
OOK / ASK
Shaped OQPSK / (G)MSK
Configurable DSSS and FEC
Supported Protocols
• Zigbee
• Thread
Bluetooth® Low Energy (Bluetooth 5)
Proprietary Protocols
Wireless M-Bus
Selected IEEE 802.15.4g SUN-FSK PHYs
Low Power Wide Area Networks
Suitable for Systems Targeting Compliance With:
FCC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249
ETSI Category I Operation, EN 300 220, EN 300 328
ARIB T-108, T-96
China regulatory
Wide selection of MCU peripherals
12-bit 1 Msps SAR Analog to Digital Converter (ADC)
2 × Analog Comparator (ACMP)
2 × Digital to Analog Converter (VDAC)
3 × Operational Amplifier (Opamp)
Digital to Analog Current Converter (IDAC)
Low-Energy Sensor Interface (LESENSE)
Multi-channel Capacitive Sense Interface (CSEN)
Up to 54 pins connected to analog channels (APORT)
shared between analog peripherals
Up to 65 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
8 Channel DMA Controller
12 Channel Peripheral Reflex System (PRS)
2 × 16-bit Timer/Counter
3 or 4 Compare/Capture/PWM channels
2 × 32-bit Timer/Counter
3 or 4 Compare/Capture/PWM channels
32-bit Real Time Counter and Calendar
16-bit Low Energy Timer for waveform generation
32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
3 × 16-bit Pulse Counter with asynchronous operation
2 × Watchdog Timer with dedicated RC oscillator
4 × Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
Low Energy UART (LEUART)
2 × I2C interface with SMBus support and address recogni-
tion in EM3 Stop
Wide Operating Range
1.8 V to 3.8 V single power supply
Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C)
temperature grades available
Support for Internet Security
General Purpose CRC
True Random Number Generator
2 × Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
QFN48 7x7 mm Package
QFN68 8x8 mm Package
BGA125 7x7 mm Package
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 1.4 | 2
2. Ordering Information
Table 2.1. Ordering Information
Ordering Code
Protocol
Stack
Frequency Band
@ Max TX Power
Flash
(kB)
RAM
(kB) GPIO Package Temp Range
EFR32MG12P433F1024GL125-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
1024 256 65 BGA125 -40 to +85°C
EFR32MG12P433F1024IL125-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
1024 256 65 BGA125 -40 to +125°C
EFR32MG12P433F1024GM68-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
1024 256 46 QFN68 -40 to +85°C
EFR32MG12P433F1024GM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
1024 256 28 QFN48 -40 to +85°C
EFR32MG12P433F1024IM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
1024 256 28 QFN48 -40 to +125°C
EFR32MG12P432F1024GL125-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 1024 256 65 BGA125 -40 to +85°C
EFR32MG12P432F1024GM68-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 1024 256 46 QFN68 -40 to +85°C
EFR32MG12P432F1024GM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 1024 256 31 QFN48 -40 to +85°C
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 1.4 | 3
Ordering Code
Protocol
Stack
Frequency Band
@ Max TX Power
Flash
(kB)
RAM
(kB) GPIO Package Temp Range
EFR32MG12P432F1024IM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 1024 256 31 QFN48 -40 to +125°C
EFR32MG12P431F1024GM68-C Zigbee
Proprietary
Sub-GHz @ 20 dBm 1024 256 46 QFN68 -40 to +85°C
EFR32MG12P431F1024GM48-C Zigbee
Proprietary
Sub-GHz @ 20 dBm 1024 256 31 QFN48 -40 to +85°C
EFR32MG12P332F1024GL125-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 10 dBm 1024 256 65 BGA125 -40 to +85°C
EFR32MG12P332F1024GM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 10 dBm 1024 256 31 QFN48 -40 to +85°C
EFR32MG12P332F1024IM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 10 dBm 1024 256 31 QFN48 -40 to +125°C
EFR32MG12P232F1024GL125-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 1024 128 65 BGA125 -40 to +85°C
EFR32MG12P232F1024GM68-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 1024 128 46 QFN68 -40 to +85°C
EFR32MG12P232F512GM68-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 512 64 46 QFN68 -40 to +85°C
EFR32MG12P232F1024GM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 19 dBm 1024 128 31 QFN48 -40 to +85°C
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 1.4 | 4
Ordering Code
Protocol
Stack
Frequency Band
@ Max TX Power
Flash
(kB)
RAM
(kB) GPIO Package Temp Range
EFR32MG12P231F1024GM68-C Zigbee
Proprietary
Sub-GHz @ 20 dBm 1024 128 46 QFN68 -40 to +85°C
EFR32MG12P231F1024GM48-C Zigbee
Proprietary
Sub-GHz @ 20 dBm 1024 128 31 QFN48 -40 to +85°C
EFR32MG12P132F1024GL125-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 10 dBm 1024 128 65 BGA125 -40 to +85°C
EFR32MG12P132F512GM68-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 10 dBm 512 64 46 QFN68 -40 to +85°C
EFR32MG12P132F1024GM48-C Bluetooth LE
Zigbee
Thread
Proprietary
2.4 GHz @ 10 dBm 1024 128 31 QFN48 -40 to +85°C
EFR32 1 P F G A R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), L (BGA)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
G
X132 1024 L 125
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Performance Grade – P (Performance), B (Basic), V (Value)
Series
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Gecko
2
Device Configuration
Figure 2.1. Ordering Code Key
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 1.4 | 5
Table of Contents
1. Feature List ................................2
2. Ordering Information ............................3
3. System Overview ..............................9
3.1 Introduction ...............................9
3.2 Radio .................................9
3.2.1 Antenna Interface ...........................9
3.2.2 Fractional-N Frequency Synthesizer .....................10
3.2.3 Receiver Architecture ..........................10
3.2.4 Transmitter Architecture .........................10
3.2.5 Wake on Radio ............................10
3.2.6 RFSENSE ..............................11
3.2.7 Flexible Frame Handling .........................11
3.2.8 Packet and State Trace .........................11
3.2.9 Data Buffering.............................11
3.2.10 Radio Controller (RAC) .........................11
3.2.11 Random Number Generator .......................12
3.3 Power .................................13
3.3.1 Energy Management Unit (EMU) ......................13
3.3.2 DC-DC Converter ...........................13
3.3.3 Power Domains ............................13
3.4 General Purpose Input/Output (GPIO) ......................14
3.5 Clocking ................................14
3.5.1 Clock Management Unit (CMU) .......................14
3.5.2 Internal and External Oscillators.......................14
3.6 Counters/Timers and PWM ..........................14
3.6.1 Timer/Counter (TIMER) .........................14
3.6.2 Wide Timer/Counter (WTIMER) .......................14
3.6.3 Real Time Counter and Calendar (RTCC) ...................14
3.6.4 Low Energy Timer (LETIMER) .......................15
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) .................15
3.6.6 Pulse Counter (PCNT) ..........................15
3.6.7 Watchdog Timer (WDOG) .........................15
3.7 Communications and Other Digital Peripherals ...................15
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ..........15
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) ..........15
3.7.3 Inter-Integrated Circuit Interface (I2C) .....................15
3.7.4 Peripheral Reflex System (PRS) ......................15
3.7.5 Low Energy Sensor Interface (LESENSE) ...................16
3.8 Security Features .............................16
3.8.1 General Purpose Cyclic Redundancy Check (GPCRC) ...............16
3.8.2 Crypto Accelerator (CRYPTO) .......................16
3.8.3 True Random Number Generator (TRNG) ...................16
3.8.4 Security Management Unit (SMU) ......................16
silabs.com | Building a more connected world. Rev. 1.4 | 6
3.9 Analog.................................16
3.9.1 Analog Port (APORT) ..........................16
3.9.2 Analog Comparator (ACMP) ........................16
3.9.3 Analog to Digital Converter (ADC) ......................17
3.9.4 Capacitive Sense (CSEN) .........................17
3.9.5 Digital to Analog Current Converter (IDAC) ...................17
3.9.6 Digital to Analog Converter (VDAC) .....................17
3.9.7 Operational Amplifiers ..........................17
3.10 Reset Management Unit (RMU) ........................17
3.11 Core and Memory ............................17
3.11.1 Processor Core ............................17
3.11.2 Memory System Controller (MSC) .....................18
3.11.3 Linked Direct Memory Access Controller (LDMA) ................18
3.12 Memory Map ..............................19
3.13 Configuration Summary ..........................21
4. Electrical Specifications ..........................22
4.1 Electrical Characteristics ..........................22
4.1.1 Absolute Maximum Ratings ........................23
4.1.2 Operating Conditions ..........................25
4.1.3 Thermal Characteristics .........................27
4.1.4 DC-DC Converter ...........................28
4.1.5 Current Consumption ..........................30
4.1.6 Wake Up Times ............................40
4.1.7 Brown Out Detector (BOD) ........................41
4.1.8 Frequency Synthesizer ..........................42
4.1.9 2.4 GHz RF Transceiver Characteristics ....................43
4.1.10 Sub-GHz RF Transceiver Characteristics ...................56
4.1.11 Modem...............................80
4.1.12 Oscillators .............................81
4.1.13 Flash Memory Characteristics .......................85
4.1.14 General-Purpose I/O (GPIO) .......................86
4.1.15 Voltage Monitor (VMON) .........................88
4.1.16 Analog to Digital Converter (ADC) .....................89
4.1.17 Analog Comparator (ACMP) .......................91
4.1.18 Digital to Analog Converter (VDAC) .....................94
4.1.19 Current Digital to Analog Converter (IDAC) ..................97
4.1.20 Capacitive Sense (CSEN) ........................99
4.1.21 Operational Amplifier (OPAMP) .....................101
4.1.22 Pulse Counter (PCNT) ........................104
4.1.23 Analog Port (APORT) .........................104
4.1.24 I2C ...............................105
4.1.25 USART SPI ............................108
4.2 Typical Performance Curves ........................109
4.2.1 Supply Current ...........................110
4.2.2 DC-DC Converter ..........................115
4.2.3 2.4 GHz Radio ...........................117
silabs.com | Building a more connected world. Rev. 1.4 | 7
5. Typical Connection Diagrams ........................119
5.1 Power ................................119
5.2 RF Matching Networks ..........................121
5.3 Other Connections............................122
6. Pin Definitions ..............................123
6.1 BGA125 2.4 GHz and Sub-GHz Device Pinout ..................123
6.2 BGA125 2.4 GHz Device Pinout .......................127
6.3 QFN68 2.4 GHz and Sub-GHz Device Pinout...................130
6.4 QFN68 2.4 GHz Device Pinout .......................133
6.5 QFN68 Sub-GHz Device Pinout .......................135
6.6 QFN48 2.4 GHz and Sub-GHz Device Pinout...................137
6.7 QFN48 2.4 GHz Device Pinout .......................139
6.8 QFN48 Sub-GHz Device Pinout .......................141
6.9 GPIO Functionality Table .........................143
6.10 Alternate Functionality Overview ......................186
6.11 Analog Port (APORT) Client Maps ......................201
7. BGA125 Package Specifications .......................210
7.1 BGA125 Package Dimensions ........................210
7.2 BGA125 PCB Land Pattern .........................212
7.3 BGA125 Package Marking .........................214
8. QFN48 Package Specifications........................215
8.1 QFN48 Package Dimensions ........................215
8.2 QFN48 PCB Land Pattern .........................217
8.3 QFN48 Package Marking .........................219
9. QFN68 Package Specifications........................220
9.1 QFN68 Package Dimensions ........................220
9.2 QFN68 PCB Land Pattern .........................222
9.3 QFN68 Package Marking .........................224
10. Revision History.............................225
silabs.com | Building a more connected world. Rev. 1.4 | 8
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3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG12 Wireless
Gecko Reference Manual.
A block diagram of the EFR32MG12 family is shown in Figure 3.1 Detailed EFR32MG12 Block Diagram on page 9. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Analog Peripherals
Clock Management
HFRCO
IDAC
ARM Cortex-M4 Core
Up to 1024 KB ISP Flash
Program Memory
Up to 256 KB RAM A
H
B
Watchdog
Timer
RESETn
Digital Peripherals
Input Mux
Port
Mapper
Port I/O Configuration
Analog Comparator
12-bit ADC
Temp
Sense
VDD
Internal
Reference
IOVDD
AUXHFRCO
LFXO
ULFRCO
HFXO
Memory Protection Unit
LFRCO
A
P
B
LDMA Controller
+
-
APORT
Floating Point Unit
Energy Management
DVDD
VREGVDD
VREGSW
bypass
AVDD
PAVDD
RFVDD
DECOUPLE
IOVDD
Voltage
Monitor
Radio Transceiver
2G4RF_IOP
2G4RF_ION
2.4 GHz RF
PA
I
Q
LNA Frequency
Synthesizer
DEMOD
AGC
IFADC
CRC
BUFC
MOD
FRC
RAC
PGA
SUBGRF_OP
SUBGRF_ON
Sub-GHz RF
I
Q
PA
SUBGRF_IP
SUBGRF_IN LNA
To RF
Frontend
Circuits
BALUN
RFSENSE
VDAC
+
-
Op-Amp
Capacitive
Sense
LESENSE
CRC
CRYPTO
I2C
LEUART
USART
RTC / RTCC
PCNT
CRYOTIMER
TIMER
LETIMER
Port K
Drivers PKn
Port J
Drivers PJn
Port I
Drivers PIn
Port F
Drivers PFn
Port D
Drivers PDn
Port C
Drivers PCn
Port B
Drivers PBn
Port A
Drivers PAn
Mux & FB
HFXTAL_P
HFXTAL_N
LFXTAL_P
LFXTAL_N
Voltage
Regulator
DC-DC
Converter
Debug Signals
(shared w/GPIO)
Brown Out /
Power-On
Reset
Reset
Management
Unit
Serial Wire
and ETM
Debug /
Programming
Figure 3.1. Detailed EFR32MG12 Block Diagram
3.2 Radio
The Mighty Gecko family features a highly configurable radio transceiver supporting a wide range of wireless protocols, including Zig-
bee, Thread, BLE and proprietary.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.4 | 9
3.2.2 Fractional-N Frequency Synthesizer
The EFR32MG12 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32MG12 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) block adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity
and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz radio
can be calibrated on-demand by the user for the desired frequency band.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32MG12 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multi-
path propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and
sub-GHz bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF re-
ceive detection operations.
Note: Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.
3.2.4 Transmitter Architecture
The EFR32MG12 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32MG12. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32MG12 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-
als.
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.4 | 10
3.2.6 RFSENSE
The RFSENSE peripheral generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, provid-
ing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
3.2.7 Flexible Frame Handling
EFR32MG12 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-
tor:
Highly adjustable preamble length
Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
Frame disassembly and address matching (filtering) to accept or reject frames
Automatic ACK frame assembly and transmission
Fully flexible CRC generation and verification:
Multiple CRC values can be embedded in a single frame
8, 16, 24 or 32-bit CRC value
Configurable CRC bit and byte ordering
Selectable bit-ordering (least significant or most significant bit first)
Optional data whitening
Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
Optional symbol interleaving, typically used in combination with FEC
Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
UART encoding over air, with start and stop bit insertion / removal
Test mode support, such as modulated or unmodulated carrier output
Received frame timestamping
3.2.8 Packet and State Trace
The EFR32MG12 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:
Non-intrusive trace of transmit data, receive data and state information
Data observability on a single-pin UART data output, or on a two-pin SPI data output
Configurable data output bitrate / baudrate
Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32MG12 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32MG12. It performs the following tasks:
Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
Run-time calibration of receiver, transmitter and frequency synthesizer
Detailed frame transmission timing, including optional LBT or CSMA-CA
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3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
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3.3 Power
The EFR32MG12 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-
tor.
The EFR32MG12 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-
ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.3.3 Power Domains
The EFR32MG12 has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power do-
main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-
rent consumption of the device.
Table 3.1. Peripheral Power Subdomains
Peripheral Power Domain 1 Peripheral Power Domain 2
ACMP0 ACMP1
PCNT0 PCNT1
ADC0 PCNT2
LETIMER0 CSEN
LESENSE DAC0
APORT LEUART0
- I2C0
- I2C1
- IDAC
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3.4 General Purpose Input/Output (GPIO)
EFR32MG12 has up to 65 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or
input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-
als. The GPIO subsystem supports asynchronous external pin interrupts.
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32MG12. Individual enabling and disabling of clocks to all periph-
erals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows
software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscilla-
tors.
3.5.2 Internal and External Oscillators
The EFR32MG12 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.
An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Wide Timer/Counter (WTIMER)
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-
old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.6.3 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes down to EM4H.
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3.6.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.6 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,
EM2 Deep Sleep, and EM3 Stop.
3.6.7 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
ISO7816 SmartCards
• IrDA
I2S
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave
and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates
from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.
The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated
transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripher-
als producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in
turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied
by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
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3.7.5 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura-
ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.
3.8 Security Features
3.8.1 General Purpose Cyclic Redundancy Check (GPCRC)
The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The suppor-
ted 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on
data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.
CRYPTO also provides trigger signals for DMA read and write operations.
3.8.3 True Random Number Generator (TRNG)
The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22
and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).
3.8.4 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Capacitive Sense (CSEN)
The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a
switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in
adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin
or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the
combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an aver-
aging filter, as well as digital threshold comparators to reduce software overhead.
3.9.5 Digital to Analog Current Converter (IDAC)
The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC
input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of
various step sizes.
3.9.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-
ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.9.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to
rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB
space, and cost as compared with standalone opamps because they are integrated on-chip.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32MG12. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
Memory Protection Unit (MPU) supporting up to 8 memory segments
Up to 1024 kB flash program memory
Up to 256 kB RAM data memory
Configuration and event handling of all peripherals
2-pin Serial-Wire debug interface
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3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.
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3.12 Memory Map
The EFR32MG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32MG12 Memory Map — Core Peripherals and Code Space
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Figure 3.3. EFR32MG12 Memory Map — Peripherals
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3.13 Configuration Summary
The features of the EFR32MG12 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.2. Configuration Summary
Module Configuration Pin Connections
USART0 IrDA
SmartCard
US0_TX, US0_RX, US0_CLK, US0_CS
USART1 I2S
SmartCard
US1_TX, US1_RX, US1_CLK, US1_CS
USART2 IrDA
SmartCard
US2_TX, US2_RX, US2_CLK, US2_CS
USART3 I2S
SmartCard
US3_TX, US3_RX, US3_CLK, US3_CS
TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 - TIM1_CC[3:0]
WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]
WTIMER1 - WTIM1_CC[3:0]
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4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.
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4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range TSTG -50 150 °C
Voltage on any supply pin VDDMAX -0.3 3.8 V
Voltage ramp rate on any
supply pin
VDDRAMPMAX 1 V / µs
DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1 2 3-0.3 Min of 5.25
and IOVDD
+2
V
Standard GPIO pins -0.3 IOVDD+0.3 V
Voltage on HFXO pins VHFXOPIN -0.3 1.4 V
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
PRFMAX2G4 10 dBm
Voltage differential between
RF pins (2G4RF_IOP -
2G4RF_ION)
VMAXDIFF2G4 -50 50 mV
Absolute voltage on RF pins
2G4RF_IOP and
2G4RF_ION
VMAX2G4 -0.3 3.3 V
Absolute voltage on Sub-
GHz RF pins
VMAXSUBG Pins SUBGRF_OP and
SUBGRF_ON
-0.3 3.3 V
Pins SUBGRF_IP and
SUBGRF_IN,
-0.3 0.3 V
Total current into VDD power
lines
IVDDMAX Source 200 mA
Total current into VSS
ground lines
IVSSMAX Sink 200 mA
Current per I/O pin IIOMAX Sink 50 mA
Source 50 mA
Current for all I/O pins IIOALLMAX Sink 200 mA
Source 200 mA
Junction temperature TJ-G grade devices -40 105 °C
-I grade devices -40 125 °C
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the
maximum IO current specifications.
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.
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4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.
VREGVDD = AVDD
DVDD ≤ AVDD
IOVDD ≤ AVDD
RFVDD ≤ AVDD
PAVDD ≤ AVDD
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4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Operating ambient tempera-
ture range1
TA-G temperature grade -40 25 85 °C
-I temperature grade -40 25 125 °C
AVDD supply voltage2VAVDD 1.8 3.3 3.8 V
VREGVDD operating supply
voltage2 3
VVREGVDD DCDC in regulation 2.4 3.3 3.8 V
DCDC in bypass, 50mA load 1.8 3.3 3.8 V
DCDC not in use. DVDD external-
ly shorted to VREGVDD
1.8 3.3 3.8 V
VREGVDD current IVREGVDD DCDC in bypass, T ≤ 85 °C 200 mA
DCDC in bypass, T > 85 °C 100 mA
RFVDD operating supply
voltage
VRFVDD 1.62 — VVREGVDD V
DVDD operating supply volt-
age
VDVDD 1.62 — VVREGVDD V
PAVDD operating supply
voltage
VPAVDD 1.62 — VVREGVDD V
IOVDD operating supply volt-
age
VIOVDD All IOVDD pins41.62 — VVREGVDD V
DECOUPLE output capaci-
tor5 6
CDECOUPLE 0.75 1.0 2.75 µF
Difference between AVDD
and VREGVDD, ABS(AVDD-
VREGVDD)2
dVDD 0.1 V
HFCORECLK frequency fCORE VSCALE2, MODE = WS1 40 MHz
VSCALE2, MODE = WS0 25 MHz
VSCALE0, MODE = WS2 20 MHz
VSCALE0, MODE = WS1 14 MHz
VSCALE0, MODE = WS0 7 MHz
HFCLK frequency fHFCLK VSCALE2 40 MHz
VSCALE0 20 MHz
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Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific appli-
cation. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Characteristics table for TJ and THETAJA.
2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.
4. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.
5. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-
ue stays within the specified bounds across temperature and DC bias.
6. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi-
tion, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70
mA (with a 2.7 µF capacitor).
4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Thermal resistance, QFN48
Package
THETAJA_QFN48 2-Layer PCB, Air velocity = 0 m/s 75.7 °C/W
2-Layer PCB, Air velocity = 1 m/s 61.5 °C/W
2-Layer PCB, Air velocity = 2 m/s 55.4 °C/W
4-Layer PCB, Air velocity = 0 m/s 30.2 °C/W
4-Layer PCB, Air velocity = 1 m/s 26.3 °C/W
4-Layer PCB, Air velocity = 2 m/s 24.9 °C/W
Thermal resistance, BGA125
Package
THE-
TAJA_BGA125
2-Layer PCB, Air velocity = 0 m/s 90.7 °C/W
2-Layer PCB, Air velocity = 1 m/s 73.7 °C/W
2-Layer PCB, Air velocity = 2 m/s 66.4 °C/W
4-Layer PCB, Air velocity = 0 m/s 45 °C/W
4-Layer PCB, Air velocity = 1 m/s 39.6 °C/W
4-Layer PCB, Air velocity = 2 m/s 37.6 °C/W
Thermal resistance, QFN68
Package
THETAJA_QFN68 4-Layer PCB, Air velocity = 0 m/s 21.5 °C/W
4-Layer PCB, Air velocity = 1 m/s 18.9 °C/W
4-Layer PCB, Air velocity = 2 m/s 17.1 °C/W
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Electrical Specifications
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4.1.4 DC-DC Converter
Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50
mA
1.8 — VVREGVDD_
MAX
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
2.4 — VVREGVDD_
MAX
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 200 mA
2.6 — VVREGVDD_
MAX
V
Output voltage programma-
ble range1
VDCDC_O 1.8 — VVREGVDD V
Regulation DC accuracy ACCDC Low Noise (LN) mode, 1.8 V tar-
get output
1.7 1.9 V
Regulation window2WINREG Low Power (LP) mode,
LPCMPBIASEMxx3 = 0, 1.8 V tar-
get output, IDCDC_LOAD ≤ 75 µA
1.63 2.2 V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 3, 1.8 V tar-
get output, IDCDC_LOAD ≤ 10 mA
1.63 2.1 V
Steady-state output ripple VRRadio disabled 3 mVpp
Output voltage under/over-
shoot
VOV CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
25 60 mV
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
45 90 mV
Overshoot during LP to LN
CCM/DCM mode transitions com-
pared to DC level in LN mode
200 — mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
40 — mV
Undershoot during BYP/LP to LN
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
100 — mV
DC line regulation VREG Input changes between
VVREGVDD_MAX and 2.4 V
0.1 — %
DC load regulation IREG Load changes between 0 mA and
100 mA in CCM mode
0.1 — %
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Parameter Symbol Test Condition Min Typ Max Unit
Max load current ILOAD_MAX Low noise (LN) mode, Heavy
Drive4, T ≤ 85 °C
200 mA
Low noise (LN) mode, Heavy
Drive4, T > 85 °C
100 mA
Low noise (LN) mode, Medium
Drive4
100 mA
Low noise (LN) mode, Light
Drive4
50 mA
Low power (LP) mode,
LPCMPBIASEMxx3 = 0
75 µA
Low power (LP) mode,
LPCMPBIASEMxx3 = 3
10 mA
DCDC nominal output ca-
pacitor5
CDCDC 25% tolerance 1 4.7 4.7 µF
DCDC nominal output induc-
tor
LDCDC 20% tolerance 4.7 4.7 4.7 µH
Resistance in Bypass mode RBYP 1.2 2.5 Ω
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.
2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL
must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.
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4.1.5 Current Consumption
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.5. Current Consumption 3.3 V without DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
mode with all peripherals dis-
abled
IACTIVE 38.4 MHz crystal, CPU running
while loop from flash1
130 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
99 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
99 105 µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
124 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
102 108 µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
280 435 µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled and voltage scaling
enabled
IACTIVE_VS 19 MHz HFRCO, CPU running
while loop from flash
88 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
234 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled
IEM1 38.4 MHz crystal1 80 — µA/MHz
38 MHz HFRCO 50 54 µA/MHz
26 MHz HFRCO 52 58 µA/MHz
1 MHz HFRCO 230 400 µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled and voltage scaling
enabled
IEM1_VS 19 MHz HFRCO 47 µA/MHz
1 MHz HFRCO 193 µA/MHz
Current consumption in EM2
mode, with voltage scaling
enabled
IEM2_VS Full 256 kB RAM retention and
RTCC running from LFXO
2.9 — µA
Full 256 kB RAM retention and
RTCC running from LFRCO
3.2 — µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO2
2.1 3.5 µA
Current consumption in EM3
mode, with voltage scaling
enabled
IEM3_VS Full 256 kB RAM retention and
CRYOTIMER running from ULFR-
CO
2.56 4.8 µA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS 128 byte RAM retention, RTCC
running from LFXO
1.0 — µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
0.45 — µA
128 byte RAM retention, no RTCC 0.43 0.9 µA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
EM4S mode
IEM4S No RAM retention, no RTCC 0.04 0.1 µA
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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4.1.5.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.6. Current Consumption 3.3 V using DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
mode with all peripherals dis-
abled, DCDC in Low Noise
DCM mode1
IACTIVE_DCM 38.4 MHz crystal, CPU running
while loop from flash2
88 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
70 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
70 — µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
85 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
77 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
636 — µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled, DCDC in Low Noise
CCM mode3
IACTIVE_CCM 38.4 MHz crystal, CPU running
while loop from flash2
98 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
81 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
82 — µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
95 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
95 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
1155 — µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled and voltage scaling
enabled, DCDC in Low
Noise CCM mode3
IACTIVE_CCM_VS 19 MHz HFRCO, CPU running
while loop from flash
101 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
1128 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled, DCDC in Low Noise
DCM mode1
IEM1_DCM 38.4 MHz crystal2 59 — µA/MHz
38 MHz HFRCO 41 µA/MHz
26 MHz HFRCO 48 µA/MHz
1 MHz HFRCO 610 µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled and voltage scaling
enabled, DCDC in Low
Noise DCM mode1
IEM1_DCM_VS 19 MHz HFRCO 52 µA/MHz
1 MHz HFRCO 587 µA/MHz
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM2
mode, with voltage scaling
enabled, DCDC in LP mode4
IEM2_VS Full 256 kB RAM retention and
RTCC running from LFXO
2.1 — µA
Full 256 kB RAM retention and
RTCC running from LFRCO
2.2 — µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO5
1.5 — µA
Current consumption in EM3
mode, with voltage scaling
enabled
IEM3_VS Full 256 kB RAM retention and
CRYOTIMER running from ULFR-
CO
1.81 — µA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS 128 byte RAM retention, RTCC
running from LFXO
0.69 — µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
0.39 — µA
128 byte RAM retention, no RTCC 0.39 µA
Current consumption in
EM4S mode
IEM4S No RAM retention, no RTCC 0.06 µA
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
2. CMU_HFXOCTRL_LOWPOWER=0.
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
4. DCDC Low Power Mode = Medium Drive, LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.
5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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4.1.5.3 Current Consumption 1.8 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.7. Current Consumption 1.8 V without DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
mode with all peripherals dis-
abled
IACTIVE 38.4 MHz crystal, CPU running
while loop from flash1
130 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
99 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
99 — µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
124 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
102 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
277 — µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled and voltage scaling
enabled
IACTIVE_VS 19 MHz HFRCO, CPU running
while loop from flash
87 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
231 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled
IEM1 38.4 MHz crystal1 80 — µA/MHz
38 MHz HFRCO 50 µA/MHz
26 MHz HFRCO 52 µA/MHz
1 MHz HFRCO 227 µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled and voltage scaling
enabled
IEM1_VS 19 MHz HFRCO 47 µA/MHz
1 MHz HFRCO 190 µA/MHz
Current consumption in EM2
mode, with voltage scaling
enabled
IEM2_VS Full 256 kB RAM retention and
RTCC running from LFXO
2.8 — µA
Full 256 kB RAM retention and
RTCC running from LFRCO
3.0 — µA
16 kB (1 bank) RAM retention and
RTCC running from LFRCO2
1.9 — µA
Current consumption in EM3
mode, with voltage scaling
enabled
IEM3_VS Full 256 kB RAM retention and
CRYOTIMER running from ULFR-
CO
2.47 — µA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS 128 byte RAM retention, RTCC
running from LFXO
0.91 — µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
0.35 — µA
128 byte RAM retention, no RTCC 0.35 µA
Current consumption in
EM4S mode
IEM4S No RAM retention, no RTCC 0.04 µA
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25
°C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T ≤ 85 °C
IRX_ACTIVE 500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
9.3 10.2 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
8.6 10.2 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
8.6 10.2 mA
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
8.6 10.2 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
8.6 10.2 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
8.4 10.2 mA
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
10.0 — mA
2 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
11.5 — mA
802.15.4 receiving frame, F = 2.4
GHz, Radio clock prescaled by 3
11 — mA
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T > 85 °C
IRX_ACTIVE_HT 500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
13 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
13 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
13 mA
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
13 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
13 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
13 mA
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Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in re-
ceive mode, listening for
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disa-
bled), T ≤ 85 °C
IRX_LISTEN 500 kbit/s, 2GFSK, F = 915 MHz,
No radio clock prescaling
10.2 11 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
No radio clock prescaling
9.5 11 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
No radio clock prescaling
9.5 11 mA
50 kbit/s, 2GFSK, F = 433 MHz,
No radio clock prescaling
9.5 11 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
No radio clock prescaling
9.4 11 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
No radio clock prescaling
9.3 11 mA
1 Mbit/s, 2GFSK, F = 2.4 GHz, No
radio clock prescaling
10.9 — mA
2 Mbit/s, 2GFSK, F = 2.4 GHz, No
radio clock prescaling
11.9 — mA
802.15.4, F = 2.4 GHz, No radio
clock prescaling
12.5 — mA
Current consumption in re-
ceive mode, listening for
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disa-
bled), T > 85 °C
IRX_LISTEN_HT 500 kbit/s, 2GFSK, F = 915 MHz,
No radio clock prescaling
14 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
No radio clock prescaling
14 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
No radio clock prescaling
14 mA
50 kbit/s, 2GFSK, F = 433 MHz,
No radio clock prescaling
14 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
No radio clock prescaling
14 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
No radio clock prescaling
14 mA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T ≤ 85 °C
ITX F = 915 MHz, CW, 20 dBm
match, External PA supply = 3.3V
90.2 134.3 mA
F = 915 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
36 42.5 mA
F = 868 MHz, CW, 20 dBm
match, External PA supply = 3.3V
79.7 106.7 mA
F = 868 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
35.3 41 mA
F = 490 MHz, CW, 20 dBm
match, External PA supply = 3.3V
93.8 125.4 mA
F = 433 MHz, CW, 10 dBm
match, External PA supply con-
nected to DC-DC output
20.3 24 mA
F = 433 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
34 41.5 mA
F = 315 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
33.5 42 mA
F = 169 MHz, CW, 20 dBm
match, External PA supply = 3.3V
88.6 116.7 mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 3
8.5 — mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 1
9.5 — mA
F = 2.4 GHz, CW, 3 dBm output
power
16.5 — mA
F = 2.4 GHz, CW, 8 dBm output
power
26 — mA
F = 2.4 GHz, CW, 10.5 dBm out-
put power
34 — mA
F = 2.4 GHz, CW, 16.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
86 — mA
F = 2.4 GHz, CW, 19.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
131 — mA
EFR32MG12 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T > 85 °C
ITX_HT F = 915 MHz, CW, 20 dBm
match, External PA supply = 3.3V
134.3 mA
F = 915 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
42.5 mA
F = 868 MHz, CW, 20 dBm
match, External PA supply = 3.3V
109.8 mA
F = 868 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
41.3 mA
F = 490 MHz, CW, 20 dBm
match, External PA supply = 3.3V
130.8 mA
F = 433 MHz, CW, 10 dBm
match, External PA supply con-
nected to DC-DC output
24.4 mA
F = 433 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
41.5 mA
F = 315 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
42 mA
F = 169 MHz, CW, 20 dBm
match, External PA supply = 3.3V
122.8 mA
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4.1.6 Wake Up Times
Table 4.9. Wake Up Times
Parameter Symbol Test Condition Min Typ Max Unit
Wake up time from EM1 tEM1_WU 3 — AHB
Clocks
Wake up from EM2 tEM2_WU Code execution from flash 10.1 µs
Code execution from RAM 3.2 µs
Wake up from EM3 tEM3_WU Code execution from flash 10.1 µs
Code execution from RAM 3.2 µs
Wake up from EM4H1tEM4H_WU Executing from flash 80 µs
Wake up from EM4S1tEM4S_WU Executing from flash 291 µs
Time from release of reset
source to first instruction ex-
ecution
tRESET Soft Pin Reset released 43 µs
Any other reset released 350 µs
Power mode scaling time tSCALE VSCALE0 to VSCALE2, HFCLK =
19 MHz2 3
31.8 — µs
VSCALE2 to VSCALE0, HFCLK =
19 MHz4
4.3 — µs
Note:
1. Time from wake up request until first instruction is executed. Wakeup results in device reset.
2. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.
3. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA
(with a 2.7 µF capacitor).
4. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.
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4.1.7 Brown Out Detector (BOD)
Table 4.10. Brown Out Detector (BOD)
Parameter Symbol Test Condition Min Typ Max Unit
DVDD BOD threshold VDVDDBOD DVDD rising 1.62 V
DVDD falling (EM0/EM1) 1.35 V
DVDD falling (EM2/EM3) 1.3 V
DVDD BOD hysteresis VDVDDBOD_HYST 18 — mV
DVDD BOD response time tDVDDBOD_DELAY Supply drops at 0.1V/µs rate 2.4 µs
AVDD BOD threshold VAVDDBOD AVDD rising 1.8 V
AVDD falling (EM0/EM1) 1.62 V
AVDD falling (EM2/EM3) 1.53 V
AVDD BOD hysteresis VAVDDBOD_HYST 20 — mV
AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/µs rate 2.4 µs
EM4 BOD threshold VEM4DBOD AVDD rising 1.7 V
AVDD falling 1.45 V
EM4 BOD hysteresis VEM4BOD_HYST 25 — mV
EM4 BOD response time tEM4BOD_DELAY Supply drops at 0.1V/µs rate 300 µs
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4.1.8 Frequency Synthesizer
Table 4.11. Frequency Synthesizer
Parameter Symbol Test Condition Min Typ Max Unit
RF synthesizer frequency
range
fRANGE 2400 - 2483.5 MHz 2400 2483.5 MHz
779 - 956 MHz 779 956 MHz
584 - 717 MHz 584 717 MHz
358 - 574 MHz 358 574 MHz
191 - 358 MHz 191 358 MHz
110 - 191 MHz 110 191 MHz
LO tuning frequency resolu-
tion with 38.4 MHz crystal
fRES 2400 - 2483.5 MHz 73 Hz
779 - 956 MHz 24 Hz
584 - 717 MHz 18.3 Hz
358 - 574 MHz 12.2 Hz
191 - 358 MHz 7.3 Hz
110 - 191 MHz 4.6 Hz
Frequency deviation resolu-
tion with 38.4 MHz crystal
dfRES 2400 - 2483.5 MHz 73 Hz
779 - 956 MHz 24 Hz
584 - 717 MHz 18.3 Hz
358 - 574 MHz 12.2 Hz
191 - 358 MHz 7.3 Hz
110 - 191 MHz 4.6 Hz
Maximum frequency devia-
tion with 38.4 MHz crystal
dfMAX 2400 - 2483.5 MHz 1677 kHz
779 - 956 MHz 559 kHz
584 - 717 MHz 419 kHz
358 - 574 MHz 280 kHz
191 - 358 MHz 167 kHz
110 - 191 MHz 105 kHz
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4.1.9 2.4 GHz RF Transceiver Characteristics
4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Maximum TX power1POUTMAX 19 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
19.5 — dBm
10 dBm-rated part numbers 10.5 dBm
Minimum active TX Power POUTMIN CW -30 — dBm
Output power step size POUTSTEP -5 dBm< Output power < 0 dBm 1 dB
0 dBm < output power <
POUTMAX
0.5 — dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power >
10 dBm.
4.5 — dB
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power =
10 dBm.
3.8 — dB
1.8 V < VVREGVDD < 3.3 V using
DC-DC converter
2.2 — dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T From -40 to +85 °C, PAVDD con-
nected to DC-DC output
1.5 — dB
From -40 to +125 °C, PAVDD
connected to DC-DC output
2.2 — dB
From -40 to +85 °C, PAVDD con-
nected to external supply
1.5 — dB
From -40 to +125 °C, PAVDD
connected to external supply
3.4 — dB
Output power variation vs RF
frequency at POUTMAX
POUTVAR_F Over RF tuning frequency range 0.4 dB
RF tuning frequency range FRANGE 2400 2483.5 MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 2400 2483.5 MHz
Receive mode maximum
spurious emission
SPURRX 30 MHz to 1 GHz -57 dBm
1 GHz to 12 GHz -47 dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216 MHz to 960 MHz, Conducted
Measurement
-55.2 — dBm
Above 960 MHz, Conducted
Measurement
-47.2 — dBm
Level above which
RFSENSE will trigger1
RFSENSETRIG CW at 2.45 GHz -24 dBm
Level below which
RFSENSE will not trigger1
RFSENSETHRES CW at 2.45 GHz -50 dBm
1% PER sensitivity SENS2GFSK 2 Mbps 2GFSK signal -89.6 dBm
250 kbps 2GFSK signal -100.7 dBm
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.9.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.14. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Transmit 6dB bandwidth TXBW 10 dBm 781 kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm -8.4 dBm/
3kHz
Per FCC part 15.247 at 20 dBm -0.4 dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
10.1 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band, 10 dBm
1.1 — MHz
In-band spurious emissions,
with allowed exceptions1
SPURINB At ± 2 MHz, 10 dBm -39.5 dBm
At ± 3 MHz, 10 dBm -44.7 dBm
At ± 2 MHz, 20 dBm -20 dBm
At ± 3 MHz, 20 dBm -30 dBm
Emissions of harmonics out-
of-band, per FCC part
15.247
SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modu-
lated carrier
-47 — dBm
Spurious emissions out-of-
band, excluding harmonics
captured in SPURHARM,FCC.
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply
SPUROOB_FCC Per FCC part 15.205/15.209,
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Restricted Bands2 3
-47 — dBm
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
-26 — dBc
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328 [2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
-16 — dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
-26 — dBm
Spurious emissions per ETSI
EN300.440
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
-60 — dBm
25-1000 MHz -42 dBm
1-12 GHz -36 dBm
Note:
1. Per Bluetooth Core_5.0, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
2. For 2476 MHz, 1.5 dB of power backoff is used to achieve this value.
3. For 2478 MHz, 4.2 dB of power backoff is used to achieve this value.
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4.1.9.4 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz.
Table 4.15. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 0.1% BER
SAT Signal is reference signal1. Packet
length is 20 bytes.
10 — dBm
Sensitivity, 0.1% BER SENS Signal is reference signal1. Using
DC-DC converter.
-94.8 — dBm
With non-ideal signals as speci-
fied in RF-PHY.TS.4.2.2, section
4.6.1.
-94.4 — dBm
Signal to co-channel interfer-
er, 0.1% BER
C/ICC Desired signal 3 dB above refer-
ence sensitivity.
10.3 — dB
N+1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1+ Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-1.8 — dB
N-1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1- Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-0.7 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I2Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz,
QFN48 and BGA125 packages.
-40.6 — dB
Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz,
QFN68 package.
-34.1 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I3Interferer is reference signal at ± 3
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
-46.2 — dB
Selectivity to image frequen-
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
C/IIM Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
-38.1 — dB
Selectivity to image frequen-
cy ± 1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
C/IIM+1 Interferer is reference signal at im-
age frequency ± 1 MHz with 1
MHz precision
-46.5 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Blocking, less than 0.1%
BER. Desired is -67dBm
BLE reference signal at
2426MHz. Interferer is CW in
OOB range2
BLOCKOOB Interferer frequency 30 MHz ≤ f ≤
2000 MHz
-5 — dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
-24 — dBm
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
-10 — dBm
Interferer frequency 3 GHz ≤ f ≤ 6
GHz
-10 — dBm
Interferer frequency 6 GHz ≤ f ≤
12.75 GHz
-17 — dBm
Intermodulation performance IM Per Core_4.1, Vol 6, Part A, Sec-
tion 4.4 with n = 3
-23.7 — dBm
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
2. Interferer max power limited by equipment capabilities and path loss. Minimum specified at 25 °C.
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4.1.9.5 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.16. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 2 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Transmit 6dB bandwidth TXBW 10 dBm 1404 kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm -12.3 dBm/
3kHz
Per FCC part 15.247 at 20 dBm -4.0 dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
11.3 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band, 10 dBm
2.1 — MHz
In-band spurious emissions,
with allowed exceptions1
SPURINB At ± 4 MHz, 10 dBm -40.3 dBm
At ± 6 MHz, 10 dBm -43.6 dBm
At ± 4 MHz, 20 dBm -32.3 dBm
At ± 6 MHz, 20 dBm -35.6 dBm
Emissions of harmonics out-
of-band, per FCC part
15.247
SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modu-
lated carrier
-47 — dBm
Spurious emissions out-of-
band, excluding harmonics
captured in SPURHARM,FCC.
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply
SPUROOB_FCC Per FCC part 15.205/15.209,
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Restricted Bands2 3 4
5
-47 — dBm
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
-26 — dBc
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328 [2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
-16 — dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
-26 — dBm
Spurious emissions per ETSI
EN300.440
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
-60 — dBm
25-1000 MHz -42 dBm
1-12 GHz -36 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Per Bluetooth Core_5.0, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
2. For 2472 MHz, 1.3 dB of power backoff is used to achieve this value.
3. For 2474 MHz, 3.8 dB of power backoff is used to achieve this value.
4. For 2476 MHz, 7 dB of power backoff is used to achieve this value.
5. For 2478 MHz, 11.2 dB of power backoff is used to achieve this value.
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4.1.9.6 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz1.
Table 4.17. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 2 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 0.1% BER
SAT Signal is reference signal2. Packet
length is 20 bytes.
10 — dBm
Sensitivity, 0.1% BER SENS Signal is reference signal2. Using
DC-DC converter. QFN48 and
BGA125 packages.
-91.3 — dBm
With non-ideal signals as speci-
fied in RF-PHY.TS.4.2.2, section
4.6.1. QFN48 and BGA125 pack-
ages.
-91 — dBm
Signal is reference signal2. Using
DC-DC converter. QFN68 pack-
age.
-91.3 — dBm
With non-ideal signals as speci-
fied in RF-PHY.TS.4.2.2, section
4.6.1. QFN68 package.
-90.1 — dBm
Signal to co-channel interfer-
er, 0.1% BER
C/ICC Desired signal 3 dB above refer-
ence sensitivity.
7.3 — dB
N+1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1+ Interferer is reference signal at +2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-10.4 — dB
N-1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1- Interferer is reference signal at -2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-13.9 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I2Interferer is reference signal at ± 4
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
-40.9 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I3Interferer is reference signal at ± 6
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
-43.7 — dB
Selectivity to image frequen-
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
C/IIM Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
-10.4 — dB
Selectivity to image frequen-
cy ± 2 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
C/IIM+1 Interferer is reference signal at im-
age frequency ± 2 MHz with 2
MHz precision
-40.9 — dB
Intermodulation performance IM Per Core_4.1, Vol 6, Part A, Sec-
tion 4.4 with n = 3
-25.1 — dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. For the BLE 2Mbps in-band blocking performance, there may be up to 5 spurious response channels where the requirement of
30.8% PER is not met and therefore an exception will need to be taken for each of these frequencies to meet the requirements of
the BLE standard.
2. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 2 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
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4.1.9.7 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle
of 66%.
Table 4.18. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Error vector magnitude (off-
set EVM), per 802.15.4-2011
EVM Average across frequency. Signal
is DSSS-OQPSK reference pack-
et1
3.8 % rms
Power spectral density limit PSDLIMIT Relative, at carrier ± 3.5 MHz, out-
put power at POUTMAX
-26 — dBc/
100kHz
Absolute, at carrier ± 3.5 MHz,
output power at POUTMAX2
-36 — dBm/
100kHz
Per FCC part 15.247, output pow-
er at POUTMAX
-4 — dBm/
3kHz
ETSI 12.1 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band
2.25 — MHz
Spurious emissions of har-
monics in restricted bands
per FCC Part 15.205/15.209,
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply,
Test Frequency is 2450 MHz
SPURHRM_FCC_
R
Continuous transmission of modu-
lated carrier
-45.8 — dBm
Spurious emissions of har-
monics in non-restricted
bands per FCC Part
15.247/15.35, Emissions tak-
en at POUTMAX, PAVDD
connected to external 3.3 V
supply, Test Frequency is
2450 MHz
SPURHRM_FCC_
NRR
Continuous transmission of modu-
lated carrier
-26 — dBc
Spurious emissions out-of-
band (above 2.483 GHz or
below 2.4 GHz) in restricted
bands, per FCC part
15.205/15.209, Emissions
taken at POUTMAX, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
SPUROOB_FCC_
R
Restricted bands 30-88 MHz; con-
tinuous transmission of modulated
carrier
-61 — dBm
Restricted bands 88-216 MHz;
continuous transmission of modu-
lated carrier
-58 — dBm
Restricted bands 216-960 MHz;
continuous transmission of modu-
lated carrier
-55 — dBm
Restricted bands >960 MHz; con-
tinuous transmission of modulated
carrier3 4
-47 — dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Spurious emissions out-of-
band in non-restricted bands
per FCC Part 15.247, Emis-
sions taken at POUTMAX,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
SPUROOB_FCC_
NR
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
-26 — dBc
Spurious emissions out-of-
band; per ETSI 300.3285
SPURETSI328 [2400-BW to 2400], [2483.5 to
2483.5+BW];
-16 — dBm
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
-26 — dBm
Spurious emissions per ETSI
EN300.4405
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
-60 — dBm
25-1000 MHz, excluding above
frequencies
-42 — dBm
1G-14G -36 — dBm
Note:
1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content.
2. For 2415 MHz, 2 dB of power backoff is used to achieve this value.
3. For 2475 MHz, 2 dB of power backoff is used to achieve this value.
4. For 2480 MHz, 13 dB of power backoff is used to achieve this value.
5. Specified at maximum power output level of 10 dBm.
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4.1.9.8 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.19. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 1% PER
SAT Signal is reference signal1. Packet
length is 20 octets.
10 — dBm
Sensitivity, 1% PER SENS Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
-102.7 — dBm
Signal is reference signal. Packet
length is 20 octets. Without DC-
DC converter.
-102.7 — dBm
Co-channel interferer rejec-
tion, 1% PER
CCR Desired signal 3 dB above sensi-
tivity limit
-4.6 — dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
ACRP1 Interferer is reference signal at +1
channel-spacing.
40.7 — dB
Interferer is filtered reference sig-
nal3 at +1 channel-spacing.
47 — dB
Interferer is CW at +1 channel-
spacing4.
54.3 — dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
ACRM1 Interferer is reference signal at -1
channel-spacing.
40.8 — dB
Interferer is filtered reference sig-
nal3 at -1 channel-spacing.
47.5 — dB
Interferer is CW at -1 channel-
spacing.
56.5 — dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level2
ACR2Interferer is reference signal at ± 2
channel-spacing
51.5 — dB
Interferer is filtered reference sig-
nal3 at ± 2 channel-spacing
53.7 — dB
Interferer is CW at ± 2 channel-
spacing
62.4 — dB
Image rejection , 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level2
IR Interferer is CW in image band4 50.4 — dB
Blocking rejection of all other
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level2. Interferer is reference
signal
BLOCK Interferer frequency < Desired fre-
quency - 3 channel-spacing
58.5 — dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
56.4 — dB
Blocking rejection of 802.11g
signal centered at +12MHz
or -13MHz5
BLOCK80211G Desired is reference signal at 6dB
above reference sensitivity level2
53 — dB
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Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.4 | 54
Parameter Symbol Test Condition Min Typ Max Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — dBm
RSSI resolution RSSIRES over RSSIMIN to RSSIMAX 0.25 — dB
RSSI accuracy in the linear
region as defined by
802.15.4-2003
RSSILIN +/-6 — dB
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s.
2. Reference sensitivity level is -85 dBm.
3. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
4. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
5. This is an IEEE 802.11b/g ERP-PBCC 22 MBit/s signal as defined by the IEEE 802.11 specification and IEEE 802.11g adden-
dum.
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4.1.10 Sub-GHz RF Transceiver Characteristics
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Electrical Specifications
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4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.
Table 4.20. Sub-GHz RF Transmitter characteristics for 915 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 902 930 MHz
Maximum TX Power1POUTMAX External PA supply = 3.3V, 20
dBm output power setting
18 19.8 23.3 dBm
External PA supply connected to
DC-DC output, 14 dBm output
power setting
12.6 14.2 16.1 dBm
Minimum active TX Power POUTMIN -45.5 — dBm
Output power step size POUTSTEP output power > 0 dBm 0.5 dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter-
nal PA supply = 3.3 V, T = 25 °C
4.8 — dB
1.8 V < VVREGVDD < 3.3 V, Exter-
nal PA supply connected to DC-
DC output, T = 25 °C
1.9 — dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C with External PA
supply = 3.3 V
0.6 1.3 dB
-40 to +85 °C with External PA
supply connected to DC-DC out-
put
0.7 1.4 dB
Output power variation vs RF
frequency
POUTVAR_F External PA supply = 3.3 V, T =
25 °C
0.2 0.6 dB
External PA supply connected to
DC-DC output, T = 25 °C
0.3 0.6 dB
Spurious emissions of har-
monics at 20 dBm output
power, Conducted measure-
ment, 20dBm match, Exter-
nal PA supply = 3.3V, Test
Frequency = 915 MHz
SPURHARM_FCC
_20
In restricted bands, per FCC Part
15.205 / 15.209
-45 -42 dBm
In non-restricted bands, per FCC
Part 15.247
-26 -20 dBc
Spurious emissions out-of-
band at 20 dBm output pow-
er, Conducted measurement,
20dBm match, External PA
supply = 3.3V, Test Frequen-
cy = 915 MHz
SPUROOB_FCC_
20
In non-restricted bands, per FCC
Part 15.247
-26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
-62 -56 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
-61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
-58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
-47 -42 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Spurious emissions of har-
monics at 14 dBm output
power, Conducted measure-
ment, 14dBm match, Exter-
nal PA supply connected to
DC-DC output, Test Fre-
quency = 915 MHz
SPURHARM_FCC
_14
In restricted bands, per FCC Part
15.205 / 15.209
-47 -42 dBm
In non-restricted bands, per FCC
Part 15.247
-26 -20 dBc
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, External PA
supply connected to DC-DC
output, Test Frequency =
915 MHz
SPUROOB_FCC_
14
In non-restricted bands, per FCC
Part 15.247
-26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
-62 -56 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
-61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
-58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
-45 -42 dBm
Error vector magnitude (off-
set EVM), per 802.15.4-2011
EVM Signal is DSSS-OQPSK reference
packet. Modulated according to
802.15.4-2011 DSSS-OQPSK in
the 915MHz band, with pseudo-
random packet data content. Ex-
ternal PA supply = 3.3V.
1.0 2.8 %rms
Power spectral density limit2PSD Relative, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolu-
tion bandwidth. The reference lev-
el shall be the highest average
spectral power measured within ±
600kHz of the carrier frequency.
External PA supply = 3.3V.
-37.1 -24.8 dBc/
100kHz
Absolute, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolu-
tion bandwidth. External PA sup-
ply = 3.3V.
-24.2 -20 dBm/
100kHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
2. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip
PN sequence mapping.
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4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.
Table 4.21. Sub-GHz RF Receiver Characteristics for 915 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 902 930 MHz
Max usable input level, 0.1%
BER
SAT500K Desired is reference 500 kbps
GFSK signal1
10 — dBm
Sensitivity SENS Desired is reference 4.8 kbps
OOK signal2, 20% PER, T ≤ 85 °C
-105.2 -100.7 dBm
Desired is reference 600 bps
GFSK signal3, 0.1% BER
-126.2 — dBm
Desired is reference 50 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
-108.2 -104.2 dBm
Desired is reference 100 kbps
GFSK signal5, 0.1% BER, T ≤ 85
°C
-105.1 -101.5 dBm
Desired is reference 500 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
-98.2 -93.2 dBm
Desired is reference 400 kbps
4GFSK signal6, 1% PER, T ≤ 85
°C
-95.2 -91 dBm
Desired is reference O-QPSK
DSSS signal7, 1% PER, Payload
length is 20 octets
-100.1 — dBm
Level above which
RFSENSE will trigger8
RFSENSETRIG CW at 915 MHz -28.1 dBm
Level below which
RFSENSE will not trigger8
RFSENSETHRES CW at 915 MHz -50 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 4.8 kbps OOK signal2
at 3dB above sensitivity level,
20% PER
48.1 — dB
Desired is 600 bps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
71.4 — dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
49.8 — dB
Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
51.1 — dB
Desired is 500 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
48.1 — dB
Desired is 400 kbps 4GFSK sig-
nal6 at 3dB above sensitivity level,
0.1% BER
41.4 — dB
Desired is reference O-QPSK
DSSS signal7 at 3dB above sensi-
tivity level, 1% PER
49.1 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 4.8 kbps OOK signal2
at 3dB above sensitivity level,
20% PER
56.3 — dB
Desired is 600 bps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
74.7 — dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
55.8 — dB
Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
56.4 — dB
Desired is 500 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
51.8 — dB
Desired is 400 kbps 4GFSK sig-
nal6 at 3dB above sensitivity level,
0.1% BER
46.8 — dB
Desired is reference O-QPSK
DSSS signal7 at 3dB above sensi-
tivity level, 1% PER
57.7 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 4.8 kbps OOK signal2
at 3dB above sensitivity level,
20% PER
48.4 — dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
54.9 — dB
Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
49.1 — dB
Desired is 500 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
47.9 — dB
Desired is 400 kbps 4GFSK sig-
nal6 at 3dB above sensitivity level,
0.1% BER
42.8 — dB
Desired is reference O-QPSK
DSSS signal7 at 3dB above sensi-
tivity level, 1% PER
48.9 — dB
Blocking selectivity, 0.1%
BER. Desired is 100 kbps
GFSK signal at 3dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz 58.7 dB
Interferer CW at Desired ± 2 MHz 62.5 dB
Interferer CW at Desired ± 10
MHz
76.4 — dB
Intermod selectivity, 0.1%
BER. CW interferers at 400
kHz and 800 kHz offsets
C/IIM Desired is 100 kbps GFSK signal5
at 3dB above sensitivity level
45 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range 0.25 dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216-960 MHz -55 -49.2 dBm
Above 960 MHz -47 -41.2 dBm
Max spurious emissions dur-
ing active receive mode,per
ARIB STD-T108 Section 3.3
SPURRX_ARIB Below 710 MHz, RBW=100kHz -60 -54 dBm
710-900 MHz, RBW=1MHz -61 -55 dBm
900-915 MHz, RBW=100kHz -61 -55 dBm
915-930 MHz, RBW=100kHz -61 -55 dBm
930-1000 MHz, RBW=100kHz -61 -55 dBm
Above 1000 MHz, RBW=1MHz -53 -47 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 835.076 kHz, channel spacing = 1
MHz.
2. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
3. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1.2 kHz, channel spacing = 300 kHz.
4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
5. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 400
kHz.
6. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 368.920 kHz, channel
spacing = 600 kHz.
7. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip
PN sequence mapping.
8. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.
Table 4.22. Sub-GHz RF Transmitter characteristics for 868 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 863 876 MHz
Maximum TX Power1POUTMAX External PA supply = 3.3V, 20
dBm output power setting, T ≤ 85
°C
17.1 19.3 22.9 dBm
External PA supply connected to
DC-DC output, 14 dBm output
power setting
11.4 13.7 16.5 dBm
Minimum active TX Power POUTMIN -43.5 — dBm
Output power step size POUTSTEP output power > 0 dBm 0.5 dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter-
nal PA supply = 3.3 V, T = 25 °C
5 — dB
1.8 V < VVREGVDD < 3.3 V, Exter-
nal PA supply connected to DC-
DC output, T = 25 °C
2 — dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C with External PA
supply = 3.3 V
0.6 0.9 dB
-40 to +85 °C with External PA
supply connected to DC-DC out-
put
0.5 1.2 dB
Output power variation vs RF
frequency
POUTVAR_F External PA supply = 3.3 V, T =
25 °C
0.2 0.6 dB
External PA supply connected to
DC-DC output, T = 25 °C
0.2 0.8 dB
Spurious emissions of har-
monics, Conducted meas-
urement, External PA supply
connected to DC-DC output,
Test Frequency = 868 MHz
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1
-35 -30 dBm
Spurious emissions out-of-
band, Conducted measure-
ment, External PA supply
connected to DC-DC output,
Test Frequency = 868 MHz
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
-59 -54 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
-42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
-36 -30 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Error vector magnitude (off-
set EVM), per 802.15.4-2015
EVM Signal is DSSS-BPSK reference
packet. Modulated according to
802.15.4-2015 DSSS-BPSK in the
868MHz band, with pseudo-ran-
dom packet data content. External
PA supply connected to external
3.3V supply
5.7 — %rms
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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4.1.10.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.
Table 4.23. Sub-GHz RF Receiver Characteristics for 868 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 863 876 MHz
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal2
10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
-120.6 — dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
-109.5 -105.4 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER
-96.4 — dBm
Desired is reference BPSK sig-
nal4, 1% PER
-110.6 — dBm
Level above which
RFSENSE will trigger5
RFSENSETRIG CW at 868 MHz -28.1 dBm
Level below which
RFSENSE will not trigger5
RFSENSETHRES CW at 868 MHz -50 dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
44.5 56.9 dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
35.4 43 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
56.8 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
48.2 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
50.2 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
48.7 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz 72.1 dB
Interferer CW at Desired ± 2 MHz 77.5 dB
Interferer CW at Desired ± 10
MHz
90.4 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range 0.25 dBm
Max spurious emissions dur-
ing active receive mode
SPURRX 30 MHz to 1 GHz -63 -57 dBm
1 GHz to 12 GHz -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.797 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. Definition of reference signal is 20 kbps BPSK
5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.10.5 Sub-GHz RF Transmitter characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.
Table 4.24. Sub-GHz RF Transmitter characteristics for 490 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 470 510 MHz
Maximum TX Power1POUTMAX External PA supply = 3.3V 18.1 20.3 23.7 dBm
Minimum active TX Power POUTMIN -44.9 — dBm
Output power step size POUTSTEP output power > 0 dBm 0.5 dB
Output power variation vs
supply, peak to peak
POUTVAR_V at 20 dBm;1.8 V < VVREGVDD <
3.3 V, External PA supply connec-
ted directly to external supply, T =
25 °C
4.3 — dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C at 20 dBm 0.2 0.9 dB
Output power variation vs RF
frequency
POUTVAR_F T = 25 °C 0.2 0.4 dB
Harmonic emissions, 20
dBm output power setting,
490 MHz
SPURHARM_CN Per China SRW Requirement,
Section 2.1, frequencies below
1GHz
-40 -36 dBm
Per China SRW Requirement,
Section 2.1, frequencies above
1GHz
-36 -30 dBm
Spurious emissions, 20 dBm
output power setting, 490
MHz
SPUROOB_CN Per China SRW Requirement,
Section 3 (48.5-72.5MHz,
76-108MHz, 167-223MHz,
470-556MHz, and 606-798MHz)
-54 — dBm
Per China SRW Requirement,
Section 2.1 (other frequencies be-
low 1GHz)
-42 — dBm
Per China SRW Requirement,
Section 2.1 (frequencies above
1GHz)
-36 — dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.
Table 4.25. Sub-GHz RF Receiver Characteristics for 490 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 470 510 MHz
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal2
10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
-122.2 — dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
-111.4 -108.9 dBm
Desired is reference 10 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
-116.8 -113.9 dBm
Desired is reference 100 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
-107.3 -104.7 dBm
Level above which
RFSENSE will trigger5
RFSENSETRIG Desired is reference 100 kbps
GFSK signal4, 0.1% BER
-28.1 — dBm
Level below which
RFSENSE will not trigger5
RFSENSETHRES CW at 490 MHz -50 dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
48 60.3 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
38.3 45.6 dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
60.4 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
52.6 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
56.5 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
54.1 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz 73.9 dB
Interferer CW at Desired ± 2 MHz 75.4 dB
Interferer CW at Desired ± 10
MHz
90.2 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range 0.25 dBm
Max spurious emissions dur-
ing active receive mode
SPURRX 30 MHz to 1 GHz -53 -47 dBm
1 GHz to 12 GHz -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf = 5 kHz, RX channel BW = 20.038 kHz.
4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz.
5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.10.7 Sub-GHz RF Transmitter characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.
Table 4.26. Sub-GHz RF Transmitter characteristics for 433 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 426 445 MHz
Maximum TX Power1POUTMAX External PA supply connected to
DC-DC output, 14dBm output
power
12.5 15.1 17.4 dBm
External PA supply connected to
DC-DC output, 10dBm output
power
8.3 10.6 13.3 dBm
Minimum active TX Power POUTMIN -42 — dBm
Output power step size POUTSTEP output power > 0 dBm 0.5 dB
Output power variation vs
supply, peak to peak, Pout =
10dBm
POUTVAR_V At 10 dBm;1.8 V < VVREGVDD <
3.3 V, External PA supply = DC-
DC output, T = 25 °C
1.7 — dB
Output power variation vs
temperature, peak to peak,
Pout= 10dBm
POUTVAR_T -40 to +85C at 10dBm 0.5 1.2 dB
Output power variation vs RF
frequency, Pout = 10dBm
POUTVAR_F T = 25 °C 0.1 0.2 dB
Spurious emissions of har-
monics FCC, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
-47 -42 dBm
In non-restricted bands, per FCC
Part 15.231
-26 -20 dBc
Spurious emissions out-of-
band FCC, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPUROOB_FCC In non-restricted bands, per FCC
Part 15.231
-26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
-52 -46 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
-61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
-58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
-47 -42 dBm
Spurious emissions of har-
monics ETSI, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (frequencies below 1Ghz)
-42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1Ghz)
-36 -30 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Spurious emissions out-of-
band ETSI, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
-60 -54 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
-42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
-36 -30 dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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4.1.10.8 Sub-GHz RF Receiver Characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.
Table 4.27. Sub-GHz RF Receiver Characteristics for 433 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 426 445 MHz
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
10 — dBm
Max usable input level, 0.1%
BER
SAT50k Desired is reference 50 kbps
GFSK signal2
10 — dBm
Sensitivity SENS Desired is reference 4.8 kbps
OOK signal3, 20% PER
-107.4 — dBm
Desired is reference 100 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
-107.3 -105 dBm
Desired is reference 50 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
-110.3 -107.2 dBm
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
-123.1 — dBm
Desired is reference 9.6 kbps
GFSK signal5, 1% PER, T ≤ 85 °C
-112.6 -109 dBm
Level above which
RFSENSE will trigger6
RFSENSETRIG CW at 433 MHz -28.1 dBm
Level below which
RFSENSE will not trigger6
RFSENSETHRES CW at 433 MHz -50 dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
51.6 — dB
Desired is 100 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
35 44.1 — dB
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
47 61.5 — dB
Desired is 50 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
45.6 53.1 dB
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
35.7 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
57.8 — dB
Desired is 100 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
54.6 — dB
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
62.4 — dB
Desired is 50 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
58.1 — dB
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
50.6 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
46.5 — dB
Desired is 100 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
51.7 — dB
Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
57.5 — dB
Desired is 50 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
54.4 — dB
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
48 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz 75.7 dB
Interferer CW at Desired ± 2 MHz 77.2 dB
Interferer CW at Desired ± 10
MHz
92 — dB
Intermod selectivity, 0.1%
BER. CW interferers at 12.5
kHz and 25 kHz offsets
C/IIM Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level
58.8 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range 0.25 dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216-960 MHz -55 -49 dBm
Above 960 MHz -47 -41 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Max spurious emissions dur-
ing active receive mode, per
ETSI 300-220 Section 8.6
SPURRX_ETSI Below 1000 MHz -63 -57 dBm
Above 1000 MHz -53 -47 dBm
Max spurious emissions dur-
ing active receive mode, per
ARIB STD T67 Section
3.3(5)
SPURRX_ARIB Below 710 MHz, RBW=100kHz -60 -54 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 200
kHz.
5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5, inner deviation = 0.8 kHz, RX channel BW = 8.5 kHz, channel spacing
= 12.5 kHz.
6. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.10.9 Sub-GHz RF Transmitter characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.
Table 4.28. Sub-GHz RF Transmitter characteristics for 315 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 195 358 MHz
Maximum TX Power1POUTMAX External PA supply connected to
DC-DC output, T ≤ 85 °C
13.8 17.2 21.1 dBm
Minimum active TX Power POUTMIN -43.9 — dBm
Output power step size POUTSTEP output power > 0 dBm 0.5 dB
Output power variation vs
supply
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter-
nal PA supply = DC-DC output, T
= 25 °C
1.8 — dB
Output power variation vs
temperature
POUTVAR_T -40 to +85C 0.5 1.2 dB
Output power variation vs RF
frequency
POUTVAR_F T = 25 °C 0.1 0.7 dB
Spurious emissions of har-
monics at 14 dBm output
power, Conducted measure-
ment, 14dBm match, Exter-
nal PA supply connected to
DC-DC output, Test Fre-
quency = 303 MHz
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
-47 -42 dBm
In non-restricted bands, per FCC
Part 15.231
-26 -20 dBc
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, External PA
supply connected to DC-DC
output, Test Frequency =
303 MHz
SPUROOB_FCC In non-restricted bands, per FCC
Part 15.231
-26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
-52 -46 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
-61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
-58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
-47 -42 dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.
Table 4.29. Sub-GHz RF Receiver Characteristics for 315 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 195 358 MHz
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal2
10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
-123.2 -120.7 dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
-111.4 -108.6 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
-98.8 -95.5 dBm
Level above which
RFSENSE will trigger4
RFSENSETRIG CW at 315 MHz -28.1 dBm
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 315 MHz -50 dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
54.1 63.6 dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
49.9 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
64.2 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level2,
0.1% BER
56.2 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
53 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
51.4 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz 75 dB
Interferer CW at Desired ± 2 MHz 76.5 dB
Interferer CW at Desired ± 10
MHz
72.6 91.9 dB
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Parameter Symbol Test Condition Min Typ Max Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range 0.25 dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216-960 MHz -63 -57 dBm
Above 960MHz -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.10.11 Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.
Table 4.30. Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 169 170 MHz
Maximum TX Power1POUTMAX External PA supply = 3.3 V 18.1 19.7 22.4 dBm
Minimum active TX Power POUTMIN -42.6 — dBm
Output power step size POUTSTEP output power > 0 dBm 0.5 dB
Output power variation vs
supply, peak to peak
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, Exter-
nal PA supply = 3.3 V, T = 25 °C
4.8 5.0 dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C at 20 dBm 0.6 1.2 dB
Spurious emissions of har-
monics, Conducted meas-
urement, External PA supply
= 3.3 V, Test Frequency =
169 MHz
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
-42 — dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)2
-38 — dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)2
-36 — dBm
Spurious emissions out-of-
band, Conducted measure-
ment, External PA supply =
3.3 V, Test Frequency = 169
MHz
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
-42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
-42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
-36 -30 dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
2. Typical value marginally passes specification. Additional margin can be obtained by increasing the order of the harmonic filter.
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4.1.10.12 Sub-GHz RF Receiver Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.
Table 4.31. Sub-GHz RF Receiver Characteristics for 169 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 169 170 MHz
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal2
10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
-124 — dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
-112.2 -108 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
-99.2 -96 dBm
Level above which
RFSENSE will trigger4
RFSENSETRIG CW at 169 MHz -28.1 dBm
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 169 MHz -50 dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 x
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
64.8 — dB
Desired is 38.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
43.3 51.4 dB
Alternate channel selectivity,
Interferer is CW at ± 2 x
channel-spacing
C/I2Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
67.4 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
60.6 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
47.1 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
47.1 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz 73.4 dB
Interferer CW at Desired ± 2 MHz 75 dB
Interferer CW at Desired ± 10
MHz
80 90.1 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range 0.25 dBm
Max spurious emissions dur-
ing active receive mode
SPURRX 30 MHz to 1 GHz -63 -57 dBm
1 GHz to 12 GHz -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
4.1.11 Modem
Table 4.32. Modem
Parameter Symbol Test Condition Min Typ Max Unit
Receive bandwidth BWRX Configurable range with 38.4 MHz
crystal
0.1 2530 kHz
IF frequency fIF Configurable range with 38.4 MHz
crystal. Selected steps available.
150 1371 kHz
DSSS symbol length SLDSSS Configurable in steps of 1 chip 2 32 chips
DSSS bits per symbol BPSDSSS Configurable 1 4 bits/
symbol
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4.1.12 Oscillators
4.1.12.1 Low-Frequency Crystal Oscillator (LFXO)
Table 4.33. Low-Frequency Crystal Oscillator (LFXO)
Parameter Symbol Test Condition Min Typ Max Unit
Crystal frequency fLFXO — 32.768 — kHz
Supported crystal equivalent
series resistance (ESR)
ESRLFXO 70 kΩ
Supported range of crystal
load capacitance 1
CLFXO_CL 6 18 pF
On-chip tuning cap range 2CLFXO_T On each of LFXTAL_N and
LFXTAL_P pins
8 40 pF
On-chip tuning cap step size SSLFXO 0.25 — pF
Current consumption after
startup 3
ILFXO ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2, AGC4 = 1
273 — nA
Start- up time tLFXO ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2
308 — ms
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.
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4.1.12.2 High-Frequency Crystal Oscillator (HFXO)
Table 4.34. High-Frequency Crystal Oscillator (HFXO)
Parameter Symbol Test Condition Min Typ Max Unit
Crystal frequency fHFXO 38.4 MHz required for radio trans-
ciever operation
38 38.4 40 MHz
Supported crystal equivalent
series resistance (ESR)
ESRHFXO_38M4 Crystal frequency 38.4 MHz 60
Supported range of crystal
load capacitance 1
CHFXO_CL 6 12 pF
On-chip tuning cap range 2CHFXO_T On each of HFXTAL_N and
HFXTAL_P pins
9 20 25 pF
On-chip tuning capacitance
step
SSHFXO 0.04 — pF
Startup time tHFXO 38.4 MHz, ESR = 50 Ohm, CL =
10 pF
300 — µs
Frequency tolerance for the
crystal
FTHFXO 38.4 MHz, ESR = 50 Ohm, CL =
10 pF
-40 40 ppm
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.12.3 Low-Frequency RC Oscillator (LFRCO)
Table 4.35. Low-Frequency RC Oscillator (LFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency fLFRCO ENVREF1 = 1, T ≤ 85 °C 31.3 32.768 33.6 kHz
ENVREF1 = 1, T > 85 °C 31.6 32.768 36.8 kHz
ENVREF1 = 0, T ≤ 85 °C 31.3 32.768 33.4 kHz
ENVREF1 = 0, T > 85 °C 30.0 32.768 33.4 kHz
Startup time tLFRCO 500 — µs
Current consumption 2ILFRCO ENVREF = 1 in
CMU_LFRCOCTRL
370 — nA
ENVREF = 0 in
CMU_LFRCOCTRL
520 — nA
Note:
1. In CMU_LFRCOCTRL register.
2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
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4.1.12.4 High-Frequency RC Oscillator (HFRCO)
Table 4.36. High-Frequency RC Oscillator (HFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Frequency accuracy fHFRCO_ACC At production calibrated frequen-
cies, across supply voltage and
temperature
-2.5 2.5 %
Start-up time tHFRCO fHFRCO ≥ 19 MHz 300 ns
4 < fHFRCO < 19 MHz 1 µs
fHFRCO ≤ 4 MHz 2.5 µs
Current consumption on all
supplies
IHFRCO fHFRCO = 38 MHz 244 265 µA
fHFRCO = 32 MHz 204 222 µA
fHFRCO = 26 MHz 173 188 µA
fHFRCO = 19 MHz 143 156 µA
fHFRCO = 16 MHz 123 136 µA
fHFRCO = 13 MHz 110 124 µA
fHFRCO = 7 MHz 85 94 µA
fHFRCO = 4 MHz 32 37 µA
fHFRCO = 2 MHz 28 34 µA
fHFRCO = 1 MHz 26 31 µA
Coarse trim step size (% of
period)
SSHFRCO_COARS
E
0.8 — %
Fine trim step size (% of pe-
riod)
SSHFRCO_FINE 0.1 — %
Period jitter PJHFRCO 0.2 % RMS
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4.1.12.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Table 4.37. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Frequency accuracy fAUXHFRCO_ACC At production calibrated frequen-
cies, across supply voltage and
temperature
-3 3 %
Start-up time tAUXHFRCO fAUXHFRCO ≥ 19 MHz 400 ns
4 < fAUXHFRCO < 19 MHz 1.4 µs
fAUXHFRCO ≤ 4 MHz 2.5 µs
Current consumption on all
supplies
IAUXHFRCO fAUXHFRCO = 38 MHz 193 213 µA
fAUXHFRCO = 32 MHz 157 175 µA
fAUXHFRCO = 26 MHz 135 151 µA
fAUXHFRCO = 19 MHz 108 122 µA
fAUXHFRCO = 16 MHz 100 113 µA
fAUXHFRCO = 13 MHz 77 88 µA
fAUXHFRCO = 7 MHz 53 63 µA
fAUXHFRCO = 4 MHz 29 36 µA
fAUXHFRCO = 2 MHz 28 34 µA
fAUXHFRCO = 1 MHz 27 31 µA
Coarse trim step size (% of
period)
SSAUXHFR-
CO_COARSE
0.8 — %
Fine trim step size (% of pe-
riod)
SSAUXHFR-
CO_FINE
0.1 — %
Period jitter PJAUXHFRCO 0.2 % RMS
4.1.12.6 Ultra-low Frequency RC Oscillator (ULFRCO)
Table 4.38. Ultra-low Frequency RC Oscillator (ULFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency fULFRCO 0.95 1 1.07 kHz
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4.1.13 Flash Memory Characteristics1
Table 4.39. Flash Memory Characteristics1
Parameter Symbol Test Condition Min Typ Max Unit
Flash erase cycles before
failure
ECFLASH 10000 — cycles
Flash data retention RETFLASH T ≤ 85 °C 10 years
T ≤ 125 °C 10 years
Word (32-bit) programming
time
tW_PROG Burst write, 128 words, average
time per word
20 24.4 30 µs
Single word 60 68.4 80 µs
Page erase time2tPERASE 20 26.4 35 ms
Mass erase time3tMERASE 20 26.5 35 ms
Device erase time4 5tDERASE T ≤ 85 °C 82 100 ms
T ≤ 125 °C 82 110 ms
Erase current6IERASE Page Erase 1.6 mA
Write current6IWRITE 3.8 mA
Supply voltage during flash
erase and write
VFLASH 1.62 3.6 V
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
3. Mass erase is issued by the CPU and erases all flash.
4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
5. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
6. Measured at 25 °C.
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4.1.14 General-Purpose I/O (GPIO)
Table 4.40. General-Purpose I/O (GPIO)
Parameter Symbol Test Condition Min Typ Max Unit
Input low voltage1VIL GPIO pins IOVDD*0.3 V
Input high voltage1VIH GPIO pins IOVDD*0.7 V
Output high voltage relative
to IOVDD
VOH Sourcing 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = WEAK
IOVDD*0.8 — V
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
DRIVESTRENGTH2 = WEAK
IOVDD*0.6 — V
Sourcing 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = STRONG
IOVDD*0.8 — V
Sourcing 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = STRONG
IOVDD*0.6 — V
Output low voltage relative to
IOVDD
VOL Sinking 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = WEAK
IOVDD*0.2 V
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = WEAK
IOVDD*0.4 V
Sinking 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH2 = STRONG
IOVDD*0.2 V
Sinking 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH2 = STRONG
IOVDD*0.4 V
Input leakage current IIOLEAK All GPIO except LFXO pins, GPIO
≤ IOVDD, T ≤ 85 °C
0.1 30 nA
LFXO Pins, GPIO ≤ IOVDD, T ≤
85 °C
0.1 50 nA
All GPIO except LFXO pins, GPIO
≤ IOVDD, T > 85 °C
110 nA
LFXO Pins, GPIO ≤ IOVDD, T >
85 °C
250 nA
Input leakage current on
5VTOL pads above IOVDD
I5VTOLLEAK IOVDD < GPIO ≤ IOVDD + 2 V 3.3 15 µA
I/O pin pull-up/pull-down re-
sistor3
RPUD 30 40 65 kΩ
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
tIOGLITCH 15 25 45 ns
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Parameter Symbol Test Condition Min Typ Max Unit
Output fall time, From 70%
to 30% of VIO
tIOOF CL = 50 pF,
DRIVESTRENGTH2 = STRONG,
SLEWRATE2 = 0x6
1.8 — ns
CL = 50 pF,
DRIVESTRENGTH2 = WEAK,
SLEWRATE2 = 0x6
4.5 — ns
Output rise time, From 30%
to 70% of VIO
tIOOR CL = 50 pF,
DRIVESTRENGTH2 = STRONG,
SLEWRATE = 0x62
2.2 — ns
CL = 50 pF,
DRIVESTRENGTH2 = WEAK,
SLEWRATE2 = 0x6
7.4 — ns
Note:
1. GPIO input threshold are proportional to the IOVDD supply, except for RESETn which is proportional to AVDD.
2. In GPIO_Pn_CTRL register.
3. GPIO pull-ups are referenced to the IOVDD supply, except for RESETn, which connects to AVDD.
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4.1.15 Voltage Monitor (VMON)
Table 4.41. Voltage Monitor (VMON)
Parameter Symbol Test Condition Min Typ Max Unit
Supply current (including
I_SENSE)
IVMON In EM0 or EM1, 1 active channel,
T ≤ 85 °C
6.3 10 µA
In EM0 or EM1, 1 active channel,
T > 85 °C
14 µA
In EM0 or EM1, All channels ac-
tive, T ≤ 85 °C
12.5 17 µA
In EM0 or EM1, All channels ac-
tive, T > 85 °C
21 µA
In EM2, EM3 or EM4, 1 channel
active and above threshold
62 — nA
In EM2, EM3 or EM4, 1 channel
active and below threshold
62 — nA
In EM2, EM3 or EM4, All channels
active and above threshold
99 — nA
In EM2, EM3 or EM4, All channels
active and below threshold
99 — nA
Loading of monitored supply ISENSE In EM0 or EM1 2 µA
In EM2, EM3 or EM4 2 nA
Threshold range VVMON_RANGE 1.62 3.4 V
Threshold step size NVMON_STESP Coarse 200 — mV
Fine 20 — mV
Response time tVMON_RES Supply drops at 1V/µs rate 460 ns
Hysteresis VVMON_HYST 26 — mV
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4.1.16 Analog to Digital Converter (ADC)
Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.42. Analog to Digital Converter (ADC)
Parameter Symbol Test Condition Min Typ Max Unit
Resolution VRESOLUTION 6 12 Bits
Input voltage range1VADCIN Single ended VFS V
Differential -VFS/2 — VFS/2 V
Input range of external refer-
ence voltage, single ended
and differential
VADCREFIN_P 1 — VAVDD V
Power supply rejection2PSRRADC At DC 80 dB
Analog input common mode
rejection ratio
CMRRADC At DC 80 dB
Current from all supplies, us-
ing internal reference buffer.
Continuous operation. WAR-
MUPMODE3 = KEEPADC-
WARM
IADC_CONTINU-
OUS_LP
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 4
270 315 µA
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 1 4
125 — µA
62.5 ksps / 1 MHz ADCCLK, BIA-
SPROG = 15, GPBIASACC = 1 4
80 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE3 = NORMAL
IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 4
45 — µA
5 ksps / 16 MHz ADCCLK BIA-
SPROG = 0, GPBIASACC = 1 4
8 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation.
AWARMUPMODE3 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
IADC_STAND-
BY_LP
125 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 4
105 — µA
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 4
70 — µA
Current from all supplies, us-
ing internal reference buffer.
Continuous operation. WAR-
MUPMODE3 = KEEPADC-
WARM
IADC_CONTINU-
OUS_HP
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 4
325 — µA
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 0 4
175 — µA
62.5 ksps / 1 MHz ADCCLK, BIA-
SPROG = 15, GPBIASACC = 0 4
125 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE3 = NORMAL
IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 4
85 — µA
5 ksps / 16 MHz ADCCLK BIA-
SPROG = 0, GPBIASACC = 0 4
16 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation.
AWARMUPMODE3 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
IADC_STAND-
BY_HP
125 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 4
160 — µA
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 4
125 — µA
Current from HFPERCLK IADC_CLK HFPERCLK = 16 MHz 160 µA
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Parameter Symbol Test Condition Min Typ Max Unit
ADC clock frequency fADCCLK 16 MHz
Throughput rate fADCRATE 1 Msps
Conversion time5tADCCONV 6 bit 7 cycles
8 bit 9 cycles
12 bit 13 cycles
Startup time of reference
generator and ADC core
tADCSTART WARMUPMODE3 = NORMAL 5 µs
WARMUPMODE3 = KEEPIN-
STANDBY
2 µs
WARMUPMODE3 = KEEPINSLO-
WACC
1 µs
SNDR at 1Msps and fIN =
10kHz
SNDRADC Internal reference6, differential
measurement
58 67 — dB
External reference7, differential
measurement
68 — dB
Spurious-free dynamic range
(SFDR)
SFDRADC 1 MSamples/s, 10 kHz full-scale
sine wave
75 — dB
Differential non-linearity
(DNL)
DNLADC 12 bit resolution, No missing co-
des
-1 2 LSB
Integral non-linearity (INL),
End point method
INLADC 12 bit resolution -6 6 LSB
Offset error VADCOFFSETERR -3 0 3 LSB
Gain error in ADC VADCGAIN Using internal reference -0.2 3.5 %
Using external reference -1 %
Temperature sensor slope VTS_SLOPE -1.84 — mV/°C
Note:
1. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than
the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on
EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_CTRL register.
4. In ADCn_BIASPROG register.
5. Derived from ADCCLK.
6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is production-tested using sine wave input at 1.5 dB lower than full scale.
7. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.
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4.1.17 Analog Comparator (ACMP)
Table 4.43. Analog Comparator (ACMP)
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VACMPIN ACMPVDD =
ACMPn_CTRL_PWRSEL 1
— VACMPVDD V
Supply voltage VACMPVDD BIASPROG2 ≤ 0x10 or FULL-
BIAS2 = 0
1.8 — VVREGVDD_
MAX
V
0x10 < BIASPROG2 ≤ 0x20 and
FULLBIAS2 = 1
2.1 — VVREGVDD_
MAX
V
Active current not including
voltage reference3
IACMP BIASPROG2 = 1, FULLBIAS2 = 0 50 — nA
BIASPROG2 = 0x10, FULLBIAS2
= 0
306 — nA
BIASPROG2 = 0x02, FULLBIAS2
= 1
6.5 — µA
BIASPROG2 = 0x20, FULLBIAS2
= 1
75 92 µA
Current consumption of inter-
nal voltage reference3
IACMPREF VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
50 — nA
VLP selected as input using VDD 20 nA
VBDIV selected as input using
1.25 V reference / 1
4.1 — µA
VADIV selected as input using
VDD/1
2.4 — µA
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Parameter Symbol Test Condition Min Typ Max Unit
Hysteresis (VCM = 1.25 V,
BIASPROG2 = 0x10, FULL-
BIAS2 = 1)
VACMPHYST HYSTSEL4 = HYST0 -3 0 3 mV
HYSTSEL4 = HYST1 5 18 27 mV
HYSTSEL4 = HYST2 12 33 50 mV
HYSTSEL4 = HYST3 17 46 65 mV
HYSTSEL4 = HYST4 23 57 82 mV
HYSTSEL4 = HYST5 26 68 98 mV
HYSTSEL4 = HYST6 30 79 130 mV
HYSTSEL4 = HYST7 34 90 150 mV
HYSTSEL4 = HYST8 -3 0 3 mV
HYSTSEL4 = HYST9 -27 -18 -5 mV
HYSTSEL4 = HYST10 -50 -33 -12 mV
HYSTSEL4 = HYST11 -65 -45 -17 mV
HYSTSEL4 = HYST12 -82 -57 -23 mV
HYSTSEL4 = HYST13 -98 -67 -26 mV
HYSTSEL4 = HYST14 -130 -78 -30 mV
HYSTSEL4 = HYST15 -150 -88 -34 mV
Comparator delay5tACMPDELAY BIASPROG2 = 1, FULLBIAS2 = 0 30 — µs
BIASPROG2 = 0x10, FULLBIAS2
= 0
3.7 — µs
BIASPROG2 = 0x02, FULLBIAS2
= 1
360 — ns
BIASPROG2 = 0x20, FULLBIAS2
= 1
35 — ns
Offset voltage VACMPOFFSET BIASPROG2 =0x10, FULLBIAS2
= 1
-35 35 mV
Reference voltage VACMPREF Internal 1.25 V reference 1 1.25 1.47 V
Internal 2.5 V reference 2 2.5 2.8 V
Capacitive sense internal re-
sistance
RCSRES CSRESSEL6 = 0 — infinite — kΩ
CSRESSEL6 = 1 15 — kΩ
CSRESSEL6 = 2 27 — kΩ
CSRESSEL6 = 3 39 — kΩ
CSRESSEL6 = 4 51 — kΩ
CSRESSEL6 = 5 100 — kΩ
CSRESSEL6 = 6 162 — kΩ
CSRESSEL6 = 7 235 — kΩ
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.
2. In ACMPn_CTRL register.
3. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP +
IACMPREF.
4. In ACMPn_HYSTERESIS registers.
5. ± 100 mV differential drive.
6. In ACMPn_INPUTSEL register.
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4.1.18 Digital to Analog Converter (VDAC)
DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.44. Digital to Analog Converter (VDAC)
Parameter Symbol Test Condition Min Typ Max Unit
Output voltage VDACOUT Single-Ended 0 — VVREF V
Differential1-VVREF — VVREF V
Current consumption includ-
ing references (2 channels)2
IDAC 500 ksps, 12-bit, DRIVES-
TRENGTH = 2, REFSEL = 4
396 — µA
44.1 ksps, 12-bit, DRIVES-
TRENGTH = 1, REFSEL = 4
72 — µA
200 Hz refresh rate, 12-bit Sam-
ple-Off mode in EM2, DRIVES-
TRENGTH = 2, REFSEL = 4,
SETTLETIME = 0x02, WARMUP-
TIME = 0x0A
1.2 — µA
Current from HFPERCLK3IDAC_CLK 5.8 — µA/MHz
Sample rate SRDAC 500 ksps
DAC clock frequency fDAC 1 MHz
Conversion time tDACCONV fDAC = 1MHz 2 µs
Settling time tDACSETTLE 50% fs step settling to 5 LSB 2.5 µs
Startup time tDACSTARTUP Enable to 90% fs output, settling
to 10 LSB
12 µs
Output impedance ROUT DRIVESTRENGTH = 2, 0.4 V ≤
VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Full supply range
2 — Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Full supply range
2 — Ω
DRIVESTRENGTH = 2, 0.1 V ≤
VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Full supply range
2 — Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Full supply range
2 — Ω
Power supply rejection ratio4PSRR Vout = 50% fs. DC 65.5 dB
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Parameter Symbol Test Condition Min Typ Max Unit
Signal to noise and distortion
ratio (1 kHz sine wave),
Noise band limited to 250
kHz
SNDRDAC 500 ksps, single-ended, internal
1.25V reference
60.4 — dB
500 ksps, single-ended, internal
2.5V reference
61.6 — dB
500 ksps, single-ended, 3.3V
VDD reference
64.0 — dB
500 ksps, differential, internal
1.25V reference
63.3 — dB
500 ksps, differential, internal
2.5V reference
64.4 — dB
500 ksps, differential, 3.3V VDD
reference
65.8 — dB
Signal to noise and distortion
ratio (1 kHz sine wave),
Noise band limited to 22 kHz
SNDRDAC_BAND 500 ksps, single-ended, internal
1.25V reference
65.3 — dB
500 ksps, single-ended, internal
2.5V reference
66.7 — dB
500 ksps, single-ended, 3.3V
VDD reference
70.0 — dB
500 ksps, differential, internal
1.25V reference
67.8 — dB
500 ksps, differential, internal
2.5V reference
69.0 — dB
500 ksps, differential, 3.3V VDD
reference
68.5 — dB
Total harmonic distortion THD 70.2 dB
Differential non-linearity5DNLDAC -0.99 1 LSB
Intergral non-linearity INLDAC -4 4 LSB
Offset error6VOFFSET T = 25 °C -8 8 mV
Across operating temperature
range
-25 25 mV
Gain error6VGAIN T = 25 °C, Low-noise internal ref-
erence (REFSEL = 1V25LN or
2V5LN)
-2.5 2.5 %
T = 25 °C, Internal reference (RE-
FSEL = 1V25 or 2V5)
-5 5 %
T = 25 °C, External reference
(REFSEL = VDD or EXT)
-1.8 1.8 %
Across operating temperature
range, Low-noise internal refer-
ence (REFSEL = 1V25LN or
2V5LN)
-3.5 3.5 %
Across operating temperature
range, Internal reference (RE-
FSEL = 1V25 or 2V5)
-7.5 7.5 %
Across operating temperature
range, External reference (RE-
FSEL = VDD or EXT)
-2.0 2.0 %
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Parameter Symbol Test Condition Min Typ Max Unit
External load capactiance,
OUTSCALE=0
CLOAD 75 pF
Note:
1. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is
limited to the single-ended range.
2. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive
the load.
3. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when
the clock to the DAC peripheral is enabled in the CMU.
4. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale
5. Entire range is monotonic and has no missing codes.
6. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at
10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.
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4.1.19 Current Digital to Analog Converter (IDAC)
Table 4.45. Current Digital to Analog Converter (IDAC)
Parameter Symbol Test Condition Min Typ Max Unit
Number of ranges NIDAC_RANGES 4 — ranges
Output current IIDAC_OUT RANGESEL1 = RANGE0 0.05 1.6 µA
RANGESEL1 = RANGE1 1.6 4.7 µA
RANGESEL1 = RANGE2 0.5 16 µA
RANGESEL1 = RANGE3 2 64 µA
Linear steps within each
range
NIDAC_STEPS 32 — steps
Step size SSIDAC RANGESEL1 = RANGE0 50 — nA
RANGESEL1 = RANGE1 100 — nA
RANGESEL1 = RANGE2 500 — nA
RANGESEL1 = RANGE3 2 — µA
Total accuracy, STEPSEL1 =
0x10
ACCIDAC EM0 or EM1, AVDD=3.3 V, T = 25
°C
-3 3 %
EM0 or EM1, Across operating
temperature range
-18 22 %
EM2 or EM3, Source mode, RAN-
GESEL1 = RANGE0, AVDD=3.3
V, T = 25 °C
-2 — %
EM2 or EM3, Source mode, RAN-
GESEL1 = RANGE1, AVDD=3.3
V, T = 25 °C
-1.7 — %
EM2 or EM3, Source mode, RAN-
GESEL1 = RANGE2, AVDD=3.3
V, T = 25 °C
-0.8 — %
EM2 or EM3, Source mode, RAN-
GESEL1 = RANGE3, AVDD=3.3
V, T = 25 °C
-0.5 — %
EM2 or EM3, Sink mode, RAN-
GESEL1 = RANGE0, AVDD=3.3
V, T = 25 °C
-0.7 — %
EM2 or EM3, Sink mode, RAN-
GESEL1 = RANGE1, AVDD=3.3
V, T = 25 °C
-0.6 — %
EM2 or EM3, Sink mode, RAN-
GESEL1 = RANGE2, AVDD=3.3
V, T = 25 °C
-0.5 — %
EM2 or EM3, Sink mode, RAN-
GESEL1 = RANGE3, AVDD=3.3
V, T = 25 °C
-0.5 — %
Start up time tIDAC_SU Output within 1% of steady state
value
5 — µs
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Parameter Symbol Test Condition Min Typ Max Unit
Settling time, (output settled
within 1% of steady state val-
ue),
tIDAC_SETTLE Range setting is changed 5 µs
Step value is changed 1 µs
Current consumption2IIDAC EM0 or EM1 Source mode, ex-
cluding output current, Across op-
erating temperature range
11 18 µA
EM0 or EM1 Sink mode, exclud-
ing output current, Across operat-
ing temperature range
13 21 µA
EM2 or EM3 Source mode, ex-
cluding output current, T = 25 °C
0.023 — µA
EM2 or EM3 Sink mode, exclud-
ing output current, T = 25 °C
0.041 — µA
EM2 or EM3 Source mode, ex-
cluding output current, T ≥ 85 °C
11 — µA
EM2 or EM3 Sink mode, exclud-
ing output current, T ≥ 85 °C
13 — µA
Output voltage compliance in
source mode, source current
change relative to current
sourced at 0 V
ICOMP_SRC RANGESEL1 = RANGE0, output
voltage = min(VIOVDD,
VAVDD2-100 mV)
0.11 — %
RANGESEL1 = RANGE1, output
voltage = min(VIOVDD,
VAVDD2-100 mV)
0.06 — %
RANGESEL1 = RANGE2, output
voltage = min(VIOVDD,
VAVDD2-150 mV)
0.04 — %
RANGESEL1 = RANGE3, output
voltage = min(VIOVDD,
VAVDD2-250 mV)
0.03 — %
Output voltage compliance in
sink mode, sink current
change relative to current
sunk at IOVDD
ICOMP_SINK RANGESEL1 = RANGE0, output
voltage = 100 mV
0.12 — %
RANGESEL1 = RANGE1, output
voltage = 100 mV
0.05 — %
RANGESEL1 = RANGE2, output
voltage = 150 mV
0.04 — %
RANGESEL1 = RANGE3, output
voltage = 250 mV
0.03 — %
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).
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4.1.20 Capacitive Sense (CSEN)
Table 4.46. Capacitive Sense (CSEN)
Parameter Symbol Test Condition Min Typ Max Unit
Single conversion time (1x
accumulation)
tCNV 12-bit SAR Conversions 20.2 µs
16-bit SAR Conversions 26.4 µs
Delta Modulation Conversion (sin-
gle comparison)
1.55 — µs
Maximum external capacitive
load
CEXTMAX IREFPROG=7 (Gain = 1x), includ-
ing routing parasitics
68 — pF
IREFPROG=0 (Gain = 10x), in-
cluding routing parasitics
680 — pF
Maximum external series im-
pedance
REXTMAX 1 — kΩ
Supply current, EM2 bonded
conversions, WARMUP-
MODE=NORMAL, WAR-
MUPCNT=0
ICSEN_BOND 12-bit SAR conversions, 20 ms
conversion rate, IREFPROG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
326 — nA
Delta Modulation conversions, 20
ms conversion rate, IRE-
FPROG=7 (Gain = 1x), 10 chan-
nels bonded (total capacitance of
330 pF)1
226 — nA
12-bit SAR conversions, 200 ms
conversion rate, IREFPROG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
33 — nA
Delta Modulation conversions,
200 ms conversion rate, IRE-
FPROG=7 (Gain = 1x), 10 chan-
nels bonded (total capacitance of
330 pF)1
25 — nA
Supply current, EM2 scan
conversions, WARMUP-
MODE=NORMAL, WAR-
MUPCNT=0
ICSEN_EM2 12-bit SAR conversions, 20 ms
scan rate, IREFPROG=0 (Gain =
10x), 8 samples per scan1
690 — nA
Delta Modulation conversions, 20
ms scan rate, 8 comparisons per
sample (DMCR = 1, DMR = 2),
IREFPROG=0 (Gain = 10x), 8
samples per scan1
515 — nA
12-bit SAR conversions, 200 ms
scan rate, IREFPROG=0 (Gain =
10x), 8 samples per scan1
79 — nA
Delta Modulation conversions,
200 ms scan rate, 8 comparisons
per sample (DMCR = 1, DMR =
2), IREFPROG=0 (Gain = 10x), 8
samples per scan1
57 — nA
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Parameter Symbol Test Condition Min Typ Max Unit
Supply current, continuous
conversions, WARMUP-
MODE=KEEPCSENWARM
ICSEN_ACTIVE SAR or Delta Modulation conver-
sions of 33 pF capacitor, IRE-
FPROG=0 (Gain = 10x), always
on
90.5 — µA
HFPERCLK supply current ICSEN_HFPERCLK Current contribution from
HFPERCLK when clock to CSEN
block is enabled.
2.25 — µA/MHz
Note:
1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the periph-
eral is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a
specific application can be estimated by multiplying the current per sample by the total number of samples per period (total_cur-
rent = single_sample_current * (number_of_channels * accumulation)).
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4.1.21 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAIN-
OUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as
specified in table footnotes1 2.
Table 4.47. Operational Amplifier (OPAMP)
Parameter Symbol Test Condition Min Typ Max Unit
Supply voltage (from AVDD) VOPA HCMDIS = 0, Rail-to-rail input
range
2 3.8 V
HCMDIS = 1 1.62 3.8 V
Input voltage VIN HCMDIS = 0, Rail-to-rail input
range
VVSS — VOPA V
HCMDIS = 1 VVSS — VOPA-1.2 V
Input impedance RIN 100 — MΩ
Output voltage VOUT VVSS — VOPA V
Load capacitance3CLOAD OUTSCALE = 0 75 pF
OUTSCALE = 1 37.5 pF
Output impedance ROUT DRIVESTRENGTH = 2 or 3, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Buffer connection,
Full supply range
0.25 — Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Buffer connection,
Full supply range
0.6 — Ω
DRIVESTRENGTH = 2 or 3, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Buffer connection,
Full supply range
0.4 — Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Buffer connection,
Full supply range
1 — Ω
Internal closed-loop gain GCL Buffer connection 0.99 1 1.01 -
3x Gain connection 2.93 2.99 3.05 -
16x Gain connection 15.07 15.7 16.33 -
Active current4IOPA DRIVESTRENGTH = 3, OUT-
SCALE = 0
580 — µA
DRIVESTRENGTH = 2, OUT-
SCALE = 0
176 — µA
DRIVESTRENGTH = 1, OUT-
SCALE = 0
13 — µA
DRIVESTRENGTH = 0, OUT-
SCALE = 0
4.7 — µA
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Parameter Symbol Test Condition Min Typ Max Unit
Open-loop gain GOL DRIVESTRENGTH = 3 135 dB
DRIVESTRENGTH = 2 137 dB
DRIVESTRENGTH = 1 121 dB
DRIVESTRENGTH = 0 109 dB
Loop unit-gain frequency5UGF DRIVESTRENGTH = 3, Buffer
connection
3.38 — MHz
DRIVESTRENGTH = 2, Buffer
connection
0.9 — MHz
DRIVESTRENGTH = 1, Buffer
connection
132 — kHz
DRIVESTRENGTH = 0, Buffer
connection
34 — kHz
DRIVESTRENGTH = 3, 3x Gain
connection
2.57 — MHz
DRIVESTRENGTH = 2, 3x Gain
connection
0.71 — MHz
DRIVESTRENGTH = 1, 3x Gain
connection
113 — kHz
DRIVESTRENGTH = 0, 3x Gain
connection
28 — kHz
Phase margin PM DRIVESTRENGTH = 3, Buffer
connection
67 — °
DRIVESTRENGTH = 2, Buffer
connection
69 — °
DRIVESTRENGTH = 1, Buffer
connection
63 — °
DRIVESTRENGTH = 0, Buffer
connection
68 — °
Output voltage noise NOUT DRIVESTRENGTH = 3, Buffer
connection, 10 Hz - 10 MHz
146 — µVrms
DRIVESTRENGTH = 2, Buffer
connection, 10 Hz - 10 MHz
163 — µVrms
DRIVESTRENGTH = 1, Buffer
connection, 10 Hz - 1 MHz
170 — µVrms
DRIVESTRENGTH = 0, Buffer
connection, 10 Hz - 1 MHz
176 — µVrms
DRIVESTRENGTH = 3, 3x Gain
connection, 10 Hz - 10 MHz
313 — µVrms
DRIVESTRENGTH = 2, 3x Gain
connection, 10 Hz - 10 MHz
271 — µVrms
DRIVESTRENGTH = 1, 3x Gain
connection, 10 Hz - 1 MHz
247 — µVrms
DRIVESTRENGTH = 0, 3x Gain
connection, 10 Hz - 1 MHz
245 — µVrms
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Parameter Symbol Test Condition Min Typ Max Unit
Slew rate6SR DRIVESTRENGTH = 3,
INCBW=17
4.7 — V/µs
DRIVESTRENGTH = 3,
INCBW=0
1.5 — V/µs
DRIVESTRENGTH = 2,
INCBW=17
1.27 — V/µs
DRIVESTRENGTH = 2,
INCBW=0
0.42 — V/µs
DRIVESTRENGTH = 1,
INCBW=17
0.17 — V/µs
DRIVESTRENGTH = 1,
INCBW=0
0.058 — V/µs
DRIVESTRENGTH = 0,
INCBW=17
0.044 — V/µs
DRIVESTRENGTH = 0,
INCBW=0
0.015 — V/µs
Startup time8TSTART DRIVESTRENGTH = 2 12 µs
Input offset voltage VOSI DRIVESTRENGTH = 2 or 3, T =
25 °C
-2 2 mV
DRIVESTRENGTH = 1 or 0, T =
25 °C
-2 2 mV
DRIVESTRENGTH = 2 or 3,
across operating temperature
range
-12 12 mV
DRIVESTRENGTH = 1 or 0,
across operating temperature
range
-30 30 mV
DC power supply rejection
ratio9
PSRRDC Input referred 70 dB
DC common-mode rejection
ratio9
CMRRDC Input referred 70 dB
Total harmonic distortion THDOPA DRIVESTRENGTH = 2, 3x Gain
connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
90 — dB
DRIVESTRENGTH = 0, 3x Gain
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
90 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,
VOUTPUT = 0.5 V.
2. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5
V. Nominal voltage gain is 3.
3. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to
drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause
another ~10 µA current when the OPAMP drives 1.5 V between output and ground.
5. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth
product of the OPAMP and 1/3 attenuation of the feedback network.
6. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
7. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,
or the OPAMP may not be stable.
8. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR
and CMRR specifications do not apply to this transition region.
4.1.22 Pulse Counter (PCNT)
Table 4.48. Pulse Counter (PCNT)
Parameter Symbol Test Condition Min Typ Max Unit
Input frequency FIN Asynchronous Single and Quad-
rature Modes
20 MHz
Sampled Modes with Debounce
filter set to 0.
8 kHz
4.1.23 Analog Port (APORT)
Table 4.49. Analog Port (APORT)
Parameter Symbol Test Condition Min Typ Max Unit
Supply current1 2IAPORT Operation in EM0/EM1 7 µA
Operation in EM2/EM3 67 nA
Note:
1. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in repor-
ted peripheral currents. Additional peripherals requesting access to APORT do not incur further current.
2. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. peri-
odic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of
the requests by the specified continuous current number.
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4.1.24 I2C
4.1.24.1 I2C Standard-mode (Sm)1
Table 4.50. I2C Standard-mode (Sm)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 100 kHz
SCL clock low time tLOW 4.7 — µs
SCL clock high time tHIGH 4 — µs
SDA set-up time tSU_DAT 250 — ns
SDA hold time3tHD_DAT 100 3450 ns
Repeated START condition
set-up time
tSU_STA 4.7 — µs
(Repeated) START condition
hold time
tHD_STA 4 — µs
STOP condition set-up time tSU_STO 4 — µs
Bus free time between a
STOP and START condition
tBUF 4.7 — µs
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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4.1.24.2 I2C Fast-mode (Fm)1
Table 4.51. I2C Fast-mode (Fm)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 400 kHz
SCL clock low time tLOW 1.3 — µs
SCL clock high time tHIGH 0.6 — µs
SDA set-up time tSU_DAT 100 — ns
SDA hold time3tHD_DAT 100 900 ns
Repeated START condition
set-up time
tSU_STA 0.6 — µs
(Repeated) START condition
hold time
tHD_STA 0.6 — µs
STOP condition set-up time tSU_STO 0.6 — µs
Bus free time between a
STOP and START condition
tBUF 1.3 — µs
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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4.1.24.3 I2C Fast-mode Plus (Fm+)1
Table 4.52. I2C Fast-mode Plus (Fm+)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 1000 kHz
SCL clock low time tLOW 0.5 — µs
SCL clock high time tHIGH 0.26 — µs
SDA set-up time tSU_DAT 50 — ns
SDA hold time tHD_DAT 100 — ns
Repeated START condition
set-up time
tSU_STA 0.26 — µs
(Repeated) START condition
hold time
tHD_STA 0.26 — µs
STOP condition set-up time tSU_STO 0.26 — µs
Bus free time between a
STOP and START condition
tBUF 0.5 — µs
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
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4.1.25 USART SPI
SPI Master Timing
Table 4.53. SPI Master Timing
Parameter Symbol Test Condition Min Typ Max Unit
SCLK period 1 2 3tSCLK 2 *
tHFPERCLK
— ns
CS to MOSI 1 2tCS_MO -14.5 13.5 ns
SCLK to MOSI 1 2tSCLK_MO -8.5 8 ns
MISO setup time 1 2tSU_MI IOVDD = 1.62 V 92 ns
IOVDD = 3.0 V 42 ns
MISO hold time 1 2tH_MI -10 — ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_MO
tH_MI
tSU_MI
tSCKL_MO
tSCLK
SCLK
CLKPOL = 1
Figure 4.1. SPI Master Timing Diagram
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SPI Slave Timing
Table 4.54. SPI Slave Timing
Parameter Symbol Test Condition Min Typ Max Unit
SCLK period 1 2 3tSCLK 6 *
tHFPERCLK
— ns
SCLK high time1 2 3tSCLK_HI 2.5 *
tHFPERCLK
— ns
SCLK low time1 2 3tSCLK_LO 2.5 *
tHFPERCLK
— ns
CS active to MISO 1 2tCS_ACT_MI 4 70 ns
CS disable to MISO 1 2tCS_DIS_MI 4 50 ns
MOSI setup time 1 2tSU_MO 8 — ns
MOSI hold time 1 2 3tH_MO 7 — ns
SCLK to MISO 1 2 3tSCLK_MI 10 + 1.5 *
tHFPERCLK
65 + 2.5 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tHFPERCLK is one period of the selected HFPERCLK.
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_ACT_MI
tSCLK_HI
tSCLK
tSU_MO
tH_MO
tSCLK_MI
tCS_DIS_MI
tSCLK_LO
SCLK
CLKPOL = 1
Figure 4.2. SPI Slave Timing Diagram
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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Supp‘y Current (rnA) Supply Current (mA) EMOr 38 MHZ HFRCOv No DCDC 6EMOv 38 MHz HFRCO. With DCDC, LN DCM ‘ ‘ 7 aneova‘aKlHflup ‘ ‘ ‘ ‘ 7 aneurwmemmop 7 — CoreMark — CoreMark 2 E ‘E E E u s 3* , E g- 2 , , u. 2 , , 1 , , 1 , , r r r r r r r r r r r r r r r r —40 —20 o 20 40 so so 100 120 —40 —2o 0 20 40 so so 100 120 Temperature (Degrees C) 6EMD, 38 MHz HFRCO, With DCDC. LN CCM Temperature [Degrees C) EMO, 38 MHz HFRCO, With DCDC, LP Temperature (Degrees c) ‘ ‘ ‘ ‘ — Pr‘mearwhHeKHLacn ‘ ‘ ‘ ‘ — Pr‘mecrwhHeUJLacD — CoreMark — CureMavk 2‘ E E E '5 U >. a 2 , , g- 2 , , m 1 , , 1 , , o r r r r r r r r o r r r r r r r r 740 720 o 20 40 60 BO 100 120 740 720 o 20 40 so an 100 120 Temperature (Degrees c)
4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current vs. Temperature
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Supply Current (mA) Supp‘y Current (mA) EM], No DCDC EM1,With DCDC, LN DCM Temperature (Degrees C) 5 r r r r r 5 r r r r — erco®3sMHz — "magnum — Hmco®26MNz — HFRCoastHz — ero@3sJMHx — HFXOQsMMHz , 4 , , Q E ‘5 E 5 U _> a. a 3 m o r r r r r r r r o r r r r r r r r 740 720 o 20 40 so so 100 120 740 720 o 20 40 so so 100 120 Temperature (Degrees c) Temperature (Degrees c) 5 EM], With DCDC, LN CCM 5 EMl, With DCDC, LP ‘ ‘ ‘ ‘ — HFRCOEZSMHI ‘ ‘ ‘ ‘ — HFRCOEBEMHz — NFRCO©2§MHI — NFRCO©26MHI _ HFxc@354MHz — HFxozaBaaMHz 4 , . . . . . . ., 2 E E E ‘5 u z e. n 3 v1 1 , , o r r r r r r r r o r r r r r r r r 740 720 o 20 40 so so 100 120 740 720 o 20 40 60 so 100 120 Temperature (Degrees C)
Figure 4.4. EM1 Sleep Mode Typical Supply Current vs. Temperature
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Supp‘y Current (uA) Supply current (uA) EM2, RTCC running from EM3, 255kB RAM Retention, LFRCO (non-duty cycled) CRYOTIMER from ULFRCO r r r r r r r r — NaDCDc.16kBRAMRelenunn — NnDCDc 14" — NoDCDC,Z§5kBRAM Reummn 140 — DCDCtuDVDD,33V _ ucucuuvuum. mu mm mm" 120 7 Dcucmuvuu,33v. ' ' " 12° ’ 25m mu mm.» 100 7 g 100 7 ‘5 an 7 g 30 = u so 7 7: 60 a. a 40 7 4° 20 r 20 o r r r r o g r r r r 740 720 0 20 40 60 BO 100 120 740 720 O 20 4O 50 80 100 120 Temperature (Degrees c) Temperature (Degrees c) EM4H, 1283 RAM Retention, RTCC from LFXO EM4S 60 r r r r 10 r r r r — Nchnc,Jav — NnDCDc.)sv — NoDcDC,33V — Nuncnc.33v — DchtuDvDD,33v — Dcnctunvnn,33v so a 40 i g s 2 so 7 5 u T: 4 20 7 E m 2 1o 7 o r r r r o r r r 740 720 o 20 40 so so 100 120 740 720 o 20 40 so so 100 120 Temperature (Degrees C) Temperature (Degrees C)
Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
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Supply Current (mA) Supp‘y Current (mA) 50 45 40 35 30 25 20 15 10 30 25 20 15 10 05 OD EMO, 38 MHz HFRCO, Whi\e(1) Loop. T=25C ( ( EMO, 25 MHz HFRCO, While(1) Loop. T=25C ( ( ( 5 0 ( — m. Dcnc — m. Dcnc — ncnc, m cm — ncnc, m cm — DCDC, LN D04 4 5 — DCDC, LN DCM 7 mm, m 7 me, u , 4 o , E V 3 5 7 E E’ 5 3 o 7 L) _>- n. 2 5 a a m 7 2 o 15 ( ( ( ( 1 o ( ( ( ( 2 n 2 5 3 o 3 5 2 o 2 5 3 o 3 5 Supply thage (V) Supp‘y mGage (V) EMl, 38 MHZ HFRCO, T=25C 3 D EMl, 26 MHZ HFRCO, T=25C ‘ ‘ ‘ — Mn DCDC ‘ ‘ ‘ — Mn DCDC — Dcnc, m cm — Dcnc, LN ch — no.1 — nch,LN om — Z 5 — DCDC, LP ‘— 3 , g 2 o , \ E ___/ 1’ 5 1 5 7 u z a , g 1 D \ (n 05 OD 20 2 5 3 0 Supply Vo‘tage (V) 35 2 5 3 o Supp‘y Vo‘tage (V) 20 35
Figure 4.6. EM0 and EM1 Mode Typical Supply Current vs. Supply
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Supply Current (uA) u Supp‘y Current (uA) N 20 15 10 05 OD EM2, RTCC running from LFRCO (non-duty cyded), T=25C ( ( CRYOTIMER from ULFRCO, T=25C ( ( ( EM3, 255kB RAM Retention, _ manmmwamm _ mm — mammmpmm — Dcnctunvun _ Dcncmnvrm, 7 m am am.“ 4 7 7 gamma, me am am.“ 2 ’__—./—’/ a l>< t="U" \="" ,="" .="" k="" g="" z="" ,="" .="" ,="" a="V." ,="" ,="" 1="" ,="" ,="" 2="" d="" 2="" 5="" 3="" 0="" 3="" 5="" 2="" 0="" 2="" 5="" 3="" d="" 3="" 5="" supply="" thage="" (v)="" supp‘y="" mgage="" (v)="" em4h,="" 128="" b="" ram="" retention,="" rtcc="" from="" lfxo,="" t="25C" 0="" 20="" em4s,="" t="25C" ‘="" ‘="" ‘="" —="" nudcdc="" i="" ‘="" ‘="" ‘="" —="" nndcdc="" _="" nchxedvnd="" _="" magnum="" ,="" ,="" 0.15="" ,="" ,="" 2="" 3="" e="" 2="" 7="" 7="" a="" 0.10="" 7="" u="" 2‘="" —/\="" n.="" a.="" a="" m="" ,="" ,="" 0.05="" ,="" ,="" (="" (="" (="" (="" 0m,="" (="" (="" (="" (="" 2="" 0="" 2="" 5="" 3="" 0="" 3="" 5="" 2="" 0="" 2="" 5="" 3="" 0="" 3="" 5="" supply="" vo‘tage="" (v)="" supp‘y="" vo‘tage="" (v)="">
Figure 4.7. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply
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Efficiency vs. Load Current, Low Power Mode Relative Output Droop vs Load Current, Low Power Mode Load Current (mA) 90 i i i 5 i i i i o S E a 75 § E a e 5 g 710 U 3 E 0 w ,3 715 E g 7 7 chwams=a — 72° — LPCMPBiAS=2 H 7 7 LPCMPsiAs-l 7 chwamsu 7 ucwms7a 7 mmms7n so i i i ,25 i i i 10 3 10'2 10'1 10° 101 10'3 10'2 10" 10° 10‘ Load Current (mA) Load Current (mA) Efficiency vs. Load Current, 100 Low Noise Mode Bypass Switch Ron vs. Supply Voitage — Wynn“ ‘ ‘ ‘ ‘ ‘ ‘- 7 Medium Drive 90 — LiqMDnv: 1 s 7 7 an 7 E 7° ’ E 1 a 7 7 > 2’ so 7 5 y g u ._ o , , E 50 7 I 1 4 40 7 1 2 7 7 3o 7 20 i i 1 o i i i i 10D 101 102 1.5 2.0 2 5 3 o 3.5 4.0 VREGVDD (V)
4.2.2 DC-DC Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.8. DC-DC Converter Typical Performance Characteristics
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100μs/div 10μs/div
2V/div
offset:1.8V
20mV/div
offset:1.8V
100mA
1mA
ILOAD
60mV/div
offset:1.8V
VSW
DVDD
DVDD
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
Figure 4.9. DC-DC Converter Transition Waveforms
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Output Power vs. Temperature, Output Power vs. Supp‘y, FAVDD = External Supp‘y, PfiVDD = Externa‘ Supply = 3.6 V 2.4 GHz, CW 25 Degrees C, 2.4 GHz, CW ‘ ‘ ‘ ‘ PeakAmphtude 24 7 ‘ ‘ _‘ PeakAmphlude 20 22 7 - - 7 E E m n: E E a) 19 a) E E i i E 18 E x x m m E E 17 7 7 12 , . . , 15 w w w w w w w w 10 w w w w 740 720 o 20 40 so so 100 120 2 o 2 5 3 o 3 5 Temperature (Degrees C) Supp‘y Vokage (V) Output Power vs. Supp‘y, PAVDD = DCVDC, 15 o 25 Degrees C, 24 GHZ, CW ‘ ‘ ‘ — Peak AMDHKude 14 5 A 14 o E m E 13 5 w '5 E 13 o n E x 12 5 m w " 12 o 7 - . . . , 11 5 7 . . . . , 11 o ‘ ‘ ‘ 2 D 2 5 3 O 3 5 Supply Vo‘tage (v)
4.2.3 2.4 GHz Radio
Figure 4.10. 2.4 GHz RF Transmitter Output Power
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Sensit ity (dBm) Sensitivity (dBm) *93 794 795 *97 *97 *98 7100 —101 7102 —103 7104 —105 BLE RX Sensitivity, 1 Mbps i BLE RX Sensitivity, 2 Mbps i 40c 25 c as c 125C Sensitivity (dBm) *91 , , _94 ANA/MM i i i i i i i ,95 i i i i i i i 241 2.42 2.43 244 2.45 2.46 247 2.45 241 242 2.43 244 2.45 2.46 247 2.4a Frequency (GHz) Frequency (6sz IEEE 80115.4 2.4GHz OOPSK PER Sensitivity i i i i i i _ MC — 25c ’ — ssc — 125: 241 242 243 244 245 245 247 243 Frequency [GHz)
Figure 4.11. 2.4 GHz RF Receiver Sensitivity
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E E a, fit but m: no 1: LI: II: Q:
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
Main
Supply
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
Figure 5.1. EFR32MG12 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
Main
Supply
VDCDC
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
Figure 5.2. EFR32MG12 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)
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Typical Connection Diagrams
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E E mu m
Main
Supply
VDCDC
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
Figure 5.3. EFR32MG12 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)
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Typical Connection Diagrams
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§§III PPM—L T F
5.2 RF Matching Networks
Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 121 for applications in the 2.4GHz band, and in Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page
121 for applications in the sub-GHz band. Application-specific component values can be found in the EFR32xG12 Reference Manual.
For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
2-Element Match for 2.4GHz Band 4-Element Match for 2.4GHz Band
L0
C0
50Ω2G4RF_IOP
2G4RF_ION 2G4RF_ION
2G4RF_IOP
L0 L1
C0 C1
50Ω
PAVDD PAVDD
PAVDD PAVDD
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
Sub-GHz Match Topology I (169-500 MHz)
Sub-GHz Match Topology 2 (500-915 MHz)
SUBGRF_IN
SUBGRF_IP
SUBGRF_ON
SUBGRF_OP
50Ω
PAVDD
L0
C0
C1
L3
L4
C4 C7
BAL1
C8 C9
L5 L6
50Ω
PAVDD
L0
C0
C1
L3
L4
C4 C7
BAL1
C8 C9
L5 L6
L1 L2
C2
C3
C5
C6
C10
L7
SUBGRF_IN
SUBGRF_IP
SUBGRF_ON
SUBGRF_OP
Figure 5.5. Typical Sub-GHz RF impedance-matching network circuits
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Typical Connection Diagrams
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5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs
website (www.silabs.com/32bit-appnotes).
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Pin A1 index 7, ®Q®®@90966 @®66699996 ®®®®Qg®@@@ OO®®9@@@® .0 .©@@ ®.. 6. 6 9 eaaaa 6 @ @@@@@ @@@@@ @@@@@ 990 @@@@@ W @@@@@ :@@ @ ®@@@@@@®6®©00 @@@®®QE®..®©Q _r
6. Pin Definitions
6.1 BGA125 2.4 GHz and Sub-GHz Device Pinout
Figure 6.1. BGA125 2.4 GHz and Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.9 GPIO Functionality Table or 6.10 Alternate Functionality Overview.
Table 6.1. BGA125 2.4 GHz and Sub-GHz Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
PF3 A1 GPIO (5V) PF1 A2 GPIO (5V)
PC5 A3 GPIO (5V) PC3 A4 GPIO (5V)
PC0 A5 GPIO (5V) PC11 A6 GPIO (5V)
PC9 A7 GPIO (5V) PC7 A8 GPIO (5V)
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Pin Name Pin(s) Description Pin Name Pin(s) Description
DECOUPLE A9
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin. This pin
should not be used to power any exter-
nal circuits.
DVDD A10 Digital power supply.
VREGVDD A11 Voltage regulator VDD input VREGSW A12 DCDC regulator switching node
VREGVSS
A13
B11
B12
Voltage regulator VSS PF8 B1 GPIO (5V)
PF2 B2 GPIO (5V) PF0 B3 GPIO (5V)
PC4 B4 GPIO (5V) PC1 B5 GPIO (5V)
PJ14 B6 GPIO (5V) PC10 B7 GPIO (5V)
PC8 B8 GPIO (5V) PC6 B9 GPIO (5V)
IOVDD
B10
F2
F11
M12
Digital IO power supply. AVDD B13 Analog power supply.
PF11 C1 GPIO (5V) PF10 C2 GPIO (5V)
PF9 C3 GPIO (5V) PC2 C5 GPIO (5V)
PJ15 C6 GPIO (5V) PB15 C10 GPIO
PB14 C11 GPIO PB13 C12 GPIO
PB12 C13 GPIO PF14 D1 GPIO (5V)
PF13 D2 GPIO (5V) PF12 D3 GPIO (5V)
PB11 D11 GPIO PB10 D12 GPIO (5V)
PB9 D13 GPIO (5V) PK1 E1 GPIO (5V)
PK0 E2 GPIO PF15 E3 GPIO (5V)
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Pin Name Pin(s) Description Pin Name Pin(s) Description
VSS
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
K2
L2
Ground PB8 E12 GPIO (5V)
PB7 E13 GPIO (5V) PK2 F1 GPIO (5V)
PB6 F12 GPIO (5V) PI3 F13 GPIO (5V)
PF5 G1 GPIO (5V) PF4 G2 GPIO (5V)
PI2 G11 GPIO (5V) PI1 G12 GPIO (5V)
PI0 G13 GPIO (5V) PF7 H1 GPIO (5V)
PF6 H2 GPIO (5V) PA9 H12 GPIO (5V)
PA8 H13 GPIO (5V) RFVDD J1
J2 Radio power supply
PA7 J11 GPIO (5V) PA6 J12 GPIO (5V)
PA5 J13 GPIO (5V) HFXTAL_N K1 High Frequency Crystal input pin.
PA4 K12 GPIO PA3 K13 GPIO
HFXTAL_P L1 High Frequency Crystal output pin. BODEN L10
Brown-Out Detector Enable. This pin
may be left disconnected or tied to
AVDD.
PA2 L12 GPIO PA1 L13 GPIO
RESETn M1
Reset input, active low. This pin is inter-
nally pulled up to AVDD. To apply an
external reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
RFVSS
M2
M3
M4
M5
N5
Radio Ground
PAVSS M6
M7
Power Amplifier (PA) voltage regulator
VSS PAVDD M8
N8
Power Amplifier (PA) voltage regulator
VDD input
PD9 M9 GPIO (5V) PD11 M10 GPIO (5V)
PD13 M11 GPIO PA0 M13 GPIO
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Pin Name Pin(s) Description Pin Name Pin(s) Description
SUBGRF_OP N1 Sub GHz Differential RF output, positive
path. SUBGRF_ON N2 Sub GHz Differential RF output, nega-
tive path.
SUBGRF_IP N3 Sub GHz Differential RF input, positive
path. SUBGRF_IN N4 Sub GHz Differential RF input, negative
path.
2G4RF_ION N6
2.4 GHz Differential RF input/output,
negative path. This pin should be exter-
nally grounded.
2G4RF_IOP N7 2.4 GHz Differential RF input/output,
positive path.
PD8 N9 GPIO (5V) PD10 N10 GPIO (5V)
PD12 N11 GPIO (5V) PD14 N12 GPIO
PD15 N13 GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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Pin A1 index 1 z z 4 5 a 7 a a 19 n 12 u A GQQQQWQWW®@@@ $99006®®6®@@® @QQ 0Q @®®® @QQ @QW 66$ @@@@@ $6 @® @@@@@ WWW 60 @@@@@ 96$ 0% @@@@@ 06 @@ @@@@@ 096 @@ 00 @@ @ @@@@@@®®6®W @®®®@@®®@®® @966 @606
6.2 BGA125 2.4 GHz Device Pinout
Figure 6.2. BGA125 2.4 GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.9 GPIO Functionality Table or 6.10 Alternate Functionality Overview.
Table 6.2. BGA125 2.4 GHz Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
PF3 A1 GPIO (5V) PF1 A2 GPIO (5V)
PC5 A3 GPIO (5V) PC3 A4 GPIO (5V)
PC0 A5 GPIO (5V) PC11 A6 GPIO (5V)
PC9 A7 GPIO (5V) PC7 A8 GPIO (5V)
DECOUPLE A9
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin. This pin
should not be used to power any exter-
nal circuits.
DVDD A10 Digital power supply.
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Pin Name Pin(s) Description Pin Name Pin(s) Description
VREGVDD A11 Voltage regulator VDD input VREGSW A12 DCDC regulator switching node
VREGVSS
A13
B11
B12
Voltage regulator VSS PF8 B1 GPIO (5V)
PF2 B2 GPIO (5V) PF0 B3 GPIO (5V)
PC4 B4 GPIO (5V) PC1 B5 GPIO (5V)
PJ14 B6 GPIO (5V) PC10 B7 GPIO (5V)
PC8 B8 GPIO (5V) PC6 B9 GPIO (5V)
IOVDD
B10
F2
F11
M12
Digital IO power supply. AVDD B13 Analog power supply.
PF11 C1 GPIO (5V) PF10 C2 GPIO (5V)
PF9 C3 GPIO (5V) PC2 C5 GPIO (5V)
PJ15 C6 GPIO (5V) PB15 C10 GPIO
PB14 C11 GPIO PB13 C12 GPIO
PB12 C13 GPIO PF14 D1 GPIO (5V)
PF13 D2 GPIO (5V) PF12 D3 GPIO (5V)
PB11 D11 GPIO PB10 D12 GPIO (5V)
PB9 D13 GPIO (5V) PK1 E1 GPIO (5V)
PK0 E2 GPIO PF15 E3 GPIO (5V)
VSS
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
G5
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
K2
L2
Ground PB8 E12 GPIO (5V)
PB7 E13 GPIO (5V) PK2 F1 GPIO (5V)
PB6 F12 GPIO (5V) PI3 F13 GPIO (5V)