MAX4838A/40A/42A Datasheet by Maxim Integrated

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lVI/JXI/VI “m‘ IVIAXIIVI
General Description
The MAX4838A/MAX4840A/MAX4842A are overvoltage-
protection ICs that protect low-voltage systems against
voltages of up to +28V. If the input voltage exceeds the
overvoltage trip level, the MAX4838A/MAX4840A/
MAX4842A turn off the low-cost external n-channel
FET(s) to prevent damage to the protected components.
An internal charge pump eliminates the need for external
capacitors and drives the FET gate for a simple,
robust solution.
The MAX4838A has a 7.4V overvoltage threshold, and
the MAX4840A has a 5.8V overvoltage threshold. The
MAX4842A has a 4.7V overvoltage threshold. The
MAX4838A/MAX4840A have an undervoltage-lockout
(UVLO) threshold of 3.25V, while the MAX4842A has a
UVLO of 2.5V. In addition to the single FET configura-
tion, the devices can be configured with back-to-back
external FETs to prevent currents from being back-dri-
ven into the adapter.
On power-up, the device waits for 50ms before driving
GATE high. FLAG is held low for an additional 50ms
after GATE goes high before deasserting. The
MAX4838A/MAX4840A/MAX4842A have an open-drain
FLAG output. The FLAG output asserts immediately to
an overvoltage fault.
Additional features include a ±15kV (HBM) ESD-pro-
tected input (when bypassed with a 1µF capacitor) and
a shutdown pin (EN) to turn off the device.
All devices are offered in a small 6-pin SC70 and 6-pin
1.5mm x 1.0mm µDFN packages and are specified
over the -40°C to +85°C extended temperature range.
Applications
Cell Phones
Digital Still Cameras
PDAs and Palmtop Devices
MP3 Players
Features
Overvoltage Protection Up to +28V
Preset 7.4V, 5.8V, or 4.7V Overvoltage Trip Level
Drives Low-Cost nMOS FET
Internal 50ms Startup Delay
Internal Charge Pump
Undervoltage Lockout
±15kV ESD-Protected Input
Voltage Fault FLAG Indicator
6-Pin SC70 and µDFN Packages
Lead Free
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
________________________________________________________________ Maxim Integrated Products 1
MAX4838A
MAX4840A
MAX4842A
INPUT
+1.2V TO +28V
IN
EN
GATE
FLAG
GND
1
6
4
2
3
OUTPUT
VIO
1µF
NOTE: EN AND PULLUP
RESISTOR
NMOS
Typical Operating Circuit
Ordering Information
19-3979; Rev 0; 2/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
PART PIN-
PACKAGE
TOP
MARK
PKG
CODE
MAX4838AEXT+T 6 SC70 ACY X6S-1
MAX4838AELT+ 6 µDFN KU
L611-1
MAX4840AEXT+T 6 SC70 ACZ X6S-1
MAX4840AELT+ 6 µDFN KV
L611-1
MAX4842AEXT+T 6 SC70 ADA X6S-1
MAX4842AELT+* 6 µDFN KW
L611-1
Selector Guide
PART
UVLO
THRESHOLD
(V)
OV
TRIP
LEVEL
(V)
EN
INPUT
FLAG
OUTPUT
MAX4838A 3.25 7.4
Yes
Open-Drain
MAX4840A 3.25 5.8
Yes
Open-Drain
MAX4842A 2.50 4.7
Yes
Open-Drain
Note: All devices specified for the -40°C to +85°C extended
temperature range.
*Future product—contact factory for availability.
+Denotes lead-free package.
[VI A X I [VI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA
= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to GND ..............................................................-0.3V to +30V
GATE to GND ........................................................-0.3V to +12V
EN, FLAG to GND ....................................................-0.3V to +6V
Continuous Power Dissipation (TA= +70°C)
6-Pin SC70 (derate 3.1mW/°C above +70°C) .............245mW
6-Pin µDFN (derate 2.1mW/°C above +70°C) ............477mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Input Voltage Range VIN 1.2
28.0
V
MAX4838A/MAX4840A
3.0
3.25
3.5
Undervoltage-Lockout Threshold
UVLO VIN falling MAX4842A 2.3 2.5 2.7 V
Undervoltage-Lockout Hysteresis
50 mV
VIN rising MAX4838A 7.0 7.4 7.8
VIN rising MAX4840A 5.5 5.8 6.1
Overvoltage Trip Level OVLO
VIN rising MAX4842A 4.4 4.7 5.0
V
MAX4838A
100
MAX4840A 80
Overvoltage Trip Level Hysteresis
MAX4842A 50
mV
No load, EN = GND or 5V,
VIN = 5V (MAX4838A/MAX4840A) 80 200
IN Supply Current IIN No load, EN = GND or 4.0V,
VIN = 4V (MAX4842A) 75 160
µA
VIN = 2.9V (MAX4838A/MAX4840A) 30
UVLO Supply Current IUVLO VIN = 2.2V (MAX4842A) 22 µA
MAX4838A/MAX4840A
910
GATE Voltage VGATE
IGATE sourcing 1µA
MAX4842A 7.5 8.0 V
GATE Pulldown Current IPD VIN > VOVLO, VGATE = 5.5V 27 mA
1.2V VIN < UVLO,
ISINK = 50µA 0.4
FLAG Output Low Voltage VOL FLAG asserted
VIN OVLO, ISINK =
1mA 0.4
V
FLAG Output High Leakage IOH VFLAG = 5.5V, FLAG deasserted 1 µA
EN Input High Voltage VIH 1.5 V
EN Input Low Voltage VIL 0.4 V
EN Input Leakage ILKG EN = GND or 5.5V 1 µA
[VI 1] X I [VI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA
= +25°C.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING
Startup Delay tSTART VIN > VUVLO, VGATE > 0.3V, Figure 1 20 50 80 ms
FLAG Blanking Time tBLANK VGATE > 0.3V, VFLAG > 2.4V, Figure 1 20 50 80 ms
GATE Turn-On Time tGON
V
GA TE
= 0.3V to 8V ( M AX 4838A/M AX 4840A) ,
V
GA TE
= 0.3V to 6V ( M AX 4842A) ,
C
GA TE
= 1500p F, Fi g ur e 1
10 ms
GATE Turn-Off Time tGOFF
VIN increasing from 5V to 8V at 3V/µs
(MAX4838A/MAX4840A), VIN increasing
from 4V to 6V at 3V/µs (MAX4842A),
VGATE = 0.3V, CGATE = 1500pF, Figure 2
62s
FLAG Assertion Delay tFLAG
VIN increasing from 5V to 8V at 3V/µs
(MAX4838A/MAX4840A), VIN increasing
from 4V to 6V at 3V/µs (MAX4842A),
VFLAG = 0.4V, Figure 2
5.8 µs
Initial Overvoltage Fault Delay tOVP
VIN increasing from 0 to 8V
(MAX4838A/MAX4840A), VIN increasing
from 0V to 6V (MAX4842A), IGATE = 80% of
IPD, Figure 3
1.5 µs
Disable Time tDIS V
EN = 2.4V , V
GA TE
= 0.3V , Fi g ur e 4 2 µs
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX4838A toc01
INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
252015105
100
200
300
400
500
600
0
030
REVERSE CURRENT
vs. OUTPUT VOLTAGE
MAX4838A toc02
OUTPUT VOLTAGE (V)
REVERSE CURRENT (µA)
5.04.54.0
1
10
100
1000
0.1
3.5 5.5
SINGLE MOSFET
BACK-TO-BACK MOSFETS
MAX4838A/MAX4840A
GATE VOLTAGE vs. INPUT VOLTAGE
MAX4838A toc03
INPUT VOLTAGE (V)
GATE VOLTAGE (V)
7654
3
6
9
12
0
38
MAX4840A MAX4838A
Typical Operating Characteristics
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A); Si9936DY external MOSFET in back-to-back configuration; TA= +25°C,
unless otherwise noted.)
Note 1: All parts are 100% tested at +25°C. Electrical limits across the full temperature range are guaranteed by design and
correlation.
/1 //-f" F““‘““‘“ // r————--—~—- ‘______, J._.__._.__ rff fry r-"er* ...J K... L/ ”W___ __.\.___ { i [MAXIIVI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
4_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A); Si9936DY external MOSFET in back-to-back configuration; TA= +25°C,
unless otherwise noted.)
MAX4842A
GATE VOLTAGE vs. INPUT VOLTAGE
MAX4838A toc04
INPUT VOLTAGE (V)
GATE VOLTAGE (V)
7651 2 3 4
3
6
9
12
0
08
MAX4842A
GATE VOLTAGE vs. INPUT VOLTAGE
MAX4838A toc05
INPUT VOLTAGE (V)
GATE VOLTAGE (V)
5.45.35.25.1
9.5
10.0
10.5
11.0
9.0
5.0 5.5
IGATE = 0
IGATE = 4µA
IGATE = 8µA
MAX4838A/MAX4840A
POWER-UP RESPONSE
MAX4838A toc06
IN
GATE
5V
0V
0V
5V
0V
5V
10V
OUT
FLAG
20ms/div
ROUT =
COUT = 0
MAX4838A/MAX4840A
POWER-UP RESPONSE
MAX4838A toc07
20ms/div
5V
0V
0V
1A
0A
5V
FLAG
IIN
GATE
IN
0V
10V
ROUT = 5
OVERVOLTAGE RESPONSE
MAX4838A toc10
400ns/div
IN
GATE
IGATE
FLAG
5V
8V
0V
40mA
0A
5V
0V
10V
CGATE = 1500pF
POWER-UP OVERVOLTAGE RESPONSE
MAX4838A toc11
1µs/div
8V
GATE
IN
IGATE
FLAG
5V
0V
50mA
0A
5V
0V
0V GATE PULLED UP
TO IN WITH 100
POWER-DOWN RESPONSE
MAX4838A toc12
10ms/div
5V
IN
GATE
OUT
FLAG
10V
0V
5V
0V
5V
0V
0V
RLOAD = 50
RFLAG = 100kTO +5V
MAX4842A
POWER-UP RESPONSE
MAX4838A toc08
20ms/div
4V
0V
0V
4V
0V
4V
FLAG
OUT
GATE
IN
0V
8V
ROUT =
COUT = 0
MAX4842A
POWER-UP RESPONSE
MAX4838A toc09
20ms/div
4V
0V
0V
800mA
0A
4V
FLAG
IIN
GATE
IN
0V
8V
ROUT = 5
[VI 1] X I [VI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
_______________________________________________________________________________________ 5
PIN NAME FUNCTION
1IN
Input. IN is both the power-supply input and the overvoltage sense input. Bypass IN to GND with
a 1µF capacitor or larger.
2GND Ground
3FLAG Fault Indication Output, Open-Drain, Active Low. FLAG is asserted low during undervoltage-
lockout and overvoltage-lockout conditions. FLAG is deasserted during normal operation.
4GATE Gate-Drive Output. GATE is the output of an on-chip charge pump. When VUVLO < VIN < VOVLO,
GATE is driven high to turn on the external n-channel MOSFET(s).
5N.C.
No Connection. Not internally connected for µDFN package. Connected to ground for SC70
6-pin package; connect to ground or leave unconnected.
6EN Device Enable Input, Active Low. Drive EN low or connect to ground to allow normal device
operation. Drive EN high to turn off the external MOSFET.
Pin Description
VIN
VGATE
0V
VUVLO
0.3V
tSTART
2.4V
tBLANK
8V (6V)
tGON
VFLAG
5V (4V)
( ) MAX4842A
Figure 1. Startup Timing Diagram
VIN
VGATE
VOVLO
0.3V
tGOFF
0.4V
tFLAG
5V (4V)
8V (6V)
VFLAG
( ) MAX4842A
Figure 2. Shutdown Timing Diagram
VIN
IGATE
VOVLO
80%
tOVP
0V
8V (6V)
( ) MAX4842A
Figure 3. Power-Up Overvoltage Timing Diagram
VGATE
0.3V
tDIS
1.5V
VEN
Figure 4. Disable Timing Diagram
Timing Diagrams
MAXIM lVI/JXIIVI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
6_______________________________________________________________________________________
Detailed Description
The MAX4838A/MAX4840A/MAX4842A provide up to
+28V overvoltage protection for low-voltage systems.
When the input voltage exceeds the overvoltage trip level,
the MAX4838A/MAX4840A/MAX4842A turn off a low-cost
external n-channel FET(s) to prevent damage to the pro-
tected components. An internal charge pump (Figure 5)
drives the FET gate for a simple, robust solution.
Undervoltage Lockout (UVLO)
The MAX4838A/MAX4840A have a fixed 3.25V typical
undervoltage-lockout level (UVLO) while the MAX4842A
has a 2.5V typical UVLO. When VIN is less than the
UVLO, the GATE driver is held low and FLAG is asserted.
Overvoltage Lockout (OVLO)
The MAX4838A has a 7.4V typical overvoltage threshold
(OVLO), and the MAX4840A has a 5.8V typical overvolt-
age threshold. The MAX4842A has a 4.7V typical over-
voltage threshold. When VIN is greater than OVLO, the
GATE driver is held low and FLAG is asserted.
FLAG
Output
The FLAG output is used to signal the host system
there is a fault with the input voltage. FLAG asserts
immediately to an overvoltage fault. FLAG is held low
for 50ms after GATE turns on before deasserting.
All devices have an open-drain FLAG output. Connect
a pullup resistor from FLAG to the logic I/O voltage of
the host system.
EN
Enable Input
EN is an active-low enable input. Drive EN low or con-
nect to ground to enable normal device operation.
Drive EN high to force the external MOSFET(s) off. EN
does not override an OVLO or UVLO fault.
GATE Driver
An on-chip charge pump is used to drive GATE above
IN, allowing the use of low-cost n-channel MOSFETS.
The charge pump operates from the internal 5.5V
regulator.
The actual GATE output voltage tracks approximately
two times VIN until VIN exceeds 5.5V or the OVLO trip
level is exceeded, whichever comes first. The
MAX4838A has a 7.4V typical OVLO; therefore GATE
remains relatively constant at approximately 10.5V for
5.5V < VIN < 7.4V. The MAX4840A has a 5.8V typical
OVLO, but this can be as low as 5.5V. The MAX4840A
in practice may never actually achieve the full 10.5V
GATE output. The MAX4842A has a 4.7V (typ) OVLO,
and the GATE output voltage is 2x the input voltage.
The GATE output voltage as a function of input voltage
is shown in the Typical Operating Characteristics.
Device Operation
The MAX4838A/MAX4840A/MAX4842A have an on-
board state machine to control device operation. A
flowchart is shown in Figure 6. On initial power-up, if
VIN < UVLO or if VIN > OVLO, GATE is held at 0V, and
FLAG is low.
If UVLO < VIN < OVLO and EN is low, the device enters
startup after a 50ms internal delay. The internal charge
pump is enabled, and GATE begins to be driven above
VIN by the internal charge pump. FLAG is held low dur-
ing startup until the FLAG blanking period expires, typi-
cally 50ms after the GATE starts going high. At this
point the device is in its on state.
At any time if VIN drops below UVLO, FLAG is driven
low and GATE is driven to ground.
IN GATE
GND
EN
5.5V
REGULATOR
2x CHARGE
PUMP GATE DRIVER
CONTROL
LOGIC AND TIMER
UVLO AND
OVLO
DETECTOR FLAG
MAX4838A
MAX4840A
MAX4842A
Figure 5. Functional Diagram
“H‘l WE ll/I/lXI/VI [VI 1] X I [VI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
_______________________________________________________________________________________ 7
Applications Information
MOSFET Configuration
The MAX4838A/MAX4840A/MAX4842A can be used
with either a single MOSFET configuration as shown in
the Typical Operating Circuit, or can be configured with
a back-to-back MOSFET as shown in Figure 7. The
back-to-back configuration has almost zero reverse
current when the input supply is below the output.
If reverse current leakage is not a concern, a single
MOSFET can be used. This approach has half the loss
of the back-to-back configuration when used with simi-
lar MOSFET types, and is a lower cost solution. Note
that if the input is actually pulled low, the output is
pulled low as well due to the parasitic body diode in the
MOSFET. If this is a concern, then the back-to-back
configuration should be used.
MOSFET Selection
The MAX4838A/MAX4840A/MAX4842A are designed for
use with either a single n-channel MOSFET or dual back-
to-back n-channel MOSFETs. In most situations,
MOSFETs with RDS(ON) specified for a VGS of 4.5V work
well. If the input supply is near the UVLO maximum of
3.5V, consider using a MOSFET specified for a lower
VGS voltage. Also, the VDS should be 30V for the MOS-
FET to withstand the full 28V IN range of all devices.
Table 1 shows a selection of MOSFETs appropriate for
use with the MAX4838A/MAX4840A/MAX4842A.
IN Bypass Considerations
For most applications, bypass IN to GND with a 1µF
ceramic capacitor. If the power source has significant
inductance due to long lead length, take care to pre-
vent overshoots due to the LC tank circuit and provide
protection if necessary to prevent exceeding the 30V
absolute maximum rating on IN.
The MAX4838A/MAX4840A/MAX4842A provide protec-
tion against voltage faults up to 28V, but this does not
include negative voltages. If negative voltages are a con-
cern, connect a Schottky diode from IN to GND to clamp
negative input voltages.
ESD Test Conditions
ESD performance depends on a number of conditions.
The MAX4838A/MAX4840A/MAX4842A are specified
for ±15kV typical ESD resistance on IN when IN is
bypassed to ground with a 1µF ceramic capacitor.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
Human Body Model
Figure 8 shows the Human Body Model, and Figure 9
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kresistor.
TIMER STARTS
COUNTING
t = 50ms
t = 50ms
VIN < UVLO
VIN > UVLO
VIN < OVLO
VIN > OVLO
STANDBY
GATE = 0
FLAG = LOW
OVLO CHECK
GATE = 0
FLAG = LOW
STARTUP
GATE DRIVEN HIGH
FLAG = LOW
ON
GATE HIGH
FLAG = HIGH
Figure 6. State Diagram
MAX4838A
MAX4840A
MAX4842A
INPUT
0 TO 28V
IN
EN
GATE
FLAG
GND
1
6
4
2
3
OUTPUT
NMOS
VIO
1µF
NOTE: EN AND PULLUP
RESISTOR ON MAX4838A/
MAX4840A/MAX4842A ONLY.
Figure 7. Back-to-Back External MOSFET Configuration
lVI/JXIIVI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
8_______________________________________________________________________________________
IEC 61000-4-2
Since January 1996, all equipment manufactured and/or
sold in the European community has been required to
meet the stringent IEC 61000-4-2 specification. The IEC
61000-4-2 standard covers ESD testing and perfor-
mance of finished equipment; it does not specifically
refer to integrated circuits. The MAX4838A/MAX4840A/
MAX4842A help users design equipment that meets
Level 3 of IEC 61000-4-2, without additional ESD-protec-
tion components.
The main difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2. Because series resistance is
lower in the IEC 61000-4-2 ESD test model (Figure 10),
the ESD-withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 11 shows the current waveform for
the ±8kV IEC 61000-4-2 Level 4 ESD Contact
Discharge test. The Air-Gap test involves approaching
the device with a charger probe. The Contact
Discharge method connects the probe to the device
before the probe is energized.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
RD
1.5k
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 8. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 9. Human Body Model Current Waveform
PART CONFIGURATION/
PACKAGE
VDS MAX (V)
RON AT 4.5V
(m)MANUFACTURER
Si5902DC Dual/1206-8 30 143
Si1426DH Single/SC70-6 30 115
Vishay Silconix
www.vishay.com
402-563-6866
FDC6305N Dual/SSOT-6 20 80
FDC6561AN Dual/ SSOT-6 30 145
FDG315N Single/SC70-6 30 160
Fairchild Semiconductor
www.fairchildsemi.com
207-775-8100
Table 1. MOSFET Suggestions
MAXIM [VI 1] X I [VI
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
_______________________________________________________________________________________ 9
GND
GATEFLAG
16EN
5 N.C.
IN
MAX4838A
MAX4840A
MAX4842A
TOP VIEW
2
34
+
SC70
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50 to 100
RD
330
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 10. IEC 61000-4-2 ESD Test Model
tr = 0.7ns to 1ns
30ns
60ns
t
100%
90%
10%
IPEAK
I
Figure 11. IEC 61000-4-2 ESD Generator Current
Pin Configurations Chip Information
PROCESS: BiCMOS
GND
GATEFLAG
EN
N.C.
IN
MAX4838A
MAX4840A
MAX4842A
TOP VIEW
+
µDFN
6
5
4
1
2
3
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MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
10 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
6L UDFN.EPS
-DRAWING NOT TO SCALE-
DOCUMENT CONTROL NO.APPROVAL
TITLE:
REV.
PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm
21-0147
2
2
D
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014Calendar Year
Legend: Marked with bar Blank space - no bar required
06-11Payweek 12-17 18-23 24-29 30-35 36-41 42-47 48-51 52-05
TABLE 2 Translation Table for Payweek Binary Coding
TABLE 1 Translation Table for Calendar Year Code
Legend: Marked with bar Blank space - no bar required
go m www‘maxim-icmomlgackages L1 mum‘ m 1 nur-/ PM 1 EHRAVING NEIT m SCALEE m A NOTE » «015 REE _.‘ ‘fi: comm mMENSmN: mm mm W A U‘Efl 1.10 A. mm mm A2 m mm b DIS 030 : DID [HE D Jan 2211 e 0‘65 BSD E 115 1.35 H: m m L UJD 0,4! L] 0425 YVP (:1 am { m I. ALL DWENSIONS ARE m meErERs. 2. DMENS‘ONS ME \NCLUSWE or was. 3. nwmsxous ARE ExcLusn/E or MOLD msu a METAL EJRR : commww 4 ms, MAX A row LENGIH MEASURED AI \NTERCEPT Pow BEYWEEN DAWN "A' AND LEAD suRmE, A mm rs FDR PACKAGE cmEmmoN REFERENCE ow 7. LEAD CENTERUNES m a: n TRUE PDSmDN AS uErmEn av BISIC D‘MENS‘DN " @M lVI/JXl/VI PM W ., MAXIM
MAX4838A/MAX4840A/MAX4842A
Overvoltage-Protection Controllers with
Status
FLAG
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
©2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
SC70, 6L.EPS
PACKAGE OUTLINE, 6L SC70
21-0077
1
1
C

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