LIS2MDL Datasheet by STMicroelectronics

View All Related Products | Download PDF Datasheet
Lg
This is information on a product in full production.
November 2018 DocID030621 Rev 5 1/41
LIS2MDL
Digital output magnetic sensor:
ultra-low-power, high-performance 3-axis magnetometer
Datasheet - production data
Features
3 magnetic field channels
±50 gauss magnetic dynamic range
16-bit data output
SPI/I2C serial interfaces
Analog supply voltage 1.71 V to 3.6 V
Selectable power mode/resolution
Single measurement mode
Programmable interrupt generator
Embedded self-test
Embedded temperature sensor
ECOPACK®, RoHS and “Green” compliant
Applications
Tilt-compensated compasses
Map rotation
Intelligent power saving for handheld devices
Gaming and virtual reality input devices
Description
The LIS2MDL is an ultra-low-power, high-
performance 3-axis digital magnetic sensor.
The LIS2MDL has a magnetic field dynamic
range of ±50 gauss.
The LIS2MDL includes an I2C serial bus interface
that supports standard, fast mode, fast mode
plus, and high-speed (100 kHz, 400 kHz,
1 MHz, and 3.4 MHz) and an SPI serial standard
interface.
The device can be configured to generate an
interrupt signal for magnetic field detection.
The LIS2MDL is available in a plastic land grid
array package (LGA) and is guaranteed to
operate over an extended temperature range
from -40 °C to +85 °C.
/*$[[PP
Table 1. Device summary
Part number Temp.
range [°C] Package Packaging
LIS2MDL -40 to +85 LGA-12 Tray
LIS2MDLTR -40 to +85 LGA-12 Tape and
reel
www.st.com
Contents LIS2MDL
2/41 DocID030621 Rev 5
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2 I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Zero-gauss level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Magnetic dynamic range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 High-current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2.1 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DocID030621 Rev 5 3/41
LIS2MDL Contents
41
6.2.2 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 OFFSET_X_REG_L (45h) and OFFSET_X_REG_H (46h) . . . . . . . . . . . 29
8.2 OFFSET_Y_REG_L (47h) and OFFSET_Y_REG_H (48h) . . . . . . . . . . . 29
8.3 OFFSET_Z_REG_L (49h) and OFFSET_Z_REG_H (4Ah) . . . . . . . . . . . 29
8.4 WHO_AM_I (4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.5 CFG_REG_A (60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.6 CFG_REG_B (61h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.7 CFG_REG_C (62h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.8 INT_CTRL_REG (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.9 INT_SOURCE_REG (64h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.10 INT_THS_L_REG (65h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.11 INT_THS_H_REG (66h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.12 STATUS_REG (67h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.13 OUTX_L_REG, OUTX_H_REG (68h - 69h) . . . . . . . . . . . . . . . . . . . . . . . 34
8.14 OUTY_L_REG, OUTY_H_REG (6Ah - 6Bh) . . . . . . . . . . . . . . . . . . . . . . 36
8.15 OUTZ_L_REG, OUTZ_H_REG (6Ch - 6Dh) . . . . . . . . . . . . . . . . . . . . . . 36
8.16 TEMP_OUT_L_REG (6Eh), TEMP_OUT_H_REG (6Fh) . . . . . . . . . . . . . 36
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1 LGA-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2 LGA-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
List of tables LIS2MDL
4/41 DocID030621 Rev 5
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. I2C slave timing values (standard and fast mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. I2C slave timing values (fast mode plus and high speed). . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. RMS noise of operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 11. Current consumption of operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Operating mode and turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Maximum ODR in single measurement mode (HR and LP modes) . . . . . . . . . . . . . . . . . . 17
Table 14. Internal pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 15. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. I2C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 17. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 19. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 23
Table 20. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23
Table 21. SAD + Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 22. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 23. CFG_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 24. CFG_REG_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 25. Output data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 26. Mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 27. CFG_REG_B_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 28. CFG_REG_B_M register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 29. Digital low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 30. CFG_REG_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 31. CFG_REG_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 32. INT_CRTL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 33. INT_CTRL_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 34. INT_SOURCE_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 35. INT_SOURCE_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 36. INT_THS_L_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 37. INT_THS_L_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 38. INT_THS_H_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 39. INT_THS_H_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 40. STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 41. STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 42. OUTX_L_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 43. OUTX_H_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 44. OUTY_L_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 45. OUTY_H_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 46. OUTZ_L_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 47. OUTZ_H_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 48. Reel dimensions for carrier tape of LGA-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DocID030621 Rev 5 5/41
LIS2MDL List of tables
41
Table 49. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
List of figures LIS2MDL
6/41 DocID030621 Rev 5
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. LIS2MDL electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 6. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. LGA-12 2.0 x 2.0 x 0.7 mm package outline and mechanical data. . . . . . . . . . . . . . . . . . . 37
Figure 10. Carrier tape information for LGA-12 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. LGA-12 package orientation in carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. Reel information for carrier tape of LGA-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DocID030621 Rev 5 7/41
LIS2MDL Block diagram and pin description
41
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
,0
<
=
<
=
;
;
&+$5*(
$03/,),(5
&21752/
$'
&219(57(5
08;
/2*,&
,
&
63,
&6
6&/63&
&/2&.
75,00,1*
&,5&8,76
6(/)7(67
7(036(1625
,17'5'<
6'$6',6'2
,17(55837
*(1(5$725
6'2
%277209,(:
',5(&7,212)
'(7(&7$%/(
0$*1(7,&),(/'6
7239,(:
;
=
<
6&/63&
1&
&6
6'$6',6'2
9GGB,2
9GG
*1'
,17'5'<6'2
  
1&
1&
&
*1'
Block diagram and pin description LIS2MDL
8/41 DocID030621 Rev 5
Table 2. Pin description
Pin# Name Function
1SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
2 NC Internally not connected. Can be tied to Vdd, Vdd_IO or GND.
3CS
I2C/SPI mode selection
(1: SPI idle mode / I2C communication enabled;
0: SPI communication mode / I2C disabled)
4
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
5 C1 Capacitor connection (C1 = 220 nF)
6 GND Connected to GND
7 INT/DRDY/SDO Interrupt/data-ready signal or SDO line for 4-wire SPI connection
8 GND 0 V
9 Vdd Power supply
10 Vdd_IO Power supply for I/O pins
11 NC Internally not connected. Can be tied to Vdd, Vdd_IO or GND.
12 NC Internally not connected. Can be tied to Vdd, Vdd_IO or GND.
“mm
DocID030621 Rev 5 9/41
LIS2MDL Module specifications
41
2 Module specifications
2.1 Sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(a).
a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.
Table 3. Sensor characteristics
Symbol Parameter Test conditions Min. Typ.(1) Max. Unit
FS Magnetic dynamic range ±49.152 gauss
So Sensitivity(2) -7% 1.5 +7% mgauss/
LSB
TCSo Sensitivity change vs.
temperature(3) ±0.03 %/°C
TyOff Magnetic sensor offset With offset cancellation(4)(5) -60 +60 mgauss
TCOff Magnetic sensor offset
change vs. temp.(4) With offset cancellation -0.3 +0.3 mgauss/
°C
RMS RMS noise(6) High-resolution mode 3 mgauss
(RMS)
ST Self-test(7) 15 500 mgauss
Top Operating temperature
range -40 +85 °C
1. Typical specifications are not guaranteed.
2. Values after factory calibration test and trimming.
3. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited
number of samples, not measured during final test for production.
4. Based on characterization data on a limited number of samples, not measured during final test for production.
5. Excluding drift due to magnetic shock.
6. With low-pass filter or offset cancellation enabled.
7.
“Self-test” is defined as: OUTPUT[gauss](Self-test enabled)
- OUTPUT[gauss]
(Self-test disabled)
.
Module specifications LIS2MDL
10/41 DocID030621 Rev 5
2.2 Temperature sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted (b).
2.3 Electrical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted.(b)
b. The product is factory calibrated at 2.5 V.The operational power supply range is from 1.71 V to 3.6 V.
Table 4. Temperature sensor characteristics
Symbol Parameter Test conditions Min. Typ.(1) Max. Unit
TSDr Temperature sensor output change vs. temp. 8 digit/°C(2)
TODR Temperature refresh rate ODR(3) Hz
Top Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed.
2. 12-bit resolution.
3. Refer to Table 25.
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ.(1) Max. Unit
Vdd Supply voltage 1.71 2.5 3.6 V
Vdd_IO Module power supply for I/O 1.71 3.6 V
Idd_HR Current consumption in
high-resolution mode ODR = 20 Hz 200 μA
Idd_LP Current consumption in
low-power mode ODR = 20 Hz 50 μA
Idd_PD Current consumption in power-down 1.5 μA
VIH Digital high-level input voltage 0.7*Vdd_IO V
VIL Digital low-level input voltage 0.3*Vdd_IO V
VOH High-level output voltage IOH = 4 mA(2) Vdd_IO - 0.2 V
VOL Low-level output voltage IOL = 4 mA(2) 0.2 V
TOP Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pin in order to
guarantee the correct digital output voltage levels VOH and VOL.
kn W3 CS SPC SDI MSE OUT SDO
DocID030621 Rev 5 11/41
LIS2MDL Module specifications
41
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Figure 3. SPI slave timing diagram
Note: Values are guaranteed at 10 MHz clock frequency for SPI with 3 wires, based on
characterization results, not tested in production.
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output
ports.
Table 6. SPI slave timing values
Symbol Parameter
Value (1)
Unit
Min Max
tc(SPC) SPI clock cycle 100 ns
fc(SPC) SPI clock frequency 10 MHz
tsu(CS) CS setup time 5
ns
th(CS) CS hold time 20
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15
tv(SO) SDO valid output time 50
th(SO) SDO output hold time 5
tdis(SO) SDO output disable time 50
Module specifications LIS2MDL
12/41 DocID030621 Rev 5
2.4.2 I2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 7. I2C slave timing values (standard and fast mode)
Symbol Parameter
I2C standard mode (1) I2C fast mode (1)
Unit
Min Max Min Max
f(SCL) SCL clock frequency 0 100 0 400 kHz
tw(SCLL) Low period of the SCL clock 4.7 1.3
μs
tw(SCLH) High period of the SCL clock 4.0 0.6
tsu(SDA) Data setup time 250 100 ns
th(SDA) Data hold time 0 3.45 0 0.9
μs
th(ST) START condition hold time 4 0.6
tsu(SR) Setup time for a repeated START condition 4.7 0.6
tsu(SP) Setup time for STOP condition 4 0.6
tw(SP:SR) Bus free time between STOP and START condition 4.7 1.3
1. Data based on standard I2C protocol requirement, not tested in production.
Table 8. I2C slave timing values (fast mode plus and high speed)
Symbol Parameter
I2C fast mode
plus(1) I2C high speed(1)
Unit
Min Max Min Max
f(SCL) SCL clock frequency 0 1 0 3.4 MHz
tw(SCLL) Low period of the SCL clock 0.5 0.16
μs
tw(SCLH) High period of the SCL clock 0.26 0.06
tsu(SDA) Data setup time 50 10 ns
th(SDA) Data hold time 0 0 0.07
μs
th(ST) START condition hold time 0.26 0.16
tsu(SR) Setup time for a repeated START condition 0.26 0.16
tsu(SP) Setup time for STOP condition 0.26 0.16
tw(SP:SR) Bus free time between STOP and START condition 0.5
1. Data based on standard I2C protocol requirement, not tested in production.
DocID030621 Rev 5 13/41
LIS2MDL Module specifications
41
Figure 4. I2C slave timing diagram
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
6'$
6&/
W
VX63
W
Z6&//
W
VX6'$
W
VX65
W
K67
W
Z6&/+
W
K6'$
W
Z6365
67$57
5(3($7('
67$57
6723
67$57
Module specifications LIS2MDL
14/41 DocID030621 Rev 5
2.5 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Note: Supply voltage on any pin should never exceed 4.8 V.
Table 9. Absolute maximum ratings
Symbol Ratings Maximum value Unit
Vdd Supply voltage -0.3 to 4.8 V
Vdd_IO I/O pins supply voltage -0.3 to 4.8 V
Vin Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO) -0.3 to Vdd_IO +0.3 V
MEF Maximum exposed field 10000 gauss
TOP Operating temperature range -40 to +85 °C
TSTG Storage temperature range -40 to +125 °C
ESD Electrostatic discharge protection (HBM) 2 kV
This device is sensitive to mechanical shock, improper handling can cause
permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damage to the part.
DocID030621 Rev 5 15/41
LIS2MDL Terminology
41
3 Terminology
3.1 Sensitivity
Sensitivity describes the ratio of the output digital data expressed in LSB units and the
applied magnetic field expressed in mG (milligauss). It can be measured, for example, by
applying a known magnetic field along one axis and measuring the digital output of the
device.
3.2 Zero-gauss level
Zero-gauss level offset (TyOff) describes the deviation of an actual output signal from the
ideal output if no magnetic field is present.
3.3 Magnetic dynamic range
The magnetic dynamic range is defined as the magnetic field driven along one sensitive
axis, giving the maximum digital output value.
Functionality LIS2MDL
16/41 DocID030621 Rev 5
4 Functionality
4.1 Power modes
The LIS2MDL provides two different power modes: high-resolution and low-power modes.
The tables below summarize the RMS noise values and current consumption in different
product configurations.
When the low-pass filter is enabled, the bandwidth is reduced while noise performance is
improved without any increase in power consumption.
Table 10. RMS noise of operating modes
CFG_REG_B[LPF]
or
CFG_REG_B[OFF_CANC]
(CFG_REG_A[LP = 0])
high-resolution mode
(CFG_REG_A[LP = 1])
low-power mode
BW [Hz] Noise RMS [mg] BW [Hz] Noise RMS [mg]
0 (disable) ODR/2 4.5 ODR/2 9
1 (enable) ODR/4 3 ODR/4 6
Table 11. Current consumption of operating modes
ODR
(Hz)
Current consumption
(μA)
(CFG_REG_A
[LP] = 0)
high-resolution
CFG_REG_B
[OFF_CANC] = 0
Current consumption
(μA)
(CFG_REG_A
[LP] = 1)
low-power
CFG_REG_B
[OFF_CANC] = 0
Current consumption
(μA)
(CFG_REG_A
[LP] = 0)
high-resolution
CFG_REG_B
[OFF_CANC] = 1
Current consumption
(μA)
(CFG_REG_A
[LP] = 1)
low-power
CFG_REG_B
[OFF_CANC] = 1
10 100 25 120 50
20 200 50 235 100
50 475 125 575 235
100 950 250 1130 460
DocID030621 Rev 5 17/41
LIS2MDL Functionality
41
The following table summarizes the turn-on time of the device in the two different power
modes with the offset cancellation function enabled or disabled (see Section : Where
Current_consumption_in_power_down and Current_consumption_10Hz can be found,
respectively, in Table 5 and Table 11.).
The LIS2MDL offers single measurement mode in both high-resolution and low-power
modes.
Single measurement mode is enabled by writing bits MD[1:0] to '01' in CFG_REG_A (60h).
In single measurement mode, once the measurement has been performed, the DRDY pin is
set to high, data is available in the output register and the LIS2MDL is automatically
configured in idle mode by setting the MD[1] bit to '1'.
Single measurement is independent of the programmed ODR but depends on the frequency
at which the MD[1:0] bits are written by the microcontroller/application processor.
Maximum ODR frequency achievable in single mode measurement is given in the following
table.
In single measurement mode, for ODR < 10 Hz, current consumption can be calculated with
the following formula:
(Current_consumption_10Hz - Current_consumption_in_power_down) / (10 Hz / ODR) +
Current_consumption_in_power_down
Where Current_consumption_in_power_down and Current_consumption_10Hz can be
found, respectively, in Table 5 and Table 11.
Table 12. Operating mode and turn-on time
Operating mode Turn-on time
CFG_REG_A[LP] CFG_REG_A[OFF_CANC = 0] CFG_REG_A[OFF_CANC = 1]
0 (high-resolution) 9.4 ms 9.4 ms + 1/ODR
1 (low-power) 6.4 ms 6.4 ms + 1/ODR
Table 13. Maximum ODR in single measurement mode (HR and LP modes)
Maximum ODR Power mode (CFG_REG_A[LP])
100 Hz High resolution (LP = ‘0’)
150 Hz Low power (LP = ‘1’)
Functionality LIS2MDL
18/41 DocID030621 Rev 5
4.2 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which
converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an
analog-to-digital converter.
The magnetic data may be accessed through an I2C/SPI interface thus making the device
particularly suitable for direct interfacing with a microcontroller.
The LIS2MDL features a data-ready signal which indicates when new sets of measured
magnetic data are available, thus simplifying data synchronization in the digital system that
uses the device.
4.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-gauss level (TyOff).
The trim values are stored inside the device in nonvolatile memory. Anytime the device is
turned on, the trim parameters are downloaded into the registers to be used during active
operation. This allows using the device without further calibration.
‘ Li 4’ D |:| |:| |:| 4’ |:| |:| lstsDw/spol CI E El ”i
DocID030621 Rev 5 19/41
LIS2MDL Application hints
41
5 Application hints
Figure 5. LIS2MDL electrical connections
The device core is supplied through the Vdd line while the I/O pads are supplied through the
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μF aluminum) should
be placed as near as possible to pin 9 of the device (common design practice).
It is possible to remove Vdd, maintaining Vdd_IO, without blocking the communication bus,
in this condition the measurement chain is powered off.
The following recommendations apply to capacitor C1:
It must be connected as close as possible to pins 5 and 6 since very high current
pulses flow from C1 to pin 5 and 6. This avoids problems caused by inductive effects
due to the length of the copper strips.
It is highly recommended to use low ESR (max 200 mOhm)
The functionality of the device and the measured acceleration data are selectable and
accessible through the I2C or SPI interfaces. When using the I2C, CS must be tied high (i.e.
connected to Vdd_IO).
The functions, the threshold and the timing of the interrupt pin (INT) can be completely
programmed by the user through the I2C/SPI interface.
'LJLWDOVLJQDOIURPWRVLJQDOFRQWUROOHU6LJQDO OHYHOVDUHGHILQHGE\SURSHUVHOHFWLRQRI9GGB,2
9GGB,2
&
)
9GG
&
Q)
*1'
&
6&/63&
6'$6',6'2
&6
*1'
9G G B, 2
,17'5'<6'2
 

9G G
&
Q)
&
Q)
7239,(:
&
 Q)
*1'
1&
1&
1&
Application hints LIS2MDL
20/41 DocID030621 Rev 5
Note: In order to program INT/DRDY as a push-pull output, write the INT_on_PIN bit or
DRDY_on_PIN bit to '1' in CFG_REG_C (62h).
Please refer to AN5069 for more information (magnetometer offset cancellation,
magnetometer hard-iron compensation, interrupt generation, self-test procedure).
Table 14. Internal pin status
Pin# Name Function Pin status
1SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC) Default: input without pull-up
2 NC Internally not connected
3CS
I2C/SPI mode selection
(1: SPI idle mode / I2C communication enabled;
0: SPI communication mode / I2C disabled)
Default: input without pull-up
4
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
Default: (SDA) input without pull-up
5 C1 Capacitor connection (C1 = 220 nF) External capacitor, voltage forced
by the device
6 GND 0 V
7 INT/DRDY/SDO Interrupt/data-ready signal or SDO for 4-wire SPI
interface Default: output high impedance
8 GND 0 V
9 Vdd Power supply
10 Vdd_IO Power supply for I/O pins
11 NC Internally not connected
12 NC Internally not connected
ww
DocID030621 Rev 5 21/41
LIS2MDL Application hints
41
5.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standards.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com.
5.2 High-current wiring effects
High current in wiring and printed circuit traces can be culprits in causing errors in magnetic
field measurements for compassing.
Conductor-generated magnetic fields will add to the Earth’s magnetic field, leading to errors
in compass heading computation.
Keep currents higher than 10 mA a few millimeters away from the sensor IC.
5.3 Startup sequence
The following general-purpose sequence can be used to configure the device:
1. Write CFG_REG_A = 80h // Enable temperature compensation
//Mag = 10 Hz (high-resolution and continuous mode)
2. Write CFG_REG_C = 01h // Mag data-ready interrupt enable
Digital interfaces LIS2MDL
22/41 DocID030621 Rev 5
6 Digital interfaces
The registers embedded inside the LIS2MDL may be accessed through both the I2C and
3W SPI serial interfaces.
The serial interfaces are mapped to the same pads. To select/exploit the I2C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
6.1 I2C serial interface
The LIS2MDL I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-
up resistor. When the bus is free, both the lines are high.
The I2C interface is compliant with standard mode (100 kHz), fast mode (400 kHz), fast
mode plus (1 MHz) and high-speed mode (3.4 MHz).
Table 15. Serial interface pin description
Pin name Pin description
CS
SPI enable
I2C/SPI mode selection
(1: SPI idle mode / I2C communication enabled;
0: SPI communication mode / I2C disabled)
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3W SPI interface serial data output (SDO)
SDO 4W SPI interface serial data output (SDO)
Table 16. I2C terminology
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave The device addressed by the master
DocID030621 Rev 5 23/41
LIS2MDL Digital interfaces
41
6.1.1 I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a high-to-low transition on the data line while the SCL line is held high. After this
has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the high period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LIS2MDL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/writes.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 21 explains how the
SAD+read/write bit pattern is composed, listing all the possible configurations.
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
Table 17. Transfer when master is writing one byte to slave
Master ST SAD + W SUB DATA SP
Slave SAK SAK SAK
Table 18. Transfer when master is writing multiple bytes to slave
Master ST SAD + W SUB DATA DATA SP
Slave SAK SAK SAK SAK
Table 19. Transfer when master is receiving (reading) one byte of data from slave
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA
Table 20. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DAT
ADATA
Digital interfaces LIS2MDL
24/41 DocID030621 Rev 5
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL low to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left high by
the slave. The master can then abort the transfer. A low-to-high transition on the SDA line
while the SCL line is high is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
Default address:
The slave address is 0011110b.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition must be issued after the sub-address byte. If the bit is ‘0’ (Write) the
master will transmit to the slave with direction unchanged. Table 21 explains how the
SAD+Read/Write bit patterns are composed, listing all the possible configurations.
Table 21. SAD + Read/Write patterns
Command SAD[6:0] R/W SAD + R/W
Read 0011110 1 00111101 (3Dh)
Write 0011110 0 00111100 (3Ch)
DocID030621 Rev 5 25/41
LIS2MDL Digital interfaces
41
6.2 SPI bus interface
The LIS2MDL SPI is a bus slave. The SPI allows writing and reading the registers of the
device.
The default serial interface interacts with the application using 3 wires: CS, SPC, SDI/O.
The 4-wire SPI interface mode can be activated by writing bit 2 of CFG_REG_C (62h) to 1.
Of course, doing this disables the interrupt and data-ready signaling capability of the device.
6.2.1 SPI write
Figure 6. SPI write protocol
The SPI write command is performed with 16 clock pulses. The multiple byte write
command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 7. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
RW DI7DI6DI5DI4DI3DI2DI1DI0
AD5 AD 4 AD 3 AD2 AD 1 AD0AD6
CS
SPC
SDI
RW
AD5 AD4 AD3 AD2 AD1 AD0
DI 7 D I6 DI 5 D I4 DI 3 DI 2 DI 1 DI 0 DI 15 D I1 4 DI 13 D I1 2 DI 11 DI 10 DI 9 DI 8
AD6
Digital interfaces LIS2MDL
26/41 DocID030621 Rev 5
6.2.2 SPI read
Figure 8. SPI read protocol
The SPI read command is performed with 16 clock pulses. A multiple read is performed by
adding blocks of 8 clock pulses to the previous one. The reading address is automatically
incremented.
bit 0: WRITE bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is available in 3-wire mode.
CS
SPC
SDI/O
RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AD5 AD 4 AD 3 AD2 AD1 AD 0AD6
DocID030621 Rev 5 27/41
LIS2MDL Register mapping
41
7 Register mapping
The table given below provides a list of the 8-bit registers embedded in the device and the
corresponding addresses.
Table 22. Register address map
Name Type(1) Register address
Default Comment
Hex Binary
Reserved 00 - 44 Reserved
OFFSET_X_REG_L R/W 45 01000101 00000000
Hard-iron registers
OFFSET_X_REG_H R/W 46 01000110 00000000
OFFSET_Y_REG_L R/W 47 01000111 00000000
OFFSET_Y_REG_H R/W 48 01001000 00000000
OFFSET_Z_REG_L R/W 49 01001001 00000000
OFFSET_Z_REG_H R/W 4A 01001010 00000000
RESERVED 4B-4C Reserved
WHO_AM_I R 4F 01001111 01000000
RESERVED 50-5F Reserved
CFG_REG_A R/W 60 01100000 00000011
Configuration
registers
CFG_REG_B R/W 61 01100001 00000000
CFG_REG_C R/W 62 01100010 00000000
INT_CRTL_REG R/W 63 01100011 11100000
Interrupt
configuration registers
INT_SOURCE_REG R 64 01100100
INT_THS_L_REG R/W 65 01100101 00000000
INT_THS_H_REG R/W 66 01100110 00000000
STATUS_REG R 67 01100111
OUTX_L_REG R 68 01101000 output
Output registers
OUTX_H_REG R 69 01101001 output
OUTY_L_REG R 6A 01101010 output
OUTY_H_REG R 6B 01101010 output
OUTZ_L_REG R 6C 01101100 output
OUTZ_H_REG R 6D 01101101 output
TEMP_OUT_L_REG R 6E 01101110 output Temperature sensor
registers
TEMP_OUT_H_REG R 6F 01101111 output
1. R = read-only register, R/W = readable/writable register
Register mapping LIS2MDL
28/41 DocID030621 Rev 5
Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.
DocID030621 Rev 5 29/41
LIS2MDL Register description
41
8 Register description
8.1 OFFSET_X_REG_L (45h) and OFFSET_X_REG_H (46h)
These registers comprise a 16-bit register and represent X hard-iron offset in order to
compensate environmental effects (data in two’s complement). These values act on the
magnetic output data value in order to delete the environmental offset.
8.2 OFFSET_Y_REG_L (47h) and OFFSET_Y_REG_H (48h)
These registers comprise a 16-bit register and represent Y hard-iron offset in order to
compensate environmental effects (data in two’s complement). These values act on the
magnetic output data value in order to delete the environmental offset.
8.3 OFFSET_Z_REG_L (49h) and OFFSET_Z_REG_H (4Ah)
These registers comprise a 16-bit register and represent Z hard-iron offset in order to
compensate environmental effects (data in two’s complement). These values act on the
magnetic output data value in order to delete the environmental offset.
8.4 WHO_AM_I (4Fh)
The identification register is used to identify the device.
01000000
Register description LIS2MDL
30/41 DocID030621 Rev 5
8.5 CFG_REG_A (60h)
The configuration register is used to configure the output data rate and the measurement
configuration.
Table 23. CFG_REG_A register
COMP_
TEMP_EN REBOOT SOFT_RST LP ODR1 ODR0 MD1 MD0
Table 24. CFG_REG_A register description
COMP_
TEMP_EN(1)
1. For proper operation, this bit must be set to '1'.
Enables the magnetometer temperature compensation. Default value: 0
(0: temperature compensation disabled; 1: temperature compensation enabled)
REBOOT Reboot magnetometer memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
SOFT_RST When this bit is set, the configuration registers and user registers are reset.
Flash registers keep their values. Default value: 0
LP Enables low-power mode. Default value: 0
0: high-resolution mode 1: low-power mode enabled
ODR[1:0] Output data rate configuration (see Table 25: Output data rate configuration)
Default value: 00
MD[1:0] These bits select the mode of operation of the device (see Table 26: Mode of
operation). Default value: 11
Table 25. Output data rate configuration
ODR1 ODR0 ODR (Hz)
0 0 10 (default)
0120
1050
1 1 100
Table 26. Mode of operation
MD1 MD0 Mode
00
Continuous mode. In continuous mode the device continuously
performs measurements and places the result in the data register. The
data-ready signal is generated when a new data set is ready to be
read. This signal can be available on the external pin by setting the
DRDY_on_PIN bit in CFG_REG_C (62h).
01
Single mode. When single mode is selected, the device performs a
single measurement, sets DRDY high and returns to idle mode. Mode
register returns to idle mode bit values.
1 0 Idle mode. Device is placed in idle mode. I2C and SPI active.
1 1 Idle mode. Device is placed in idle mode. I2C and SPI active (default).
DocID030621 Rev 5 31/41
LIS2MDL Register description
41
8.6 CFG_REG_B (61h)
Table 27. CFG_REG_B_M register
Table 28. CFG_REG_B_M register description
00 0
OFF_
CANC_
ONE_
SHOT
INT_on_
DataOFF Set_FREQ OFF_CANC LPF
OFF_CANC_
ONE_SHOT
Enables offset cancellation in single measurement mode. The OFF_CANC bit
must be set to 1 when enabling offset cancellation in single measurement mode.
Default value: 0
(0: offset cancellation in single measurement mode disabled;
1: offset cancellation in single measurement mode enabled)
INT_on_
DataOFF
If ‘1’, the interrupt block recognition checks data after the hard-iron correction to
discover the interrupt. Default value: 0
Set_FREQ Selects the frequency of the set pulse. Default value: 0
(0: set pulse is released every 63 ODR;
1: set pulse is released only at power-on after PD condition)
OFF_CANC Enables offset cancellation. Default value: 0
(0: offset cancellation disabled; 1: offset cancellation enabled)
LPF Enables low-pass filter (see Table 29). Default value: 0
(0: digital filter disabled; 1: digital filter enabled)
Table 29. Digital low-pass filter
CFG_REG_B[LPF] BW [Hz]
0 (disable) ODR/2
1 (enable) ODR/4
Register description LIS2MDL
32/41 DocID030621 Rev 5
8.7 CFG_REG_C (62h)
Table 30. CFG_REG_C register
Table 31. CFG_REG_C register description
8.8 INT_CTRL_REG (63h)
The interrupt control register is used to enable and to configure the interrupt recognition.
Table 32. INT_CRTL_REG register
0 INT_on_PIN I2C_DIS BDU BLE 4WSPI Self_test DRDY_on_PIN
INT_on_PIN If '1', the INTERRUPT signal (INT bit in INT_SOURCE_REG (64h)) is driven
on the INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode.
Default value: 0
I2C_DIS If ‘1’, the I2C interface is inhibited. Only the SPI interface can be used.
BDU If enabled, reading of incorrect data is avoided when the user reads asynchro-
nously. In fact if the read request arrives during an update of the output data, a
latch is possible, reading incoherent high and low parts of the same register. Only
one part is updated and the other one remains old.
BLE If ‘1’, an inversion of the low and high parts of the data occurs.
4WSPI Set to '1' to enable SDO line on pin 7.
Self_test If ‘1’, the self-test is enabled.
DRDY_on_PIN If '1', the data-ready signal (Zyxda bit in STATUS_REG (67h)) is driven on the
INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode.
Default value: 0
XIEN YIEN ZIEN 0(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
0(1) IEA IEL IEN
Table 33. INT_CTRL_REG register description
XIEN Enables the interrupt detection for the X-axis. Default value: 1
(1: enabled; 0: disabled)
YIEN Enables the interrupt detection for the Y-axis. Default value: 1
(1: enabled; 0: disabled)
ZIEN Enables the interrupt detection for the Z-axis. Default value: 1
(1: enabled; 0: disabled)
IEA Controls the polarity of the INT bit (INT_SOURCE_REG (64h)) when an interrupt occurs.
Default: 0
If IEA = 0, then INT = 0 signals an interrupt
If IEA = 1, then INT = 1 signals an interrupt
DocID030621 Rev 5 33/41
LIS2MDL Register description
41
8.9 INT_SOURCE_REG (64h)
When interrupt latched is selected, reading this register resets all the bits in this register.
Table 34. INT_SOURCE_REG register
Table 35. INT_SOURCE_REG register description
8.10 INT_THS_L_REG (65h)
This register contains the least significant bits of the threshold value chosen for the interrupt.
Table 36. INT_THS_L_REG register
Table 37. INT_THS_L_REG register description
8.11 INT_THS_H_REG (66h)
This register contains the most significant bits of the threshold value chosen for the
interrupt.
Table 38. INT_THS_H_REG register
IEL Controls whether the INT bit (INT_SOURCE_REG (64h)) is latched or pulsed. Default: 0
If IEL = 0, then INT is pulsed.
If IEL = 1, then INT is latched.
Once latched, INT remains in the same state until INT_SOURCE_REG (64h) is read.
IEN Interrupt enable. When set, enables the interrupt generation. The INT bit
is in INT_SOURCE_REG (64h). Default: 0
Table 33. INT_CTRL_REG register description (continued)
P_TH_S_
X
P_TH_S_
Y
P_TH_S_
Z
N_TH_S_
X
N_TH_S_
Y
N_TH_S_
ZMROI INT
P_TH_S_X X-axis value exceeds the threshold positive side
P_TH_S_Y Y-axis value exceeds the threshold positive side
P_TH_S_Z Z-axis value exceeds the threshold positive side
N_TH_S_X X-axis value exceeds the threshold negative side
N_TH_S_Y Y-axis value exceeds the threshold negative side
N_TH_S_Z Z-axis value exceeds the threshold negative side
MROI MROI flag generation is alway enabled.This flag is reset by reading
INT_SOURCE_REG (64h).
INT This bit signals when the interrupt event occurs.
TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0
TH[7:0] Threshold value for the interrupt.
TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8
Register description LIS2MDL
34/41 DocID030621 Rev 5
Table 39. INT_THS_H_REG register description
These registers set the threshold value for the output to generate the interrupt (INT bit in
INT_SOURCE_REG (64h)). This threshold is common to all three (axes) output values and
is unsigned unipolar. The threshold value is correlated to the current gain and it is unsigned
because the threshold is considered as an absolute value, but crossing the threshold is
detected for both positive and negative sides.
8.12 STATUS_REG (67h)
The status register is an 8-bit read-only register. This register is used to indicate device
status.
Table 40. STATUS_REG register
Table 41. STATUS_REG register description
8.13 OUTX_L_REG, OUTX_H_REG (68h - 69h)
The data output X registers are two 8-bit registers, data output X MSB register (69h) and
output X LSB register (68h).
The output data represents the raw magnetic data only if OFFSET_X_REG is equal to zero,
otherwise hard-iron calibration is included.
Table 42. OUTX_L_REG register
TH[15:8] Threshold value for the interrupt.
Zyxor zor yor xor Zyxda zda yda xda
Zyxor X-, Y- and Z-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new set of data has overwritten the previous set).
zor Z-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data).
yor Y-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data).
xor X-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data).
Zyxda X-, Y- and Z-axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available).
zda Z-axis new data available. Default value: 0
(0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available)
yda Y-axis new data available. Default value: 0
(0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available)
xda X-axis new data available. Default value: 0
(0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
0 0 0 00000
DocID030621 Rev 5 35/41
LIS2MDL Register description
41
Table 43. OUTX_H_REG register
The value of the magnetic field is expressed in two’s complement. This register contains the
X component of the magnetic data.
0 0 0 00000
Register description LIS2MDL
36/41 DocID030621 Rev 5
8.14 OUTY_L_REG, OUTY_H_REG (6Ah - 6Bh)
The data output Y registers are two 8-bit registers, data output Y MSB register (6Bh) and
output Y LSB register (6Ah).
The output data represents the raw magnetic data only if OFFSET_Y_REG is equal to zero,
otherwise hard-iron calibration is included.
Table 44. OUTY_L_REG register
Table 45. OUTY_H_REG register
The value of the magnetic field is expressed in two’s complement. This register contains the
Y component of the magnetic data.
8.15 OUTZ_L_REG, OUTZ_H_REG (6Ch - 6Dh)
The data output Z registers are two 8-bit registers, data output Z MSB register (6Bh) and
output Z LSB register (6Ah).
The output data represents the raw magnetic data only if OFFSET_Z_REG is equal to zero,
otherwise hard-iron calibration is included.
Table 46. OUTZ_L_REG register
Table 47. OUTZ_H_REG register
The value of the magnetic field is expressed in two’s complement. This register contains the
Z component of the magnetic data.
8.16 TEMP_OUT_L_REG (6Eh), TEMP_OUT_H_REG (6Fh)
Temperature sensor data.
These registers contain temperature values from the internal temperature sensor. The
output value is expressed as a signed 16-bit byte in 2’s complement. The four most
significant bits contain a copy of the sign bit.
The nominal sensitivity is 8 LSB/°C.
0 0 0 00000
0 0 0 00000
0 0 0 00000
0 0 0 00000
THF \E W — Lenglh [L] 2 :0.1 wmm [W] 2 :0.1 Heighl [H] 0.7 MAX /
DocID030621 Rev 5 37/41
LIS2MDL Package information
41
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
9.1 LGA-12 package information
Figure 9. LGA-12 2.0 x 2.0 x 0.7 mm package outline and mechanical data
'LPHQVLRQVDUHLQPLOOLPHWHUXQOHVVRWKHUZLVHVSHFLILHG
*HQHUDO7ROHUDQFHLVPPXQOHVVRWKHUZLVHVSHFLILHG
287(5',0(16,216
,7(0 ',0(16,21>PP@ 72/(5$1&(>PP@
/HQJWK>/@ 
:LGWK>:@ 
+HLJKW>+@ 0$;
'0B
J 1 75:0 1 5 5010 as SEE NOTE 2 Bo & 12 on RD 20 MAX ‘I Fina ‘ g B sscnoN BVB % OOOOOO .-;;, v;- utm U QL'E H User Direction cfi Feed —'
Package information LIS2MDL
38/41 DocID030621 Rev 5
9.2 LGA-12 packing information
Figure 10. Carrier tape information for LGA-12 package
Figure 11. LGA-12 package orientation in carrier tape
0,1






6((127(
6((127(



6((127(
%
%
$$
57<3
6&$/(
.R

50$;
%R
6(&7,21%%
$R
6(&7,21$$
',0
$R
 
%R
 
.R
 
127(6
6352&.(7+2/(3,7&+&808/$7,9(72/(5$1&(

32&.(7326,7,215(/$7,9(726352&.(7+2/(0($685('$6758(326,7,212)32&.(7127

32&.(7+2/(
$R$1'%R$5(&$/&8/$7('21$3/$1($7$',67$1&(5$%29(7+(%277202)7+(32&.(7

DocID030621 Rev 5 39/41
LIS2MDL Package information
41
Figure 12. Reel information for carrier tape of LGA-12 package
Table 48. Reel dimensions for carrier tape of LGA-12 package
Reel dimensions (mm)
A (max) 330
B (min) 1.5
C 13 ±0.25
D (min) 20.2
N (min) 60
G 12.4 +2/-0
T (max) 18.4
$'
%
)X O O UDG L X V 7DSHVORW
LQFRUHIRU
WDSHVWDUW
PPPLQZLGWK
*PHDVXUHGDWKXE 
&
1
PPPLQ
$FFHVVKROHDW
VORWORFDWLRQ
7
Revision history LIS2MDL
40/41 DocID030621 Rev 5
10 Revision history
Table 49. Document revision history
Date Revision Changes
11-May-2017 1 Initial release
18-Jul-2017 2 Document status promoted to “Datasheet - production data”
21-Sep-2017 3
Updated Table 2: Pin description
Updated Table 5: Electrical characteristics
Updated Figure 3: SPI slave timing diagram
Removed Magnetometer offset cancellation, Magnetometer interrupt, Magnetometer
hard-iron compensation, and Self-test
Updated Section 5: Application hints, Section 5.1: Soldering information, and Section 5.3:
Startup sequence
Updated Section 6: Digital interfaces and Section 6.1: I2C serial interface
Updated CFG_REG_A (60h)
Specified default values in CFG_REG_B (61h)
Updated CFG_REG_C (62h)
Updated description of STATUS_REG (67h)
Updated description of OUTX_L_REG, OUTX_H_REG (68h - 69h), OUTY_L_REG,
OUTY_H_REG (6Ah - 6Bh) and TEMP_OUT_L_REG (6Eh), TEMP_OUT_H_REG (6Fh)
07-Nov-2018 4 Added 4-wire SPI function to pin 7 (updated Figure 1, Section 1.2: Pin description,
Section 5: Application hints, Section 6: Digital interfaces, and CFG_REG_C (62h))
28-Nov-2018 5 Updated Table 5: Electrical characteristics
DocID030621 Rev 5 41/41
LIS2MDL
41
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved

Products related to this Datasheet

SENSOR MR I2C/SPI 12LGA
LIS2MDL ADAPTER BOARD STANDARD D
3D HALL 3 CLICK
SENSOR MR I2C/SPI 12LGA
SENSOR MR I2C/SPI 12LGA