LT1168 Datasheet by Analog Devices Inc.

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7L|nt “I2 LTlléB TECHNOLOGY plifierthat requires only one external resistor 1 to 10,000. The low voltage noise of 10nV/W Vt i of L7 Umz L7LJL1WW
1
LT1168
1168fa
Low Power, Single
Resistor Gain Programmable,
Precision Instrumentation Amplifier
The LT
®
1168 is a micropower, precision instrumentation am-
plifier that requires only one external resistor to set gains of
1 to 10,000. The low voltage noise of 10nV/Hz (at 1kHz) is
not compromised by low power dissipation (350µA typical for
±15V supplies). The wide supply range of ±2.3V to ±18V allows
the LT1168 to fit into a wide variety of industrial as well as
battery-powered applications.
The high accuracy of the LT1168 is due to a 20ppm maximum
nonlinearity and 0.4% max gain error (G = 10). Previous mono-
lithic instrumentation amps cannot handle a 2k load resistor
whereas the nonlinearity of the LT1168 is specified for loads
as low as 2k. The LT1168 is laser trimmed for very low input
offset voltage (40µV max), drift (0.3µV/°C), high CMRR (90dB,
G = 1) and PSRR (103dB, G = 1). Low input bias currents of
250pA max are achieved with the use of superbeta process-
ing. The output can handle capacitive loads up to 1000pF in
any gain configuration while the inputs are ESD protected up
to 13kV (human body). The LT1168 with two external 5k
resistors passes the IEC 1000-4-2 level 4 specification.
The LT1168 is a pin-for-pin improved second source for the
AD620 and INA118. The LT1168, offered in 8-pin PDIP and
SO packages, requires significantly less PC board area than
discrete op amp resistor designs. These advantages make
the LT1168 the most cost effective solution for precision
instrumentation amplifier applications.
Supply Current: 530µA Max
Meets IEC 1000-4-2 Level 4 (±15kV) ESD Tests
with Two External 5k Resistors
Single Gain Set Resistor: G = 1 to 10,000
Gain Error: G = 10, 0.4% Max
Input Offset Voltage Drift: 0.3µV/°C Max
Gain Nonlinearity: G = 10, 20ppm Max
Input Offset Voltage: 40µV Max
Input Bias Current: 250pA Max
PSRR at A
V
=1: 103dB Min
CMRR at A
V
= 1: 90dB Min
Wide Supply Range: ±2.3V to ±18V
1kHz Voltage Noise: 10nV/Hz
0.1Hz to 10Hz Noise: 0.28µV
P-P
Available in 8-Pin PDIP and SO Packages
Bridge Amplifiers
Strain Gauge Amplifiers
Thermocouple Amplifiers
Differential to Single-Ended Converters
Differential Voltage to Current Converters
Data Acquisition
Battery-Powered and Portable Equipment
Medical Instrumentation
Scales
Single Supply* Pressure Monitor
NONLINEARITY (100ppm/DIV)
G = 1000 OUTPUT VOLTAGE (2V/DIV)
1168 TA01a
R
L
= 2k
V
OUT
= ±10V
Gain Nonlinearity
*See Theory of Operation section
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
+
23
2
1
1
1
1/2
LT1112
3.5k
5V
3.5k
3.5k
3.5k
87
6
1168 TA01
5
40k
20k
40k
DIGITAL
DATA
OUTPUT
4
R1
G = 200
249
3
REF
IN
AGND
ADC
LTC®1286
BI TECHNOLOGIES
67-8-3 R40KQ, (0.02% RATIO MATCH)
+
LT1168
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
PflCKflGEIOflDEflI FOB flTIOl'I WWI—HT UUUU
2
LT1168
1168fa
Supply Voltage ...................................................... ±20V
Differential Input Voltage (Within the
Supply Voltage) ..................................................... ±40V
Input Voltage (Equal to Supply Voltage) ................ ±20V
Input Current (Note 2) ....................................... ±20mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4) .. 40°C to 85°C
Specified Temperature Range
LT1168AC/LT1168C (Note 5) ............. 40°C to 85°C
LT1168AI/LT1168I ............................. – 40°C to 85°C
Storage Temperature Range ................. 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
S8 PART MARKING
LT1168ACN8
LT1168ACS8
LT1168AIN8
LT1168AIS8
LT1168CN8
LT1168CS8
LT1168IN8
LT1168IS8
1168A
1168AI
T
JMAX
= 150°C, θ
JA
= 150°C/ W (N8)
T
JMAX
= 150°C, θ
JA
= 190°C/ W (S8)
T
A = 25°C. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted.
1168
1168I
(Note 1)
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
1
2
3
4
8
7
6
5
TOP VIEW
R
G
–IN
+IN
–V
S
R
G
+V
S
OUTPUT
REF
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
+
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature
ranges.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LT1168AC/LT1168AI LT1168C/LT1168I
SYMBOL PARAMETER CONDITIONS (Note 6) MIN TYP MAX MIN TYP MAX UNITS
G Gain Range G = 1 + (49.4k/R
G
) 1 10k 1 10k
Gain Error G = 1 0.008 0.02 0.015 0.03 %
G = 10 (Note 7) 0.04 0.4 0.05 0.5 %
G = 100 (Note 7) 0.04 0.5 0.05 0.6 %
G = 1000 (Note 7) 0.08 0.5 0.08 0.6 %
Gain Nonlinearity (Notes 7, 8) V
O
= ±10V, G = 1 2 6 3 10 ppm
V
O
= ±10V,G = 10 and 100 10 20 15 25 ppm
V
O
= ±10V, G = 1000 20 40 25 60 ppm
V
O
= ±10V, G = 1, R
L
= 2k 4 15 5 20 ppm
V
O
= ±10V,G = 10 and 100, R
L
= 2k 20 40 30 60 ppm
V
O
= ±10V, G = 1000, R
L
= 2k 40 75 50 90 ppm
V
OST
Total Input Referred Offset Voltage V
OST
= V
OSI
+ V
OSO
/G
V
OSI
Input Offset Voltage G = 1000, V
S
= ±5V to ±15V 15 40 20 60 µV
V
OSO
Output Offset Voltage G = 1, V
S
= ±5V to ±15V 40 200 50 300 µV
I
OS
Input Offset Current 50 300 60 450 pA
I
B
Input Bias Current 40 250 80 500 pA
e
n
Input Noise Voltage, RTI 0.1Hz to 10Hz, G = 1 2.00 2.00 µV
P-P
0.1Hz to 10Hz, G = 1000 0.28 0.28 µV
P-P
Input Noise Voltage Density, RTI f
O
= 1kHz 10 15 10 15 nV/Hz
Output Noise Voltage Density, RTI f
O
= 1kHz (Note 9) 165 220 165 220 nV/Hz
i
n
Input Noise Current f
O
= 0.1Hz to 10Hz 5 5 pA
P-P
Input Noise Current Density f
O
= 10Hz 74 74 fA/Hz
R
IN
Input Resistance V
IN
= ±10V 300 1250 200 1250 G
L7 LINE/“2
3
LT1168
1168fa
LT1168AC LT1168C
SYMBOL PARAMETER CONDITIONS (Note 6) MIN TYP MAX MIN TYP MAX UNITS
Gain Error G = 1 0.01 0.03 0.012 0.04 %
G = 10 (Note 7) 0.40 1.5 0.500 1.6 %
G = 100 (Note 7) 0.45 1.6 0.550 1.7 %
G = 1000 (Note 7) 0.50 1.7 0.600 1.8 %
Gain Nonlinearity V
OUT
= ±10V, G = 1 2 15 3 20 ppm
(Notes 7, 8) V
OUT
= ±10V, G = 10 and 100 7 30 10 35 ppm
V
OUT
= ±10V, G = 1000 25 60 30 80 ppm
G/T Gain vs Temperature G < 1000 (Note 7) 100 200 100 200 ppm/°C
LT1168AC/LT1168AI LT1168C/LT1168I
SYMBOL PARAMETER CONDITIONS (Note 6) MIN TYP MAX MIN TYP MAX UNITS
C
IN(DIFF)
Differential Input Capacitance f
O
= 100kHz 1.6 1.6 pF
C
IN(CM)
Common Mode Input f
O
= 100kHz 1.6 1.6 pF
Capacitance
V
CM
Input Voltage Range G = 1, Other Input Grounded
V
S
= ±2.3V to ±5V –V
S
+ 1.9 +V
S
– 1.2 –V
S
+ 1.9 +V
S
– 1.2 V
V
S
= ±5V to ±18V –V
S
+ 1.9 +V
S
– 1.4 –V
S
+ 1.9 +V
S
– 1.4 V
CMRR Common Mode 1k Source Imbalance,
Rejection Ratio V
CM
= 0V to ±10V
G = 1 90 95 85 95 dB
G = 10 106 115 100 115 dB
G = 100 120 135 110 135 dB
G = 1000 126 140 120 140 dB
PSRR Power Supply V
S
= ±2.3V to ±18V
Rejection Ratio G = 1 103 108 100 108 dB
G = 10 122 128 118 128 dB
G = 100 131 145 126 145 dB
G = 1000 135 150 130 150 dB
I
S
Supply Current V
S
= ±2.3V to ±18V 350 530 350 530 µA
V
OUT
Output Voltage Swing R
L
= 10k
V
S
= ±2.3V to ±5V –V
S
+ 1.1 +V
S
– 1.2 –V
S
+ 1.1 +V
S
– 1.2 V
V
S
= ±5V to ±18V –V
S
+ 1.2 +V
S
– 1.3 –V
S
+ 1.2 +V
S
– 1.3 V
I
OUT
Output Current 20 32 20 32 mA
BW Bandwidth G = 1 400 400 kHz
G = 10 200 200 kHz
G = 100 13 13 kHz
G = 1000 1 1 kHz
SR Slew Rate G = 1, V
OUT
= ±10V 0.3 0.5 0.3 0.5 V/µs
Settling Time to 0.01% 10V Step
G = 1 to 100 30 30 µs
G = 1000 200 200 µs
REFIN Reference Input Resistance 60 60 k
I
REFIN
Reference Input Current V
REF
= 0V 18 18 µA
V
REF
Reference Voltage Range –V
S
+ 1.6 +V
S
– 1.6 –V
S
+ 1.6 +V
S
– 1.6 V
A
VREF
Reference Gain to Output 1 ± 0.0001 1 ± 0.0001
TA = 25°C. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted.
The denotes the specifications which apply over the 0°C TA 70°C temperature range. VS = ±15V, VCM = 0V, RL = 10k unless
otherwise noted.
ELECTRICAL CHARACTERISTICS
4
LT1168
1168fa
The denotes the specifications which apply over the 0°C TA 70°C
temperature range. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted.
The denotes the specifications which apply over the –40°C TA 85°C temperature range. VS = ±15V, VCM = 0V, RL = 10k unless
otherwise noted. (Note 8)
LT1168AI LT1168I
SYMBOL PARAMETER CONDITIONS (Note 6) MIN TYP MAX MIN TYP MAX UNITS
Gain Error G = 1 0.014 0.04 0.015 0.05 %
G = 10 (Note 7) 0.600 1.9 0.700 2.0 %
G = 100 (Note 7) 0.600 2.0 0.700 2.1 %
G = 1000 (Note 7) 0.600 2.1 0.700 2.2 %
G
N
Gain Nonlinearity V
O
= ±10V, G = 1 3 20 5 25 ppm
(Notes 7, 8) V
O
= ±10V, G = 10 and 100 10 35 15 40 ppm
VO = ±10V, G = 1000 30 70 35 100 ppm
G/T Gain vs Temperature G < 1000 (Note 7) 100 200 100 200 ppm/°C
LT1168AC LT1168C
SYMBOL PARAMETER CONDITIONS (Note 6) MIN TYP MAX MIN TYP MAX UNITS
V
OST
Total Input Referred Offset Voltage V
OST
= V
OSI
+ V
OSO
/G
V
OSI
Input Offset Voltage V
S
= ±5V to ±15V 18 60 23 80 µV
V
OSIH
Input Offset Voltage Hysteresis (Notes 7, 10) 3.0 3.0 µV
V
OSO
Output Offset Voltage V
S
= ±5V to ±15V 60 380 70 500 µV
V
OSOH
Output Offset Voltage Hysteresis (Notes 7, 10) 30 30 µV
V
OSI
/T Input Offset Drift (RTI) (Note 9) 0.05 0.3 0.06 0.4 µV/°C
V
OSO
/T Output Offset Drift (Note 9) 0.7 3 0.8 4 µV/°C
I
OS
Input Offset Current 100 400 120 550 pA
I
OS
/T Input Offset Current Drift 0.3 0.4 pA/°C
I
B
Input Bias Current 65 350 105 600 pA
I
B
/T Input Bias Current Drift 1.4 1.4 pA/°C
V
CM
Input Voltage Range G = 1, Other Input Grounded
V
S
= ±2.3V to ±5V –V
S
+ 2.1 +V
S
– 1.3 –V
S
+ 2.1 +V
S
– 1.3 V
V
S
= ±5V to ±18V –V
S
+ 2.1 +V
S
– 1.4 –V
S
+ 2.1 +V
S
– 1.4 V
CMRR Common Mode 1k Source Imbalance,
Rejection Ratio V
CM
= 0V to ±10V
G = 1 88 92 83 92 dB
G = 10 100 110 97 110 dB
G = 100 115 120 113 120 dB
G = 1000 117 135 114 135 dB
PSRR Power Supply V
S
= ±2.3V to ±18V
Rejection Ratio G = 1 102 115 98 115 dB
G = 10 123 130 118 130 dB
G = 100 127 135 124 135 dB
G = 1000 129 145 126 145 dB
I
S
Supply Current V
S
= ±2.3V to ±18V 390 615 390 615 µA
V
OUT
Output Voltage Swing R
L
= 10k
V
S
= ±2.3V to ±5V –V
S
+ 1.4 +V
S
– 1.3 –V
S
+ 1.4 +V
S
– 1.3 V
V
S
= ±5V to ±18V –V
S
+ 1.6 +V
S
– 1.5 –V
S
+ 1.6 +V
S
– 1.5 V
I
OUT
Output Current 16 25 16 25 mA
SR Slew Rate G = 1, V
OUT
= ±10V 0.25 0.48 0.25 0.48 V/µs
V
REF
Voltage Range (Note 9) –V
S
+ 1.6 +V
S
– 1.6 –V
S
+ 1.6 +V
S
– 1.6 V
ELECTRICAL CHARACTERISTICS
L7 LINE/“2
5
LT1168
1168fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: If the input voltage exceeds the supplies, the input current should
be limited to less than 20mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT1168AC/LT1168C are guaranteed functional over the
operating temperature range of –40°C and 85°C.
Note 5: The LT1168AC/LT1168C are guaranteed to meet specified
performance from 0°C to 70°C. The LT1168AC/LT1168C are designed,
characterized and expected to meet specified performance from –40°C
to 85°C but are not tested or QA sampled at these temperatures. The
LT1168AI/LT1168I are guaranteed to meet specified performance from
–40°C to 85°C.
Note 6: Typical parameters are defined as the 60% of the yield parameter
distribution.
Note 7: Does not include the tolerance of the external gain resistor R
G
.
Note 8: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
magnitude of these thermal effects are dependent on the package used,
heat sinking and air flow conditions.
Note 9: This parameter is not 100% tested.
Note 10: Hysteresis in offset voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Offset voltage hysteresis is always measured at 25°C, but
the IC is cycled to 85°C I-grade (or 70°C C-grade) or –40°C I-grade
(0°C C-grade) before successive measurement. 60% of the parts will
pass the typical limit on the data sheet.
The denotes the specifications which apply over the –40°C TA 85°C
temperature range. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. (Note 5)
ELECTRICAL CHARACTERISTICS
LT1168AI LT1168I
SYMBOL PARAMETER CONDITIONS (Note 6) MIN TYP MAX MIN TYP MAX UNITS
V
OST
Total Input Referred Offset Voltage V
OST
= V
OSI
+ V
OSO
/G
V
OSI
Input Offset Voltage 20 75 25 100 µV
V
OSIH
Input Offset Voltage Hysteresis (Notes 7, 10) 3.0 3.0 µV
V
OSO
Output Offset Voltage 180 500 200 600 µV
V
OSOH
Output Offset Voltage Hysteresis (Notes 7, 10) 30 30 µV
V
OSI
/T Input Offset Drift (RTI) (Note 9) 0.05 0.3 0.06 0.4 µV/°C
V
OSO
/T Output Offset Drift (Note 9) 0.8 5 1 6 µV/°C
I
OS
Input Offset Current 110 550 120 700 pA
I
OS
/T Input Offset Current Drift 0.3 0.3 pA/°C
I
B
Input Bias Current 120 500 220 800 pA
I
B
/T Input Bias Current Drift 1.4 1.4 pA/°C
V
CM
Input Voltage Range V
S
= ±2.3V to ±5V –V
S
+ 2.1 +V
S
– 1.3 –V
S
+ 2.1 +V
S
– 1.3 V
V
S
= ±5V to ±18V –V
S
+ 2.1 +V
S
– 1.4 –V
S
+ 2.1 +V
S
– 1.4 V
CMRR Common Mode 1k Source Imbalance,
Rejection Ratio V
CM
= 0V to ±10V
G = 1 86 90 81 90 dB
G = 10 98 105 95 105 dB
G = 100 114 118 112 118 dB
G = 1000 116 133 112 133 dB
PSRR Power Supply V
S
= ±2.3V to ±18V
Rejection Ratio G = 1 100 112 95 112 dB
G = 10 120 125 115 125 dB
G = 100 125 132 120 132 dB
G = 1000 128 140 125 140 dB
I
S
Supply Current 420 650 420 650 µA
V
OUT
Output Voltage Swing V
S
= ±2.3V to ±5V –V
S
+ 1.4 +V
S
– 1.3 –V
S
+ 1.4 +V
S
– 1.3 V
V
S
= ±5V to ±18V –V
S
+ 1.6 +V
S
– 1.5 –V
S
+ 1.6 +V
S
– 1.5 V
I
OUT
Output Current 15 22 15 22 mA
SR Slew Rate 0.22 0.41 0.22 0.42 V/µs
V
REF
Voltage Range (Note 9) –V
S
+ 1.6 +V
S
– 1.6 –V
S
+ 1.6 +V
S
– 1.6 V
CHANGE IN TOTAL INPUT REFERRED OFFSET VOLTAGE (“VI 35 an I 2 3 a 5 TIME AFTER POWERVON (MINUTES) GAIN ma) J JD FREQUENCY 1sz) qu quu quu qu Iu VOLTAGE NOISE DENSITV (NV/v z Ia GAIN = we quu “10 ‘k Wk FREQUENCV (Hz) In nsa L7 J EAR
6
LT1168
1168fa
Distribution of Input Offset
Voltage
Distribution of Output Offset
Voltage
Distribution of Output Offset
Voltage Drift
Distribution of Input Offset
Voltage Drift
Output Offset Voltage
Long-Term Drift
TYPICAL PERFOR A CE CHARACTERISTICS
UW
OUTPUT OFFSET VOLTAGE (µV)
150
0
PERCENT OF UNITS (%)
10
20
30
40
60
100 –50 0 50
1168 G01
100 150
50
5
15
25
35
55
45
VS = ±15V
TA = 25°C
G = 1
299 N8 (2 LOTS)
337 S0-8 (2 LOTS)
636 TOTAL PARTS
INPUT OFFSET VOLTAGE (µV)
–60
0
PERCENT OF UNITS (%)
10
20
30
40
60
–40 –20 0 20
1168 G02
40 60
50
5
15
25
35
55
45
VS = ±15V
TA = 25°C
G = 1000
299 N8 (2 LOTS)
337 S0-8 (2 LOTS)
636 TOTAL PARTS
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
1.8
0
PERCENT OF UNITS (%)
5
15
20
25
35
1168 G03
10
30
1.0 0.2
1.4 0.6 –0.2
V
S
= ±15V
T
A
= –40°C TO 85°C
G = 1
97 N8 (2 LOTS)
49 S0-8 (1 LOT)
146 TOTAL PARTS
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
0.45
0
PERCENT OF UNITS (%)
5
15
20
25
35
1168 G04
10
30
0.25 0.05
0.35 0.15 –0.05
97 N8 (2 LOTS)
49 S0-8 (1 LOT)
146 TOTAL PARTS
VS = ±15V
TA = –40°C TO 85°C
G = 1000
TIME (MONTHS)
0
–50
CHANGE IN OUTPUT OFFSET VOLTAGE (µV)
–30
–10
10
12
1168 G05
30
50
–40
–20
0
20
40
3
VS = ±15V
TA = 30°C
G = 1
4 PARTS FROM 4 LOTS
WARMED UP
Input Offset Voltage
Long-Term Drift
TIME (MONTHS)
0
–5
CHANGE IN INPUT OFFSET VOLTAGE (µV)
–3
–1
1
12
1168 G05
3
5
–4
–2
0
2
4
3
VS = ±15V
TA = 30°C
G = 1000
4 PARTS FROM 4 LOTS
WARMED UP
Warm-Up Drift Gain vs Frequency
Voltage Noise Density
vs Frequency
TIME AFTER POWER-ON (MINUTES)
012345
CHANGE IN TOTAL INPUT REFERRED
OFFSET VOLTAGE (µV)
1168 G07
35
30
25
20
15
10
5
0
SO-8
N-8
V
S
= ±15V
T
A
= 25°C
G = 1
FREQUENCY (kHz)
GAIN (dB)
1168 G08
0.01
60
50
40
30
20
10
0
–10
–20 1 100 10000.1 10
G = 1000
G = 100
G = 10
G = 1
V
S
= ±15V
T
A
= 25°C
FREQUENCY (Hz)
1 10 100 1k 10k 100k
1
VOLTAGE NOISE DENSITY (nV/Hz)
10
100
1000
1168 G09
V
S
= ±15V
T
A
= 25°C
1/f CORNER = 2Hz
GAIN = 1
GAIN = 10
GAIN = 100, 1000
1/f CORNER = 7Hz
1/f CORNER = 3Hz
BW LIMIT
GAIN = 1000
BW LIMIT
GAIN = 100
LT] 168 WPICHL pensonmnnce CHHBHCTEBISTICS NOISE VOLTAGE (ZIIV/DIV) NOISE CURRENT (SM/DIV) D.1Hzln 1DH1 Neise Vellage, G _ 1 v5=1I5v Trzzs’c I 2 a 4 5 5 7 TIME(SEC) a .1 Hz In 10H: Currenl Nnise vszmv TA = 2% I 2 a 4 5 5 7 TIME(SEC) a 9m 9m IO Inn CAPACITIVE LOAD (of) Iona quuu OUTPUT CURRENT (mm (SINRI OUTPU NOISE VOLTAGE (n zIIwva [1.1 HZ In 1DH1 Nnise Vellage, HTI G = 1000 V5=tl5v Trzzs’c I II 0‘23456789 TIME(SEC) In Sheri-Circuit Currenl vs 50 40 an 20 IO O v5 =1I5V Trance 40 720 730 740 750 n I 2 3 TIME FROM OUTPUT SHORT TO GROUND (MINUTES) Input Bias Currenl "a n 7200 420 740 40 I20 INPUT BIAS CURRENT (M) 200 IDDD CURRENT NOISE DENSITV (mm OUTRUT INIREDANOE( Inn IO Currenl Nnise Density vs Frequency 7RD v5=1I5v TA=25’C 4 III CORNER : 5st I IO Inn FREOUENOV (Hz) IDDD Oulpul Impedance vs Frequency Vs=tI5V TA 25’s G=ITOIDDD Ik Ink TOOK EREOUEncv (Hz) IM Inpul Dllsel Current I3 n 42a in 4n 0 an an INPUT OFFSET CURRENT (9A) I2 “5803 L7LJL1WW 7
7
LT1168
1168fa
0.1Hz to 10Hz Noise Voltage,
G = 1
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TIME (SEC)
0
NOISE VOLTAGE (2µV/DIV)
8
1168 G10
24510
6
139
7
V
S
= ±15V
T
A
= 25°C
0.1Hz to 10Hz Noise Voltage,
RTI G = 1000
TIME (SEC)
0
NOISE VOLTAGE (0.2µV/DIV)
8
1168 G11
24510
6
139
7
V
S
= ±15V
T
A
= 25°C
FREQUENCY (Hz)
1
10
CURRENT NOISE DENSITY (fA/Hz)
100
1000
10 100 1000
1168 G12
V
S
= ±15V
T
A
= 25°C
RS
1/f CORNER = 55Hz
Current Noise Density
vs Frequency
0.1Hz to 10Hz Current Noise
TIME (SEC)
0
NOISE CURRENT (5pA/DIV)
8
1168 G13
24510
6
139
7
V
S
= ±15V
T
A
= 25°C
Short-Circuit Current vs Time
TIME FROM OUTPUT SHORT TO GROUND (MINUTES)
0
–50
(SINK) (SOURCE)
OUTPUT CURRENT (mA)
–40
–20
–10
0
50
20
12
1168 G14
–30
30
40
10
3
T
A
= –40°C
V
S
= ±15V
T
A
= –40°C
T
A
= 25°C
T
A
= 85°C
T
A
= 85°C
T
A
= 25°C
Output Impedance vs Frequency
FREQUENCY (Hz)
1
OUTPUT IMPEDANCE ()
10
100
1k
10k 100k 1M
1168 G15
0.1
1k
V
S
= ±15V
T
A
= 25°C
G = 1 TO 1000
Overshoot vs Capacitive Load Input Bias Current Input Offset Current
CAPACITIVE LOAD (pF)
10
40
OVERSHOOT (%)
50
60
70
80
100 1000 10000
1168 G16
30
20
10
0
90
100
V
S
= ±15V
V
OUT
= ±50mV
R
L
=
G = 100, 1000
G = 10
G = 1
INPUT BIAS CURRENT (pA)
–200
OUTPUT VOLTAGE (V)
30
40
50
120
1168 G17
20
10
0–120
+I
B
+I
B
–I
B
–40 40 200
V
S
±15V
T
A
= 25°C
302 N8 (2 LOTS)
313 SO-8 (2 LOTS)
615 TOTAL PARTS
INPUT OFFSET CURRENT (pA)
–120
PERCENT OF UNITS (%)
30
40
50
40
1168 G18
20
10
0–80 –40 080 120
V
S
= ±15V
T
A
= 25°C
302 N8 (2 LOTS)
313 SO-8 (2 LOTS)
615 TOTAL PARTS
20 302 NE (2 Lo 8) Is LS 5073 (2 LCTsI EIETOTALPARTS g I2 3 RIM = 5m RINCM = mom 3 In E a E e 4 2 u u 4 a IZISZUZAZEBZSA CHANGE IN INPUT BIAS CURRENT (9A) Sellling Time (0.1%) vs Lead Capacitance 34 32 G=I FALLING EDGE’ 30 ,CzIIRI‘SINCEDCEfl i I I 1 23 7 g C, quEALLINC EDGEj : 25 ‘ i <5 5="" 24="" iszmu‘="" 79:“)="" 7="" e="" rising="" edge="" 7="" eallinc="" edge="" fi="" 22="" ‘="" £9qu="" i’nisincedce="" ’="" in="" an="" icc="" 300="" load="" capacitance="" (pr)="" mun="" rising="" edge="" settling="" time="" (0.10%)="" cm="" 005="" cid="" tonum="" w="" vcui="" uv—i—="" mama/i,="" d="" tdui‘vc="" i="" s="" in="" i2="" i4="" tc="" tc="" 20="" 22="" 24="" 25="" 23="" an="" 32="" settling="" time="" (us)="" input="" bias="" and="" oilsel="" currenl="" vs="" temperature="" 500="" man="" 300="" 200="" inn="" 0="" 7="" i="" an="" 7200="" 7300="" 7400="" v5="" :isv="" v5="" v="" input="" bias="" and="" offset="" current="" (pm="" a="" 775="" fan="" 725="" ii="" 25="" sd="" 75="" h10="" ‘25="" temperature="" settling="" time="" in.n1%)="" vs="" load="" capacitance="" 35="" i="" i="" z="" szn.="" 34="" *ealewhdgew="" irisinceucei="" i="" 32="" i="" m="" a="" cziirisinceuce="" ;="" 3="" an="" ‘="" %="" e="" e="" 23="" j="" g="" szioieallinced="" e="" ‘="" e="" 25="" i="" i="" e="" 24="" ,gmo‘risingedgej="" gei="" 7="" w="" falling="" 22="" 7="" edge="" i="" 20="" m="" stepsize="IOV" in="" an="" inn="" 300="" load="" capacitance="" (pf)="" i000="" i000="" sewling="" time="" (ms)="" peak-to-peak="" output="" swing="" (vi="" i00="" i0="" inn="" inn="" gain="" i="" i0="" frequency="" (khz)="" inn="" inn="" was="" l7="" hhs/5r="">
8
LT1168
1168fa
Change in Input Bias Current for
VCM = 20V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Settling Time vs Step Size Settling Time vs Gain
CHANGE IN INPUT BIAS CURRENT (pA)
0
0
PERCENT OF UNITS (%)
2
6
8
10
20
14
816 20 34
1168 G19
4
16
18
12
412 24 28 32
V
S
= ±15V
V
CM
= ±10V
T
A
= 25°C
302 N8 (2 LOTS)
313 SO-8 (2 LOTS)
615 TOTAL PARTS
R
INCM
= 5TR
INCM
= 700G
GAIN
1
1
SETTLING TIME (µs)
10
100
1000
10 100 1000
1168 G21
VS = ±15V
TA = 25°C
VOUT = 10V TO 0.01%
Settling Time (0.1%)
vs Load Capacitance
LOAD CAPACITANCE (pF)
10
SETTLING TIME (µs)
34
32
30
28
26
24
22
20
18
16
1168 G22
30 100 300 1000
G = 10,
FALLING EDGE
G = 10,
RISING EDGE
G = 1, FALLING EDGE
G = 1, RISING EDGE
G = 100,
RISING EDGE
G = 100, FALLING EDGE
V
S
= ±15V
T
A
= 25°C
R
L
= 1k
STEP SIZE = 10V
Falling Edge Settling Time
(0.10%)
V
IN
(V)
5µs/DIV 1168 G24
V
OUT
(V)
0
–5
–10
0
–5
–10
0.10
0.05
0.05
0.10
SETTLING (%)
0
Input Bias and Offset Current
vs Temperature
TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
INPUT BIAS AND OFFSET CURRENT (pA)
1168 G23
500
400
300
200
100
0
100
200
300
400
500
V
S
= ±15V
V
CM
= 0V
I
OS
I
B
T
A
= 25°C
V
S
= ±15V
R
L
= 2k
C
L
= 15pF
t = 0
Rising Edge Settling Time
(0.10%)
V
IN
(V)
5µs/DIV 1168 G25
V
OUT
(V)
10
5
0
10
5
0
0.10
0.05
0.05
0.10
SETTLING (%)
0
T
A
= 25°C
V
S
= ±15V
R
L
= 2k
C
L
= 15pF
t = 0
LOAD CAPACITANCE (pF)
10
SETTLING TIME (µs)
36
34
32
30
28
26
24
22
20
18
1168 G26
30 100 300 1000
G = 100,
FALLING EDGE
G = 1, RISING EDGE
G = 100,
RISING EDGE
G = 10, RISING EDGE G = 1,
FALLING
EDGE
G = 10, FALLING EDGE
V
S
= ±15V
T
A
= 25°C
R
L
= 1k
STEP SIZE = 10V
FREQUENCY (kHz)
1
PEAK-TO-PEAK OUTPUT SWING (V)
10 100 1000
1168 G27
35
30
25
20
15
10
5
0
VS = ±15V
TA = 25°C
G = 10, 100, 1000
G = 1
Settling Time (0.01%)
vs Load Capacitance
Undistorted Output Swing
vs Frequency
SETTLING TIME (µs)
8 101214161820222426283032
OUTPUT STEP (V)
2
6
10
1168 G20
–2
–6
0
4
8
–4
–8
–10
0V V
OUT
TO 0.1%
TO 0.1%
TO 0.01%
TO 0.01%
0V V
OUT
V
S
= ±15
G = 1
T
A
= 25°C
C
L
= 30pF
R
L
= 1k
.vs onsius Sfigovsim gg§0V5iV5 a; “0V5izfl $3 ovsizs 53 $9 rVSoZS éE g: g vsns x =5 vsnn *VsoUS *Vs um 01 1 m mm 45 4| 77 ,3 3 7 u 15 ouwun CURRENT (mm VuuT( ) Dulnul Shon-Circuil Currenl vs Temneralure Slew Hale vs Temneralure an v5=115v ‘0 wsv \ 50 HE E A v \ swmnscunnEm 3 / g 40 \ 5 as / K m E \ \ E fik/ismw 3 an 3 n4 / 2 \ m n SOURCINGCURRENT 4 E m 3 \ 20 M m n 750 725 u 25 50 75 um 750 725 u 25 50 75 w TEMPERATURE (we) TEMPERATURE «m Large-signal Transient Respnnse Small-Signal Transient Resnnnse Large-Signal Tran m 10.5 V—\ SV/DW ZUmV/DW SV/UW fiflysy‘DW VDys/DN L7LJL1WW
9
LT1168
1168fa
OUTPUT CURRENT (mA)
(SINK) (SOURCE)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGE
+VS
–VS
–VS + 0.5
–VS + 1.0
–VS + 1.5
–VS + 2.0
–VS + 2.5
+VS – 2.5
+VS – 2.0
+VS – 1.5
+VS – 1.0
+VS – 0.5
0.01 1 10 100
1168 G28
0.1
VS = ±15V 85°C
25°C
–40°C
Large-Signal Transient Response
50µs/DIV
G = 10
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
5V/DIV
1168 G33
50µs/DIV
Large-Signal Transient Response
G = 1
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
5V/DIV
1168 G31
Small-Signal Transient Response
10µs/DIV
G = 1
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
20mV/DIV
1168 G32
Output Voltage Swing vs
Load Current
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
50 –25
10
OUTPUT CURRENT (mA)
30
60
050 75
1168 G29
20
50
40
25 100
VS = ±15V
SINKING CURRENT
SOURCING CURRENT
TEMPERATURE (°C)
50 –25
0
SLEW RATE (V/µs)
0.4
1.0
050 75
1168 G30
0.2
0.8
0.6
25 100
VS = ±15V
VOUT = ±10V
G = 1
+SLEW SLEW
Output Short-Circuit Current
vs Temperature Slew Rate vs Temperature
V
OUT
(V)
–15
INPUT VOLTAGE RANGE WITH RESPECT TO
NEGATIVE SUPPLY (–V
S
+ V
IN
)
INPUT VOLTAGE RANGE WITH RESPECT TO
POSITIVE SUPPLY (+V
S
– V
IN
)
9
12
15
14
13
10
11
7
8
4
5
1
2
–3 7
1168 G43
6
3
0
–6
–3
0
–1
–2
–5
–4
–8
–7
–11
–10
–14
–13
–9
–12
–15
–11 –7 311 15
+V
CM
= +V
S
– 1.4V
–V
CM
= –V
S
+ 1.9V
V
OUT
= +V
S
– 1.3V
V
OUT
= –V
S
+ 1.2V
V
S
= ±15V
T
A
= 25°C
G = 1
G = 1
G = 100
G = 100
G = 10
G = 2
G = 2
G = 10
Input Voltage Range vs Output
Voltage for Various Gains
RL=2k mzzx spannr CHEW z m I nu ma 1k m mu EREouENmHz) g 150 ‘60 HE E m '43 W E 9 as E m E Vzu E E V a mu 5 mu E 0 a u. g m / L: L: > an fi EU I / E r: a / 2 an B an 3 “3 1‘ g E 2 g 4n 5 Au w m 3. E v am 5 20 v5 :ISV é 2“ 1:450 a TA 25% Q wsouacEIMaALANcE E n m UV I ‘0 I00 1k Wk Iflflk U] V I0 ‘00 Vk Wk WM ’50 ’25 U 25 50 75 IUD 12 FREQUENCV (Hz) EnEquch (Hz) TEMPERATURE we) n53! L7 J EAR _L O
10
LT1168
1168fa
200µs/DIV
Large-Signal Transient Response
G = 1000
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
5V/DIV
1168 G37
Small-Signal Transient Response
200µs/DIV
G = 1000
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
20mV/DIV
1168 G38
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Negative Power Supply Rejection
Ratio vs Frequency
FREQUENCY (Hz)
0.1 1 10 100 1k 10k 100k
NEGATIVE POWR SUPPLY REJECTION RATIO (dB)
1168 G39
160
140
120
100
80
60
40
20
0
G = 1000
G = 100
G = 10
G = 1
V
S
= ±15V
T
A
= 25°C
Positive Power Supply Rejection
Ratio vs Frequency
FREQUENCY (Hz)
0.1 1 10 100 1k 10k 100k
POSITIVE POWR SUPPLY REJECTION RATIO (dB)
1168 G40
160
140
120
100
80
60
40
20
0
G = 1000
G = 100
G = 10
G = 1
VS = ±15V
TA = 25°C
FREQUENCY (Hz)
0.1 1 10 100 1k 10k 100k
COMMON MODE REJECTION RATIO (dB)
1168 G41
160
140
120
100
80
60
40
20
0
G = 1000
G = 100
G = 10
G = 1
VS = ±15V
TA = 25°C
1k SOURCE IMBALANCE
TEMPERATURE (°C)
50 –25
0.1
SUPPLY CURRENT (mA)
0.3
0.6
050 75
1168 G42
0.2
0.5
0.4
25 100 125
V
S
= ±15V
Common Mode Rejection Ratio vs
Frequency (1k Source Imbalance) Supply Current vs Temperature
Large-Signal Transient Response
50µs/DIV
G = 100
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
5V/DIV
1168 G35
Small-Signal Transient Response
10µs/DIV
G = 100
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
20mV/DIV
1168 G36
20mV/DIV
Small-Signal Transient Response
10µs/DIV
G = 10
V
S
= ±15V
R
L
= 2k
C
L
= 60pF
1168 G34
. m H + W M Ran—69 : + 5|]— : i—i 4) L1 : M M L a | M f II + + M —n (P —|:| PREAMP STAGE E D‘FFERENCE AMPUFIER STAGE L7LJIJNW
11
LT1168
1168fa
BLOCK DIAGRA
W
Q1
RG
2
OUTPUT
6
REF
1168 F01
5
7
+
A1
+
A3
VB
R1
24.7k
R3
400
R4
400
C1
1
RG8
R7
30k
R8
30k
R5
30k
R6
30k
DIFFERENCE AMPLIFIER STAGEPREAMP STAGE
+IN
–IN
3
+
A2
VB
R2
24.7k
C2
+VS
–VS
–VS
+VS
–VS
Q2 –VS
+VS
4–VS
Figure 1. Block Diagram
The LT1168 is a modified version of the three op amp
instrumentation amplifier. Laser trimming and monolithic
construction allow tight matching and tracking of circuit
parameters over the specified temperature range. Refer to
the block diagram (Figure 1) to understand the following
circuit description. The collector currents in Q1 and Q2 are
trimmed to minimize offset voltage drift, thus assuring a
high level of performance. R1 and R2 are trimmed to an
absolute value of 24.7k to assure that the gain can be set
accurately (0.6% at G = 100) with only one external
resistor R
G
. The value of R
G
in parallel with R1 (R2)
determines the transconductance of the preamp stage. As
R
G
is reduced for larger programmed gains, the transcon-
ductance of the input preamp stage increases to that of the
input transistors Q1 and Q2. This increases the open-loop
gain when the programmed gain is increased, reducing
the input referred gain related errors and noise. The input
voltage noise at gains greater than 50 is determined only
by Q1 and Q2. At lower gains the noise of the difference
amplifier and preamp gain setting resistors increase the
noise. The gain bandwidth product is determined by C1,
C2 and the preamp transconductance which increases
with programmed gain. Therefore, the bandwidth does not
drop proportionally with gain.
The input transistors Q1 and Q2 offer excellent matching,
which is inherent in NPN bipolar transistors, as well as
picoampere input bias current due to superbeta process-
ing. The collector currents in Q1 and Q2 are held constant
due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop which in turn impresses the differential
input voltage across the external gain set resistor R
G
.
Since the current that flows through R
G
also flows through
R1 and R2, the ratios provide a gained-up differential
THEORY OF OPERATIO
U
12
LT1168
1168fa
voltage, G = (R1 + R2)/R
G
, to the unity-gain difference
amplifier A3. The common mode voltage is removed by
A3, resulting in a single-ended output voltage referenced
to the voltage on the REF pin. The resulting gain equation
is:
G = (49.4k/R
G
) + 1
solving for the gain set resistor gives:
R
G
= 49.4k/(G – 1)
Table 1 shows appropriate 1% resistor values for a variety
of gains.
Table 1
DESIRED GAIN R
G
CLOSEST 1% VALUE RESULTANT GAIN
1 Open Open 1
2 49400499001.99
5 12350124004.984
10 5488.8954909.998
20 2600261019.93
50 1008.16100050.4
100 498.9949999.998
200 248.24249199.4
500 99100495
1000 49.9549.41001
Input and Output Offset Voltage
The offset voltage of the LT1168 has two components: the
output offset and the input offset. The total offset voltage
referred to the input (RTI) is found by dividing the output
offset by the programmed gain (G) and adding it to the
input offset. At high gains the input offset voltage domi-
nates, whereas at low gains the output offset voltage
dominates. The total offset voltage is:
Total input offset voltage (RTI)
= input offset + (output offset/G)
Total output offset voltage (RTO)
= (input offset • G) + output offset
Reference Terminal
The reference terminal is one end of one of the four 30k
resistors around the difference amplifier. The output
voltage of the LT1168 (Pin 6) is referenced to the voltage
on the reference terminal (Pin 5). Resistance in series
with the REF pin must be minimized for best common
mode rejection. For example, a 6 resistance from the
REF pin to ground will not only increase the gain error by
0.02% but will lower the CMRR to 80dB.
Input Voltage Range
The input voltage range for the LT1168 is specified in the
data sheet at 1.4V below the positive supply to 1.9V
above the negative supply for a gain of one. As the gain
increases the input voltage range decreases. This is due
to the IR drop across the internal gain resistors R1 and
R2 in Figure 1. For the unity gain condition there is no IR
drop across the gain resistors R1 and R2, the output of
the GM amplifiers is just the differential input voltage at
Pin 2 and Pin 3 (level shifted by one V
BE
from Q1 and Q2).
When a gain resistor is connected across Pins 1 and 8,
the output swing of the GM cells is now the differential
input voltage (level shifted by V
BE
) plus the differential
voltage times the gain (ratio of the internal gain resistors
to the external gain resistor across Pins 1 and 8). To
calculate how close to the positive rail the input (V
IN
) can
swing for a gain of 2 and a maximum expected output
swing of 10V, use the following equation:
+V
S
– V
IN
= –0.5 – (V
OUT
/G) • (G – 1)/2
Substituting yields:
0.5 – (10/2) • (1/2) = –3V
below the positive supply or 12V for a 15V supply. To
calculate how far above the negative supply the input can
swing for a gain of 10 with a maximum expected output
swing of –10V, the equation for the negative case is:
–V
S
+ V
IN
= 1.5 – (V
OUT
/G) • (G – 1)/2
Substituting yields:
1.5 – (–10/10) • 9/2 = 6V
above the negative supply or –9V for a negative supply
voltage of –15V. Figures 2 and 3 are for the positive
common mode and negative common mode cases
respectively.
THEORY OF OPERATIO
U
\ \ \ o = 2 ,AREA OF \/ OPERATlON c = mm c m i AREA oE = OPERATION AREA 0‘ ‘ ‘ OPERA'HDN z 251p PUT coMMou ooE RANGE is *3 U 2 4 5 8 vim 1V) TA =25’c , ilNPUT coMMou / MODE RANGE is ’ AaovE THE cuRv c = mu AREA or i \ 4 OPERATION o z 2 \ AREA oE OPERATlON / \ l l l Single Supply Operation Forbest results undersingle supply operatio should be raised abovethe negativesupply(P of the inputs should be at least 2.5V above barometerapplication laterinthisdata sheet that satisfies these conditions. The resistan the bridgetransducerto ground setsthe ope forthe bridgeandWith R6,also hastheeffec input common mode voltage. The output of always inSide the specified range since th pressure rarely goes low enoughto cause the (30.00 inches of Hg corresponds to 3.000V) tions that require the output to swmg at or b L7LJL1WW lF‘MTl
13
LT1168
1168fa
Single Supply Operation
For best results under single supply operation, the REF pin
should be raised above the negative supply (Pin 4) and one
of the inputs should be at least 2.5V above ground. The
barometer application later in this data sheet is an example
that satisfies these conditions. The resistance R
SET
from
the bridge transducer to ground sets the operating current
for the bridge, and with R6, also has the effect of raising the
input common mode voltage. The output of the LT1168 is
always inside the specified range since the barometric
pressure rarely goes low enough to cause the output to clip
(30.00 inches of Hg corresponds to 3.000V). For applica-
tions that require the output to swing at or below the REF
V
OUT
(V)
0
INPUT VOLTAGE WITH RESPECT
TO POSITIVE SUPPLY (+V
S
– V
IN
)(V)
–1
6
1168 F02
–4
–6
24 8
–7
–8
+V
S
–2
–3
–5
10 12 14
G = 2
AREA OF
OPERATION
T
A
= 25°C
INPUT COMMON
MODE RANGE IS
BELOW THE CURVE
G = 100
AREA OF
OPERATION
G = 1
AREA OF OPERATION
G = 10
AREA OF
OPERATION
Figure 2. Positive Input Range vs
Output Voltage for Different Gains
V
OUT
(V)
–14
–V
S
1
3
4
5
–4 –2–6
9
1168 F03
2
–10 –8–12 0
6
7
8
INPUT VOLTAGE RANGE WITH RESPECT
TO NEGATIVE SUPPLY (–V
S
+ V
IN
)(V)
T
A
= 25°C
INPUT COMMON
MODE RANGE IS
ABOVE THE CURVE
G = 2
AREA OF
OPERATION
G = 100
AREA OF
OPERATION
G = 10
AREA OF
OPERATION
G = 1
AREA OF OPERATION
Figure 4. Optional Trimming of Output Offset Voltage
Figure 3. Negative Input Voltage Range
vs Output Voltage for Various Gains
potential, the voltage on the REF pin can be further level
shifted. The application in the front of this data sheet,
Single Supply Pressure Monitor, is an example. An op amp
is used to buffer the voltage on the REF pin since a parasitic
series resistance will degrade the CMRR.
Output Offset Trimming
The LT1168 is laser trimmed for low offset voltage so that
no external offset trimming is required for most applica-
tions. In the event that the offset needs to be adjusted, the
circuit in Figure 4 is an example of an optional offset adjust
circuit. The op amp buffer provides a low impedance to the
REF pin where resistance must be kept to minimum for
best CMRR and lowest gain error.
Input Bias Current Return Path
The low input bias current of the LT1168 (250pA) and the
high input impedance (200G) allow the use of high
impedance sources without introducing additional offset
voltage errors, even when the full common mode range is
required. However, a path must be provided for the input
bias currents of both inputs when a purely differential
signal is being amplified. Without this path the inputs will
float to either rail and exceed the input common mode
range of the LT1168, resulting in a saturated input stage.
Figure 5 shows three examples of an input bias current
THEORY OF OPERATIO
U
@> {p w IIIII L7 HHS/5R
14
LT1168
1168fa
The LT1168 is a low power precision instrumentation
amplifier that requires only one external resistor to accu-
rately set the gain anywhere from 1 to 1000. The LT1168
is trimmed for critical DC parameters such as gain error
(0.04%, G = 10), input offset voltage (40µV, RTI), CMRR
(90dB min, G = 1) and PSRR (103dB min, G = 1). These
trims allow the amplifier to achieve very high DC accuracy.
The LT1168 achieves low input bias current of just 250pA
(max) through the use of superbeta processing. The
output can handle capacitive loads up to 1000pF in any
gain configuration and the inputs are protected against
ESD strikes up to ±13kV (human body).
Input Protection
The LT1168 can safely handle up to ±20mA of input
current in an overload condition. Adding an external 5k
input resistor in series with each input allows DC input
fault voltage up to ±100V and improves the ESD immunity
to ±8kV (contact) and ±15kV (air discharge), which is the
IEC 1000-4-2 level 4 specification. If lower value input
resistors must be used, a clamp diode from the positive
supply to each input will maintain the IEC 1000-4-2
specification to level 4 for both air and contact discharge.
A 2N4393 drain/source to gate is a good low leakage diode
for use with resistors between 1k and 20k, see Figure 6.
The input resistors should be carbon and not metal film or
carbon film in order to withstand the fault conditions.
path. The first example is of a purely differential signal
source with a 10k input current path to ground. Since the
impedance of the signal source is low, only one resistor is
needed. Two matching resistors are needed for higher
impedance signal sources as shown in the second
example. Balancing the input impedance improves both
common mode rejection and DC offset.
Figure 5. Providing an Input Common Mode Current Path
10k
1168 F05
THERMOCOUPLE
200k
MICROPHONE,
HYDROPHONE,
ETC
200k
CENTER-TAP PROVIDES
BIAS CURRENT RETURN
+
LT1168
+
LT1168
+
LT1168
Figure 6. Input Protection
APPLICATIO S I FOR ATIO
WUUU
–V
S
1168 F06
+V
S
J2
2N4393
J1
2N4393
OUT
OPTIONAL FOR
R
IN
< 20k
R
G
R
IN
R
IN
+
LT1168 REF
RFI Reduction
In many industrial and data acquisition applications,
instrumentation amplifiers are used to accurately amplify
small signals in the presence of large common mode
THEORY OF OPERATIO
U
L7LJL1WW
15
LT1168
1168fa
voltages or high levels of noise. Typically, the sources of
these very small signals (on the order of microvolts or
millivolts) are sensors that can be a significant distance
from the signal conditioning circuit. Although these sen-
sors may be connected to signal conditioning circuitry,
using shielded or unshielded twisted-pair cabling, the ca-
bling may act as antennae, conveying very high frequency
interference directly into the input stage of the LT1168.
The amplitude and frequency of the interference can have
an adverse effect on an instrumentation amplifier’s input
stage by causing an unwanted DC shift in the amplifier’s
input offset voltage. This well known effect is called RFI
rectification and is produced when out-of-band interfer-
ence is coupled (inductively, capacitively or via radiation)
and rectified by the instrumentation amplifier’s input tran-
sistors. These transistors act as high frequency signal
detectors, in the same way diodes were used as RF
envelope detectors in early radio designs. Regardless of
the type of interference or the method by which it is
coupled into the circuit, an out-of-band error signal ap-
pears in series with the instrumentation amplifier’s inputs.
To significantly reduce the effect of these out-of-band
signals on the input offset voltage of instrumentation
amplifiers, simple lowpass filters can be used at the
inputs. This filter should be located very close to the input
pins of the circuit. An effective filter configuration is
illustrated in Figure 7, where three capacitors have been
added to the inputs of the LT1168. Capacitors C
XCM1
and
C
XCM2
form lowpass filters with the external series resis-
tors R
S1, 2
to any out-of-band signal appearing on each of
the input traces. Capacitor C
XD
forms a filter to reduce any
unwanted signal that would appear across the input traces.
An added benefit to using C
XD
is that the circuit’s AC
common mode rejection is not degraded due to common
mode capacitive imbalance. The differential mode and
common mode time constants associated with the capaci-
tors are:
t
DM(LPF)
= (R
S1
+ R
S2
)(C
XD
+ C
XCM1
+ C
XCM2
)
t
CM(LPF)
= (R
S1
|| R
S2
)(C
XCM1
+
C
XCM2
)
Setting the time constants requires a knowledge of the
frequency, or frequencies of the interference. Once this
frequency is known, the common mode time constants
can be set followed by the differential mode time constant.
To avoid any possibility of inadvertently affecting the
signal to be processed, set the common mode time
constant an order of magnitude (or more) smaller than the
differential mode time constant. Set the common mode
time constants such that they do not degrade the LT1168
inherent AC CMR. Then the differential mode time con-
stant can be set for the bandwidth required for the appli-
cation. Setting the differential mode time constant close to
the sensor’s BW also minimizes any noise pickup along
the leads. To avoid any possibility of common mode to
differential mode signal conversion, match the common
mode time constants to 1% or better. If the sensor is an
RTD or a resistive strain gauge and is in proximity to the
instrumentation amplifier, then the series resistors R
S1, 2
can be omitted.
Figure 7. Adding a Simple RC Filter at the Inputs to an
Instrumentation Amplifier is Effective in Reducing Rectification
of High Frequency Out-of-Band Signals
APPLICATIO S I FOR ATIO
WUUU
–V
S
+V
S
IN
+
IN
1168 F07
V
OUT
R
G
C
XCM1
0.001µF
C
XCM2
0.001µF
C
XD
0.1µF
R
S1
1.6k
R
S2
1.6k
EXTERNAL RFI
FILTER
+
LT1168
f
3dB
500Hz
Nerve Impulse Amplifier
The LT1168’s low current noise makes it ideal for EMG
monitors that have high source impedances. Demonstrat-
ing the LT1168’s ability to amplify low level signals, the
circuit in Figure 8 takes advantage of the amplifier’s high
gain and low noise operation. This circuit amplifies the low
level nerve impulse signals received from a patient at
Pins 2 and 3. R
G
and the parallel combination of R3 and R4
set a gain of ten. The potential on LT1112’s Pin 1 creates
PATiENT/CiRCUiT 3v L‘msa G=Tfl u 3H1 /HiGHPASS OUTPUT — W/mV 73v PROTECTTON/TSOLATTON 3 AM a 0‘ F R 0 Dip i T2k R2 TM PATTENT GND AV = mi ,‘N PULE AT Tm 45v TfinF Figure B. Nerve Impulse Amp 49 m2 Figure 9. Precisinn Temperature Wiihnui Precision Resisiars 16 was \mw IL // \\‘ \ / *YSH‘NDDE \ \ \\ vsmaau / / u 740 720 u 20 40 an an Tun T2 TEMPERATURE (7(3) Figure 1|]. Response pl Figure 9 [or Varinus T L7 HHS/5R
16
LT1168
1168fa
a ground for the common mode signal. C1 was chosen to
maintain the stability of the patient ground. The LT1168’s
high CMRR ensures that the desired differential signal is
amplified and unwanted common mode signals are at-
tenuated. Since the DC portion of the signal is not impor-
tant, R6 and C2 make up a 0.3Hz highpass filter. The AC
signal at LT1112’s Pin 5 is amplified by a gain of 101 set
by R7/R8 +1. The parallel combination of C3 and R7 form
a lowpass filter that decreases this gain at frequencies
above 1kHz. The ability to operate at ±3V on 350µA of
supply current makes the LT1168 ideal for battery-pow-
ered applications. Total supply current for this application
is 1.05mA. Proper safeguards, such as isolation, must be
added to this circuit to protect the patient from possible
harm.
Low I
B
Favors High Impedance Bridges, Lowers
Dissipation
The LT1168’s low supply current, low supply voltage
operation and low input bias currents allow it to fit nicely
into battery-powered applications. Low overall power
dissipation necessitates using higher impedance bridges.
The single supply pressure monitor application on the
front of this data sheet, shows the LT1168 connected to
the differential output of a 3.5k bridge. The picoampere
input bias currents keep the error caused by offset current
to a negligible level. The LT1112 level shifts the LT1168’s
reference pin and the ADC’s analog ground pins above
ground. The LT1168’s and LT1112’s combined power
dissipation is still less than the bridge’s. This circuit’s total
supply current is just 2.2mA.
Figure 8. Nerve Impulse Amplifier
APPLICATIO S I FOR ATIO
WUUU
2
2
–IN
PATIENT
GND
OUTPUT
1V/mV
+IN
1
1
8
R6
1M
R7
10k
R8
100
1168 F08
A
V
= 101
POLE AT 1kHz
5
5
4
–3V
–3V
3V
3V
7
68
4
7
6
+
1/2
LT1112
1/2
LT1112
R4
30k
R3
30k
R1
12k
C1
0.01µF
R
G
6k
3
3
R2
1M
C2
0.47µF
0.3Hz
HIGHPASS
C3
15nF
PATIENT/CIRCUIT
PROTECTION/ISOLATION
+
LT1168
G = 10
+
Figure 9. Precision Temperature Without Precision Resistors
1168 F09
15V
15V
15V
649.4k
R
T
V
OUT
= 1.25 •
7
3
8
1
24
22kLT1634-1.25
PRECISION
THERMISTOR
5
R
T
+
LT1168 REF
Figure 10. Response of Figure 9 for Various Thermistors
TEMPERATURE (°C)
–40
OUTPUT VOLTAGE (V)
8
10
12
80 100
1168 F10
6
4
020 20 40 60 120
2
0
14
YSI #44006
YSI #44011
THERMOMETRICS
DC95F103W
THERMO
METRICS
DC95G104Z
\W‘ L7LJL1W _
17
LT1168
1168fa
Single Supply Barometer
TYPICAL APPLICATIO S
U
+
+
+
2
1
1
1
2
1
R5
200k
R4
50k
R3
50k
R8
100k
R6
1k
LT1634CCZ-1.25
8
4
1/2
LT1490
3
RSET
0.6% ACCURACY AT 25°C
1.7% ACCURACY AT 0°C TO 60°C
VS = 8V TO 30V
5k
5k
5k
5k
VS
5
4
3
2
+7
1/2
LT1490
5
6
2
8
LUCAS NOVA SENOR
NPC-1220-015-A-3L
7
VS
6
1168 TA03
5TO
4-DIGIT
DVM
4
R2
12
LT1168
G = 60
R1
825
3
6
R7
50k VOLTS
2.800
3.000
3.200
INCHES Hg
28.00
30.00
32.00
2
–IN
OUTPUT
+IN
1
8R1
1M
1168 TA02
2
3
5
6
6
C1
0.1µF
+
LT1677
R
G
3
f
3dB
= 1
(2π)(R1)(C1)
= 1.59Hz
+
LT1168
REF
AC Coupled Instrumentation Amplifier
L7 HHS/5R
18
LT1168
1168fa
4-Digit Pressure Sensor
TYPICAL APPLICATIO S
U
+
+
2
1
1
1
2
1
R8
392k
LT1634CCZ-1.25
4
11
1/4
LT1114
+
1/4
LT1114
3
5k
5k
5k
5k
9V
9V
5
4
3
2
28
LUCAS NOVA SENOR
NPC-1220-015A-3L
7
6
1168 TA04
5TO
4-DIGIT
DVM
4
8
R5
100k
R3
51k
R4
100k
R1
825
R2
12
C1
1µF
R9
1k
R
SET
R6
50k
R7
180k
3
12
14
13
6
+
1/4
LT1114
10
9
+
LT1168
G = 60
0.6% ACCURACY AT ROOM TEMP
1.7% ACCURACY AT 0°C TO 60°C
VOLTS
2.800
3.000
3.200
INCHES Hg
28.00
30.00
32.00
sun , 325 4, WWI—lm D mmmm ms, 055 P i (ll-13465” ‘ l l l mas J 7 U 55‘) — w \ SH Package B-Lead Plastic Small Dulline (Narrow 0.150) 1E1 El: um: RECOMMENDED mm my mum mu (0254 an m (a 203 7 9 25m L7LJL1WW Hnwevev unvesnnnsl 7 nm 415nm Mya‘ me DWG # usrusr1s1m 13H HH nus my 2» (5 7m 75 my l 2 a 4 user 069 n my l 7521 TVP mnmmannn mmsneu by Lmeav Tammany Cmpovalmn l5 believed m he aumale an w ‘5 assumed my us use LmearTenhnnlogy Commune" makes no lalmnmamamlemonnemonomsmmmlsasdescvmeunavemvmlnulmmngaanexlslmgna
19
LT1168
1168fa
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
Dimensions in inches (millimeters) unless otherwise noted.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
.120
(3.048)
MIN
12 34
87 65
.255 ± .015*
(6.477 ± 0.381)
.400*
(10.160)
MAX
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
MEV nsv rt 5v COMMENTS n Butldtng Block Swnched Capacttor RalHorRatl tnput tZDdB C Instrumentation Amptmer G :10m100,v03:10uv‘ IB:50pA Suppty tnstrumentalton Amplmer tlun Amptmer G:100r100,|5:t05tm G :10 ur100, Slew Rate :SDV/us PlBCtSID" tnstrumentalton Amplmer Lower Norse than LTttSE‘ 9N : 7 EnV/V‘W Corporation 95035-7417 AX (403)43470507 - www hneantecncom LT/Lwt U905 REV A - PR L7 HHS/5R ‘ UNEAR TECHNOLOGV cons
20
LT1168
1168fa
LT/LWI 0906 REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2000
PART NUMBER DESCRIPTION COMMENTS
LTC1043 Dual Precision Instrumentation Building Block Switched Capacitor, Rail-to-Rail Input, 120dB CMRR
LTC1100 Precision Chopper-Stabilized Instrumentation Amplifier G = 10 or 100, V
OS
= 10µV, I
B
= 50pA
LT1101 Precision, Micropower, Single Supply Instrumentation Amplifier G = 10 or 100, I
S
= 105µA
LT1102 High Speed, JFET Instrumentation Amplifier G = 10 or 100, Slew Rate = 30V/µs
LT1167 Single Resistor Programmable Precision Instrumentation Amplifier Lower Noise than LT1168, e
N
= 7.5nV/Hz
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear-tech.com
Low Power Programmable Audio HPF/LPF with “Pop-Less” Switching
TYPICAL APPLICATIO
U
+
LTC
®
201
314
215
116
12 13
89
P1
R3
8k
P2
4
+15VNC –15V
4
8
1
–15V TOTAL SUPPLY CURRENT < 400µA
+15V
VIN
3
25
611
C1
100µF
2
3
710
4
5
7
–15V
1168 TA05
+15V
6
5
6
7
HPF
LPF
+
1
8
GAIN SET
R2
4k
R1
4k LT1168
P1 0 1 0 < 0.8V
P20 1 1 1 > 2.4V
POLE 100 200 400 Hz
+
1/2 LT1462
1/2 LT1462
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