ADuM260N-63N Datasheet by Analog Devices Inc.

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ANALOG DEVICES
5.0 kV RMS, 6-Channel Digital Isolators
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals (pending)
UL recognition: 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
CQC certification per GB4943.1-2011
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS-compliant, wide body SOIC_IC package
APPLICATIONS
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM260N/ADuM261N/ADuM262N/ADuM263N1 are
6-channel digital isolators based on Analog Devices, Inc., iCouple
technology. Combining high speed, complementary metal-oxide
semiconductor (CMOS) and monolithic air core transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as
optocoupler devices and other integrated couplers. The maxi-
mum propagation delay is 13 ns with a pulse width distortion of
less than 4.5 ns at 5 V operation. Channel to channel matching
of propagation delay is tight at 4.0 ns maximum.
The ADuM260N/ADuM261N/ADuM262N/ADuM263N data
channels are independent and are available in a variety of
configurations with a withstand voltage rating of 5.0 kV rms
(see the Ordering Guide). The devices operate with the supply
voltage on either side ranging from 1.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling
voltage translation functionality across the isolation barrier.
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available by which the outputs transition to a predeter-
mined state when the input power supply is not applied.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
V
IA
V
IB
V
IC
V
ID
V
IE
V
IF
V
OA
V
OB
V
OC
V
OD
V
OE
V
OF
GND
1
V
DD2
ADuM260N
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
14998-001
Figure 1. ADuM260N Functional Block Diagram
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
V
IA
V
IB
V
IC
V
ID
V
IE
V
OF
V
OA
V
OB
V
OC
V
OD
V
OE
V
IF
GND
1
V
DD2
ADuM261N
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
14998-002
Figure 2. ADuM261N Functional Block Diagram
DECODE ENCODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
V
IA
V
IB
V
IC
V
ID
V
OE
V
OF
V
OA
V
OB
V
OC
V
OD
V
IE
V
IF
GND
1
V
DD2
ADuM262N
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
14998-003
Figure 3. ADuM262N Functional Block Diagram
DECODE ENCODE
DECODE ENCODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
V
IA
V
IB
V
IC
V
OD
V
OE
V
OF
V
OA
V
OB
V
OC
V
ID
V
IE
V
IF
GND
1
V
DD2
ADuM263N
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
14998-004
Figure 4. ADuM263N Functional Block Diagram
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 2 of 23
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—2.5 V Operation ............................ 7
Electrical Characteristics—1.8 V Operation ............................ 9
Insulation and Safety Related Specifications .......................... 11
Package Characteristics ............................................................. 11
Regulatory Information ............................................................. 11
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 12
Recommended Operating Conditions .................................... 12
Absolute Maximum Ratings ......................................................... 13
ESD Caution................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 18
Theory of Operation ...................................................................... 20
Applications Information .............................................................. 21
PCB Layout ................................................................................. 21
Propagation Delay Related Parameters ................................... 21
Jitter Measurement ..................................................................... 21
Insulation Lifetime ..................................................................... 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/2019—Rev. 0 to Rev. A
Changes to Table 11 ........................................................................ 11
Updated Outline Dimensions ....................................................... 23
12/2016—Revision 0: Initial Version
Table L
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 3 of 23
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. M inimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD25.5 V, and −40°C TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
ns
Within pulse width distortion (PWD)
limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output
Pulse Width Distortion PWD 0.5 4.5 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew
t
PSK
6.1
ns
Between any two units at the
same temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.5 4.0 ns
Opposing Direction tPSKOD 0.5 4.5 ns
Jitter 490 ps p-p See the Jitter Measurement section
70 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx
0.2
V IOx2 = −4 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 4 mA, VIx = VIxL4
Input Current per Channel II 10 +0.01 +10 µA 0 V VIx ≤ VDDx
Quiescent Supply Current
ADuM260N
IDD1 (Q) 2.3 3.5 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 3.3 4.52 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 19.3 30 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 3.5 4.82 mA VI5 = 1 (N0), 0 (N1)6
ADuM261N
IDD1 (Q) 2.5 3.8 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 3.2 4.22 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 16.0 24.8 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 7.2 11.2 mA VI5 = 1 (N0), 0 (N1)6
ADuM262N
IDD1 (Q) 2.8 4.0 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 3.0 4.2 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 14.1 22.5 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 10.5 16.7 mA VI5 = 1 (N0), 0 (N1)6
ADuM263N
IDD1 (Q) 3.0 4.26 mA VI5 = 0 (N0), 1 (N1)6
I
DD2 (Q)
2.8
3.92
mA
V
I5
= 0 (N0), 1 (N1)
6
IDD1 (Q) 11.8 18.9 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 14.6 23 mA VI5 = 1 (N0), 0 (N1)6
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 4 of 23
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.02 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive V
DDx
Threshold
V
DDxUV+
1.6
V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity7
|CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM260N0/ADuM261N0/ADuM262N0/ADuM263N0 models. N1 refers to the ADuM260N1/ADuM261N1/ADuM262N1/ADuM263N1 models. See the
Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 2. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
Supply Current Side 1 IDD1 10.8 15.8 12.3 19.2 18.3 26 mA
Supply Current Side 2 IDD2 3.6 5.5 5.63 9.0 12.8 20.9 mA
ADuM261N
Supply Current Side 1 IDD1 9.27 14.5 10.9 17.2 17.3 25.6 mA
Supply Current Side 2 IDD2 5.33 9.0 7.39 12 14.5 22.2 mA
ADuM262N
Supply Current Side 1 IDD1 8.53 13.0 10.2 15.6 16.4 25.5 mA
Supply Current Side 2 IDD2 6.83 10.5 8.64 13.1 14.6 22.3 mA
ADuM263N
Supply Current Side 1 IDD1 7.47 12.3 9.35 14.5 15.9 23 mA
Supply Current Side 2 IDD2 8.75 14.0 10.5 16.0 17.0 23.3 mA
Table 3‘
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 5 of 23
ELECTRICAL CHARACTERISTICS3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD23.6 V, and −40°C TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 4.5 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.5 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.7 4.0 ns
Opposing Direction tPSKOD 0.7 4.5 ns
Jitter 580 ps p-p See the Jitter Measurement section
120 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel
I
I
10
+0.01
+10
µA
0 V ≤ V
Ix
≤ V
DDx
Quiescent Supply Current
ADuM260N
IDD1 (Q) 2.2 3.4 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 3.1 4.1 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 19 27.7 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 3.4 4.7 mA VI5 = 1 (N0), 0 (N1)6
ADuM261N
IDD1 (Q) 2.3 3.6 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 3.0 4.0 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 15.8 24.6 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 7.0 11 mA VI5 = 1 (N0), 0 (N1)6
ADuM262N
IDD1 (Q) 2.6 3.8 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 2.8 4.0 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 13.9 22.2 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 10.3 16.5 mA VI5 = 1 (N0), 0 (N1)6
ADuM263N
IDD1 (Q) 2.8 4.16 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 2.6 3.82 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 11.5 18.5 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 14.3 22.5 mA VI5 = 1 (N0), 0 (N1)6
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Table 4‘ Tom Supply Current vs. Data Throughput
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 6 of 23
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Undervoltage Lockout UVLO
Positive VDDx Threshold VDDxUV+ 1.6 V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM260N0/ADuM261N0/ADuM262N0/ADuM263N0 models. N1 refers to the ADuM260N1/ADuM261N1/ADuM262N1/ADuM263N1 models. See the
Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 4. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM260N
Supply Current Side 1 IDD1 10.5 15.5 11.7 18.6 16.6 24.6 mA
Supply Current Side 2 IDD2 3.4 5.4 5.4 7.8 11.8 19.9 mA
Supply Current Side 1 IDD1 9.0 14.2 10.4 16.6 15.7 24.1 mA
Supply Current Side 2 IDD2 5.1 8.8 7.0 11.6 13.1 20.8 mA
ADuM262N
Supply Current Side 1 IDD1 8.3 12.8 9.8 14.8 15.2 24.3 mA
Supply Current Side 2 IDD2 6.6 10.3 8.3 12.6 13.8 21.5 mA
ADuM263N
Supply Current Side 1 IDD1 7.3 12 8.9 14.2 14.9 22 mA
Supply Current Side 2 IDD2 8.5 13.7 9.9 15.6 16 22.3 mA
Table 5‘
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 7 of 23
ELECTRICAL CHARACTERISTICS2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD22.75 V, −40°C TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay
t
PHL
, t
PLH
5.0
7.0
14
ns
50% input to 50% output
Pulse Width Distortion PWD 0.7 5.0 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.8 ns Between any two units at the
same temperature, voltage, load
Channel Matching
Codirectional
t
PSKCD
0.7
5.0
ns
Opposing Direction tPSKOD 0.7 5.0 ns
Jitter 800 ps p-p See the Jitter Measurement section
190 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel II 10 +0.01 +10 µA 0 V VIx ≤ VDDx
Quiescent Supply Current
ADuM260N
IDD1 (Q) 2.1 3.3 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 3.1 4.1 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 19 27.7 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 3.3 4.6 mA VI5 = 1 (N0), 0 (N1)6
ADuM261N
IDD1 (Q) 2.2 3.5 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 2.9 3.9 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 15.7 24.5 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 6.9 10.9 mA VI5 = 1 (N0), 0 (N1)6
ADuM262N
IDD1 (Q) 2.5 3.7 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 2.7 3.9 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 13.8 22.1 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 10.2 16.4 mA VI5 = 1 (N0), 0 (N1)6
ADuM263N
I
DD1 (Q)
2.7
4.08
mA
V
I5
= 0 (N0), 1 (N1)
6
IDD2 (Q) 2.55 3.72 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 11.5 18.4 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 14.3 22.3 mA VI5 = 1 (N0), 0 (N1)6
Dynamic Supply Current
Dynamic Input
I
DDI (D)
0.01
mA/Mbps
Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Table 6‘ Tom Supply Current vs. Data Throughput
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 8 of 23
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Undervoltage Lockout
Positive VDDx Threshold VDDxUV+ 1.6 V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM260N0/ADuM261N0/ADuM262N0/ADuM263N0 models. N1 refers to the ADuM260N1/ADuM261N1/ADuM262N1/ADuM263N1 models. See the
Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 6. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM260N
Supply Current Side 1 IDD1 10.4 15.4 11.2 18.4 16 24 mA
Supply Current Side 2 IDD2 3.3 5.3 4.8 7.2 9.8 17.9 mA
Supply Current Side 1 IDD1 8.9 14.1 10.1 16.3 14.8 23.6 mA
Supply Current Side 2 IDD2 5.0 8.7 6.5 11.1 11.4 20.1 mA
ADuM262N
Supply Current Side 1 IDD1 8.1 12.6 9.4 14.4 14.1 23.2 mA
Supply Current Side 2 IDD2 6.5 10.2 7.8 12.1 12.4 20.1 mA
ADuM263N
Supply Current Side 1 IDD1 7.1 11.9 8.5 13.9 13.6 21 mA
Supply Current Side 2 IDD2 8.3 13.4 9.7 15.2 14.8 21.3 mA
Table 7‘
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 9 of 23
ELECTRICAL CHARACTERISTICS1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 1.9 V, 1.7 V ≤ VDD21.9 V, and −40°C TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 5.0 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.0 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional
t
PSKCD
0.7
5.0
ns
Opposing Direction tPSKOD 0.7 5.0 ns
Jitter 470 ps p-p See the Jitter Measurement section
70 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel II 10 +0.01 +10 µA 0 V VIx ≤ VDDx
Quiescent Supply Current
ADuM260N
IDD1 (Q) 2.0 3.2 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 3.0 4.0 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 18.7 27.4 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 3.3 4.6 mA VI5 = 1 (N0), 0 (N1)6
ADuM261N
IDD1 (Q) 2.1 3.4 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 2.9 3.9 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 15.5 24.3 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 6.8 10.8 mA VI5 = 1 (N0), 0 (N1)6
ADuM262N
IDD1 (Q) 2.4 3.6 mA VI5 = 0 (N0), 1 (N1)6
IDD2 (Q) 2.7 3.9 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 13.7 22 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 10.1 16.3 mA VI5 = 1 (N0), 0 (N1)6
ADuM263N
I
DD1 (Q)
2.6
4.03
mA
V
I5
= 0 (N0), 1 (N1)
6
IDD2 (Q) 2.5 3.72 mA VI5 = 0 (N0), 1 (N1)6
IDD1 (Q) 11.3 18.3 mA VI5 = 1 (N0), 0 (N1)6
IDD2 (Q) 14 22 mA VI5 = 1 (N0), 0 (N1)6
Dynamic Supply Current
Dynamic Input
I
DDI (D)
0.01
mA/Mbps
Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Table 3‘ Tom Supply Current vs. Data Throughput
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 10 of 23
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Undervoltage Lockout UVLO
Positive VDDx Threshold VDDxUV+ 1.6 V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, D, E, or F.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 N0 refers to the ADuM260N0/ADuM261N0/ADuM262N0/ADuM263N0 models. N1 refers to the ADuM260N1/ADuM261N1/ADuM262N1/ADuM263N1 models. See the
Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 8. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM260N
Supply Current Side 1 IDD1 10.2 15.2 11.3 18.2 15.9 23.9 mA
Supply Current Side 2 IDD2 3.3 5.3 4.8 7.2 9.8 17.9 mA
Supply Current Side 1 IDD1 8.7 13.9 10 16.2 14.6 23.4 mA
Supply Current Side 2 IDD2 4.9 8.6 6.4 11 11.4 20.1 mA
ADuM262N
Supply Current Side 1 IDD1 8.0 12.5 9.2 14.2 13.9 23 mA
Supply Current Side 2 IDD2 6.4 10.1 7.7 12 12.4 20.1 mA
ADuM263N
Supply Current Side 1 IDD1 7.0 11.8 8.3 13.7 13.3 20.7 mA
Supply Current Side 2 IDD2 8.2 13.3 9.5 15 14.5 21 mA
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 11 of 23
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 9.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 8.3 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L (I02) 8.3 mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 8.3 mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 μm min Minimum distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 10.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 R
I-O 1013 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 C
I 4.0 pF
IC Junction to Ambient Thermal Resistance θJA 45 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-
isolation waveforms and insulation levels.
Table 11.
UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
Recognized Under UL 1577
Component Recognition Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Certified under
CQC11-471543-2015,
GB4943.1-2011:
Single Protection, 5000 V rms Isolation
Voltage
CSA 60950-1-07+A1+A2 and IEC
60950-1, second edition, +A1 + A2:
Reinforced insulation, VIORM =
849 V peak, VIOSM = 10 kV peak
Basic insulation at
830 V rms (1174 V peak)
Basic insulation at 830 V rms
(1174 V peak)
Basic insulation, VIORM =
849 V peak, VIOSM = 16 kV peak
Reinforced insulation at
415 V rms (587 V peak)
Reinforced insulation at 415 V rms
(587 V peak)
Tropical climate, altitude
≤5000 meters
IEC 60601-1 Edition 3 + A1 two means
of patient protection (2 MOPP),
261 V rms (369 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains,
830 V rms secondary (1174 V peak)
File E214100 File 205078 File 2471900-4880-0001 File CQC18001192420
1 In accordance with UL 1577, each ADuM260N/ADuM261N/ADuM262N/ADuM263N in the RI-16 wide body (SOIC_IC) package is proof tested by applying an insulation
test voltage ≥ 6000 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADuM260N/ADuM261N/ADuM262N/ADuM263N in the RI-16 wide body (SOIC_IC) package is proof tested by applying an
insulation test voltage ≥ 1592 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10
approval.
Table 12. Table 13.
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 12 of 23
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 12.
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage 150 V rms I to IV
For Rated Mains Voltage 300 V rms I to IV
For Rated Mains Voltage 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 849 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd (m) 1592 V peak
Input to Output Test Voltage, Method A Vpd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1274 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1019 V peak
Highest Allowable Overvoltage VIOTM 8000 V peak
Surge Isolation Voltage Basic
V
PEAK
= 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
V
IOSM
16,000
V peak
Surge Isolation Voltage Reinforced VPEAK = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM 10,000 V peak
Safety Limiting Values Maximum value allowed in the event of a
failure (see Figure 5)
Maximum Junction Temperature TS 150 °C
Total Power Dissipation at 25°C PS 2.78 W
Insulation Resistance at TS RS >109
3.0
2.5
2.0
1.5
0.5
1.0
0020015010050
SAFE LIMITING POWER (W)
AMBIENT TEMPERATURE (°C)
14998-005
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 13.
Parameter
Symbol
Rating
Operating Temperature TA 40°C to +125°C
Supply Voltages VDD1, VDD2 1.7 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms
ESD CAUTION A M ESD (alemostaii: discharge) sensitive device. Chzigcd dchc: and mm board: an disthzlgc wnhom daemon Although (in: pmdud feature: untamed m pmpnemy pmeman ("(umy, damage may accuv an dams Subjected m high enevgy ESD Thevefme, pmpev ESD plEzaLmunS Shnuid be iaken to avoid perfavmance dagvadanon m ‘05; of functionahiy Table 15. Maximum Continuous Working Voliage Table I6. ADuMZGON/ADILM261N/ADuM262N/ADILMZS3N Tl'llfl'l Table (Positive Logic)
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 13 of 23
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 14.
Parameter Rating
Storage Temperature (TST) Range 65°C to +150°C
Ambient Operating Temperature
(TA) Range
40°C to +125°C
Supply Voltages (VDD1, VDD2) 0.5 V to +7.0 V
Input Voltages (VIA, VIB, VIC, VID, VIE,
VIF)
0.5 V to VDDI1 + 0.5 V
Output Voltages (VOA, VOB, VOC, VOD, VOE,
VOF)
0.5 V to VDDO2 + 0.5 V
Average Output Current per Pin3
Side 1 Output Current (IO1) 10 mA to +10 mA
Side 2 Output Current (IO2) 10 mA to +10 mA
Common-Mode Transients4 150 kV/μs to +150 kV/μs
1 VDDI is the input side supply voltage.
2 VDDO is the output side supply voltage.
3 See Figure 5 for the maximum rated current values for various temperatures.
4 Refers to the common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Table 15. Maximum Continuous Working Voltage1
Parameter Rating Constraint
AC Voltage
Bipolar Waveform
Basic Insulation 849 V peak 50-year minimum insulation lifetime
Reinforced Insulation 819 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 1698 V peak 50-year minimum insulation lifetime
Reinforced Insulation 943 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation 1157 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 579 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Truth Table
Table 16. ADuM260N/ADuM261N/ADuM262N/ADuM263N Truth Table (Positive Logic)
VIx Input1, 2 VDDI State2 VDDO State2
Default Low (N0),
VOx Output1, 2, 3
Default High (N1),
VOx Output1, 2, 3 Test Conditions/Comments
L
Powered
Powered
L
L
Normal operation
H Powered Powered H H Normal operation
L Unpowered Powered L H Fail-safe output
X4 Powered Unpowered Indeterminate Indeterminate Output Unpowered
1 L means low, H means high, and X means don’t care.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, E or F). VDDI and VDDO refer to the supply voltages on the input and output sides of the
given channel, respectively.
3 N0 refers to the ADuM260N0/ADuM261N0/ADuM262N0/ADuM263N0 models. N1 refers to the ADuM260N1/ADuM261N1/ADuM262N1/ADuM263N1 models. See the
Ordering Guide section.
4 Input pins (VIx) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.
3333333] EEEEEEEE
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 14 of 23
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1
VIA
VIB
VIC
VID
VIE
VIF
VOA
VOB
VOC
VOD
VOE
VOF
GND1
VDD2
GND2
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM260N
TOP VIEW
(Not to Scale)
14998-006
Figure 6. ADuM260N Pin Configuration
Table 17. ADuM260N Pin Function Descriptions
Pin No.1 Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 VIA Logic Input A.
3 VIB Logic Input B.
4 VIC Logic Input C.
5 VID Logic Input D.
6 VIE Logic Input E.
7 VIF Logic Input F.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VOF Logic Output F.
11 VOE Logic Output E.
12 VOD Logic Output D.
13 VOC Logic Output C.
14 VOB Logic Output B.
15 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
33333333 EEEEEEEE
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 15 of 23
VDD1
VIA
VIB
VIC
VID
VIE
VOF
VOA
VOB
VOC
VOD
VOE
VIF
GND1
VDD2
GND2
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM261N
TOP VIEW
(Not to Scale)
14998-007
Figure 7. ADuM261N Pin Configuration
Table 18. ADuM261N Pin Function Descriptions
Pin No.1 Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 VIA Logic Input A.
3 VIB Logic Input B.
4 VIC Logic Input C.
5 VID Logic Input D.
6 VIE Logic Input E.
7 VOF Logic Output F.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VIF Logic Input F.
11 VOE Logic Output E.
12 VOD Logic Output D.
13 VOC Logic Output C.
14 VOB Logic Output B.
15 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
33333333 EEEEEEEE
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 16 of 23
V
DD1
V
IA
V
IB
V
IC
V
ID
V
OE
V
OF
V
OA
V
OB
V
OC
V
OD
V
IE
V
IF
GND
1
V
DD2
GND
2
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM262N
TOP VIEW
(Not to Scale)
14998-008
Figure 8. ADuM262N Pin Configuration
Table 19. ADuM262N Pin Function Descriptions
Pin No.1 Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 VIA Logic Input A.
3 VIB Logic Input B.
4 VIC Logic Input C.
5 VID Logic Input D.
6 VOE Logic Output E.
7 VOF Logic Output F.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VIF Logic Input F.
11 VIE Logic Input E.
12 VOD Logic Output D.
13 VOC Logic Output C.
14 VOB Logic Output B.
15 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
33333333 EEEEEEEE
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 17 of 23
V
DD1
V
IA
V
IB
V
IC
V
OD
V
OE
V
OF
V
OA
V
OB
V
OC
V
ID
V
IE
V
IF
GND
1
V
DD2
GND
2
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM263N
TOP VIEW
(Not to Scale)
14998-009
Figure 9. ADuM263N Pin Configuration
Table 20. ADuM263N Pin Function Descriptions
Pin No.1 Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 VIA Logic Input A.
3 VIB Logic Input B.
4 VIC Logic Input C.
5 VOD Logic Output D.
6 VOE Logic Output E.
7 VOF Logic Output F.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VIF Logic Input F.
11 VIE Logic Input E.
12 VID Logic Input D.
13 VOC Logic Output C.
14 VOB Logic Output B.
15 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
\\\ \\ \ \\ \ \\ \ \\ \\ \\\ \\ \\ \\ \\ \\
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 18 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
15
10
5
0020 40 60 80 100 120 140 160
IDD1 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5V
3.3V
2.5V
1.8V
14998-010
Figure 10. ADuM260N IDD1 Supply Current vs. Data Rate at Various Voltages
25
20
15
10
5
0020 40 60 80 100 120 140 160
IDD2 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5V
3.3V
2.5V
1.8V
14998-011
Figure 11. ADuM260N IDD2 Supply Current vs. Data Rate at Various Voltages
IDD1 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
25
20
15
10
5
0020 40 60 80 100 120 140 160
5V
3.3V
2.5V
1.8V
14998-012
Figure 12. ADuM261N IDD1 Supply Current vs. Data Rate at Various Voltages
IDD2 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
25
20
15
10
5
0020 40 60 80 100 120 140 160
5V
3.3V
2.5V
1.8V
14998-013
Figure 13. ADuM261N IDD2 Supply Current vs. Data Rate at Various Voltages
25
20
15
10
5
0020 40 60 80 100 120 140 160
5V
3.3V
2.5V
1.8V
IDD1 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
14998-014
Figure 14. ADuM262N IDD1 Supply Current vs. Data Rate at Various Voltages
25
20
15
10
5
0020 40 60 80 100 120 140 160
5V
3.3V
2.5V
1.8V
IDD2 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
14998-015
Figure 15. ADuM262N IDD2 Supply Current vs. Data Rate at Various Voltages
/%; éé/ / / %?4 %4
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 19 of 23
25
20
15
10
5
0020 40 60 80 100 120 140 160
IDD1 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5V
3.3V
2.5V
1.8V
14998-016
Figure 16. ADuM263N IDD1 Supply Current vs. Data Rate at Various Voltages
25
20
15
10
5
0020 40 60 80 100 120 140 160
5V
3.3V
2.5V
1.8V
IDD2 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
14998-017
Figure 17. ADuM263N IDD2 Supply Current vs. Data Rate at Various Voltages
14
12
10
8
6
4
2
0
–40 –20 020 40 60 80 120100 140
PROPAGATION DELAY
t
PLH
(ns)
TEMPERATURE (°C)
5V
3.3V
2.5V
1.8V
14998-018
Figure 18. Propagation Delay, tPLH vs. Temperature at Various Voltages
14
12
10
8
6
4
2
0
–40 –20 020 40 60 80 120100 140
PROPAGATION DELAY
t
PHL
(ns)
TEMPERATURE (°C)
5V
3.3V
2.5V
1.8V
14998-019
Figure 19. Propagation Delay, tPHL vs. Temperature at Various Voltages
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 20 of 23
THEORY OF OPERATION
The ADuM260N/ADuM261N/ADuM262N/ADuM263N use
a high frequency carrier to transmit data across the isolation
barrier using iCoupler chip scale transformer coils separated by
layers of polyimide isolation. Using an on/off keying (OOK)
technique and the differential architecture shown in Figure 20
and Figure 21, the ADuM260N/ADuM261N/ADuM262N/
ADuM263N have very low propagation delay and high speed.
Internal regulators and input/output design techniques allow
logic and supply voltages over a wide range from 1.7 V to 5.5 V,
offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic.
The architecture is designed for high common-mode transient
immunity and high immunity to electrical noise and magnetic
interference. Radiated emissions are minimized with a spread
spectrum OOK carrier and other techniques.
Figure 20 shows the waveforms for models of the ADuM260N0/
ADuM261N0/ADuM262N0/ADuM263N0 that have the
condition of the fail-safe output state equal to low, where the
carrier waveform is off when the input state is low. If the input
side is off or not operating, the fail-safe output state of low sets
the output to low. For the ADuM260N1/ADuM261N1/
ADuM262N1/ADuM263N1 that have a fail-safe output state of
high, Figure 21 illustrates the conditions where the carrier
waveform is off when the input state is high. When the input
side is off or not operating, the fail-safe output state of high sets
the output to high. See the Ordering Guide for the model
numbers that have the fail-safe output state of low or the fail-safe
output state of high.
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14998-020
Figure 20. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14998-021
Figure 21. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
2:: 32:“
Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 21 of 23
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM260N/ADuM261N/ADuM262N/ADuM263N digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at
the input and output supply pins (see Figure 22). Bypass
capacitors are connected between Pin 1 and Pin 8 for VDD1 and
between Pin 9 and Pin 16 for VDD2. The recommended bypass
capacitor value is between 0.01 μF and 0.1 μF. The total lead
length between both ends of the capacitor and the input power
supply pin must not exceed 10 mm.
V
DD1
V
IA
V
IB
V
IC
V
ID
, V
OD
V
IE
, V
OE
V
IF
, V
OF
GND
1
V
DD2
V
OA
V
OB
V
OC
V
ID
, V
OD
V
IE
, V
OE
V
IF
, V
OF
GND
2
14998-022
Figure 22. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
14998-023
Figure 23. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM260N/
ADuM261N/ADuM262N/ADuM263N component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM260N/ADuM261N/
ADuM262N/ADuM263N components operating under the
same conditions.
JITTER MEASUREMENT
Figure 24 illustrates the eye diagram for the ADuM260N/
ADuM261N/ADuM262N/ADuM263N. The measurement was
taken using an Agilent 81110A pulse pattern generator at
150 Mbps with pseudorandom bit sequences (PRBS) 2(n − 1), n =
14, for 5 V supplies. Jitter was measured with the Tektronix
Model 5104B oscilloscope, 1 GHz, 10 GSPS with the DPOJET
jitter and eye diagram analysis tools. The result shows a typical
measurement on the ADuM260N/ADuM261N/ADuM262N/
ADuM263N with 490 ps p-p jitter.
105
0
1
2
3
4
VOLTAGE (V)
5
0
TIME (ns)
–5–10
14998-024
Figure 24. ADuM260N/ADuM261N/ADuM262N/ADuM263N Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking,
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation, pollution degree, and material group. The material
group and creepage for the ADuM260N/ADuM261N/
ADuM262N/ADuM263N isolators are presented in Table 9.
ADuM260N/ADuM261N/ADuM262N/ADuM263N Data Sheet
Rev. A | Page 22 of 23
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
Testing and modeling have shown that the primary driver of long-
term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as:
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltages. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out,
Equation 1 can be rearranged to solve for the ac rms voltage, as
is shown in Equation 2. For insulation wear out with the polyimide
materials used in these products, the ac rms voltage determines
the product lifetime.
22
DCRMSACRMS
VVV +=
(1)
or
22
DCRMSRMSAC
VVV =
(2)
where:
VAC RMS is the time varying portion of the working voltage.
VRMS is the total rms working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms, a 400 V dc bus voltage is present on
the other side of the isolation barrier, and the isolator material
is polyimide. To establish the critical voltages in determining
the creepage, clearance and lifetime of a device, see Figure 25
and the following equations.
ISOLATION VOLTAGE
TIME
V
AC RMS
V
RMS
V
DC
V
PEAK
14998-025
Figure 25. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
22
DCRMSACRMS
VVV +=
22
400240 +=
RMS
V
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
22
DCRMSRMS
AC
VVV =
22
400466
=
RMSAC
V
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 15 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Note that the dc working voltage limit in Table 15 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
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Data Sheet ADuM260N/ADuM261N/ADuM262N/ADuM263N
Rev. A | Page 23 of 23
OUTLINE DIMENSIONS
16 9
81
COPLANARITY
0.10
1.27 BSC
12.95
12.80
12.65
7.60
7.50
7.40
2.64
2.50
2.36
1.27
0.41
2.44
2.24
0.25
0.10
10.55
10.30
10.05
0.49
0.35
0.33
0.23
0.76
0.25 45°
0.25 BSC
GAGE
PLANE
COMPLIANT TO JEDEC STANDARDS MS-013-AC
12-13-2017-B
PKG-004586
TOP VIEW
SIDE VIEW
END VIEW
PIN 1
INDICATOR
SEATING
PLANE
Figure 26. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range
No. of
Inputs,
VDD1
Side
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating
(kV rms)
Fail-Safe
Output
State Package Description
Package
Option
ADuM260N1BRIZ 40°C to +125°C 6 0 5.0 High 16-Lead SOIC_IC RI-16-2
ADuM260N1BRIZ-RL 40°C to +125°C 6 0 5.0 High 16-Lead SOIC_IC RI-16-2
ADuM260N0BRIZ 40°C to +125°C 6 0 5.0 Low 16-Lead SOIC_IC RI-16-2
ADuM260N0BRIZ-RL 40°C to +125°C 6 0 5.0 Low 16-Lead SOIC_IC RI-16-2
ADuM261N1BRIZ 40°C to +125°C 5 1 5.0 High 16-Lead SOIC_IC RI-16-2
ADuM261N1BRIZ-RL
40°C to +125°C
5
1
5.0
High
16-Lead SOIC_IC
RI-16-2
ADuM261N0BRIZ 40°C to +125°C 5 1 5.0 Low 16-Lead SOIC_IC RI-16-2
ADuM261N0BRIZ-RL 40°C to +125°C 5 1 5.0 Low 16-Lead SOIC_IC RI-16-2
ADuM262N1BRIZ 40°C to +125°C 4 2 5.0 High 16-Lead SOIC_IC RI-16-2
ADuM262N1BRIZ-RL 40°C to +125°C 4 2 5.0 High 16-Lead SOIC_IC RI-16-2
ADuM262N0BRIZ 40°C to +125°C 4 2 5.0 Low 16-Lead SOIC_IC RI-16-2
ADuM262N0BRIZ-RL 40°C to +125°C 4 2 5.0 Low 16-Lead SOIC_IC RI-16-2
ADuM263N1BRIZ 40°C to +125°C 3 3 5.0 High 16-Lead SOIC_IC RI-16-2
ADuM263N1BRIZ-RL 40°C to +125°C 3 3 5.0 High 16-Lead SOIC_IC RI-16-2
ADuM263N0BRIZ 40°C to +125°C 3 3 5.0 Low 16-Lead SOIC_IC RI-16-2
ADuM263N0BRIZ-RL 40°C to +125°C 3 3 5.0 Low 16-Lead SOIC_IC RI-16-2
1 Z = RoHS Compliant Part.
©20162019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14998-0-7/19(A)

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