PIC18Fxx2, xx8 Programming Specification Datasheet by Microchip Technology

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Q ‘MICROCHIP P|C1 8FXX2/XX8
2010 Microchip Technology Inc. DS39576C-page 1
PIC18FXX2/XX8
1.0 DEVICE OVERVIEW
This document includes the programming specifica-
tions for the following devices:
•PIC18F242
•PIC18F248
•PIC18F252
•PIC18F258
•PIC18F442
•PIC18F448
•PIC18F452
•PIC18F458
2.0 PROGRAMMING OVERVIEW
OF THE PIC18FXX2/XX8
The PIC18FXX2/XX8 can be programmed using the
high voltage In-Circuit Serial ProgrammingTM (ICSPTM)
method, or the low voltage ICSP method. Both of these
can be done with the device in the users’ system. The
low voltage ICSP method is slightly different than the
high voltage method, and these differences are noted
where applicable. This programming specification
applies to PIC18FXX2/XX8 devices in all package
types.
2.1 Hardware Requirements
In high voltage ICSP mode, the PIC18FXX2/XX8
requires two programmable power supplies: one for
VDD and one for MCLR/VPP. Both supplies should have
a minimum resolution of 0.25V. Refer to Section 6.0 for
additional hardware parameters.
2.1.1 LOW VOLTAGE ICSP
PROGRAMMING
In low voltage ICSP mode, the PIC18FXX2/XX8 can be
programmed using a VDD source in the operating
range. This only means that MCLR/VPP does not have
to be brought to a different voltage, but can instead be
left at the normal operating voltage. Refer to
Section 6.0 for additional hardware parameters.
2.2 Pin Diagrams
The pin diagrams for the PIC18FXX2/XX8 family are
shown in Figure 2-1. The pin descriptions of these dia-
grams do not represent the complete functionality of
the device types. Users should refer to the appropriate
device data sheet for complete pin descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX2/XX8
Pin Name During Programming
Pin Name Pin Type Pin Description
MCLR/VPP VPP P Programming Enable
VDD VDD P Power Supply
Vss VSS P Ground
RB5 PGM I Low Voltage ICSP™ Input when LVP Configuration bit equals ‘1’(1)
RB6 SCLK I Serial Clock
RB7 SDATA I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 for more detail.
Flash Microcontroller Programming Specification
:::::::::: jjjjjjjjjjjjjjjj 33]] EEEEEEEEEEEEEEEE 11111111111111 EEEEEEEEEEEEEE [[[E MM 1 2m#* IIIIIIIIIII :::::H WNW i
PIC18FXX2/XX8
DS39576C-page 2 2010 Microchip Technology Inc.
FIGURE 2-1: PIC18FXX2/XX8 FAMILY PIN DIAGRAMS
Note: Not all multiplexed pin definitions are shown. Refer to the appropriate data sheet for complete pin descriptions.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9PIC18F4X2
RA4
RA5
RE0
OSC2
NC
RE1
RE2
VDD
OSC1
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
VSS
RC0
PIC18F4X8
44L PLCC
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
NC
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
PIC18F4X2
PIC18F4X8
44L QFP
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
VDD
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4X2/8 40L DIP
9
MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
1
2
3
4
5
6
7
8
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
9
PIC18F2X2/8 28L DIP
PIC18F2X2/8 28L SOIC
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3
RA2
RA1
RA0
MCLR/VPP
RB3
RB7
RB6
RB5
RB4
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
PIC18F4X2 AVSS
VDD
AVDD
PIC18F4X8
44L QFN
2010 Microchip Technology Inc. DS39576C-page 3
PIC18FXX2/XX8
2.3 Memory Map
The code memory space extends from 0000h to 7FFFh
(32 Kbytes) in four, 8-Kbyte panels. Addresses 0000h
through 01FFh, however, define a “Boot Block” region
that is treated separately from Panel 1. All code
memory is on-chip.
In addition to the code memory space, there are three
blocks in the configuration and ID space that are acces-
sible to the user through Table Reads and Table Writes.
Their locations in the memory map are shown in
Figure 2-3.
TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-2: CODE MEMORY SPACE FOR PIC18FXX2/XX8 DEVICES
Device Code Memory Size
(Bytes)
PIC18F242 0000h - 3FFFh (16K)
PIC18F248
PIC18F252 0000h - 7FFFh (32K)
PIC18F258
PIC18F442 0000h - 3FFFh (16K)
PIC18F448
PIC18F452 0000h - 7FFFh (32K)
PIC18F458
MEMORY SIZE / DEVICE Block Code Protection
Controlled By:
16 Kbytes
(PIC18FX42) 32 Kbytes
(PIC18FX52) Address
Range
Boot Block Boot Block 000000h
0001FFh CPB, WRTB, EBTRB
Block 0 Block 0 000200h
001FFFh CP0, WRT0, EBTR0
Block 1 Block 1 002000h
003FFFh CP1, WRT1, EBTR1
Unimplemented
Read ‘0’s Block 2 004000h
005FFFh CP2, WRT2, EBTR2
Unimplemented
Read ‘0’s Block 3 006000h
007FFFh CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s Unimplemented
Read ‘0’s
008000h
1FFFFFh
(Unimplemented Memory Space)
PIC18FXX2/XX8
DS39576C-page 4 2010 Microchip Technology Inc.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300001h through 30000Dh are reserved for
the configuration bits. These bits may be set to select
various device options, and are described in
Section 5.0. These configuration bits read out normally
even after code protected.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed,
and are described in Section 5.0. These configuration
bits read out normally even after code protection.
2.3.1 MEMORY ADDRESS POINTER
Memory in the address space 000000h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointer registers:
TBLPTRU, at address 0FF8h
TBLPTRH, at address 0FF7h
TBLPTRL, at address 0FF6h
The 4-bit command, ‘0000’ (Core Instruction), is used
to load the Table Pointer prior to using many Read or
Write operations.
FIGURE 2-3: CONFIGURATION AND ID LOCATIONS FOR PIC18FXX2/XX8 DEVICES
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
ID Location 7 200006h
ID Location 8 200007h
CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
CONFIG3L 300004h
CONFIG3H 300005h
CONFIG4L 300006h
CONFIG4H 300007h
CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh
Device ID1 3FFFFEh
Device ID2 3FFFFFh
Note: Sizes of memory areas are not to scale.
000000h
1FFFFFh
3FFFFFh
01FFFFh Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
2FFFFFh
2010 Microchip Technology Inc. DS39576C-page 5
PIC18FXX2/XX8
2.4 High Level Overview of the
Programming Process
Figure 2-5 shows the high level overview of the pro-
gramming process. First, a bulk erase is performed.
Next, the code memory, ID locations, and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the configuration bits are then
programmed and verified.
2.5 Entering High Voltage ICSP
Program/Verify Mode
The High Voltage ICSP Program/Verify mode is
entered by holding SCLK and SDATA low, and then
raising MCLR/VPP to VIHH (high voltage). Once in this
mode, the code memory, data EEPROM, ID locations,
and configuration bits can be accessed and
programmed in serial fashion.
The sequence that enters the device into the Program-
ming/Verify mode places all unused I/Os in the high
impedance state.
2.5.1 ENTERING LOW VOLTAGE ICSP
PROGRAM/VERIFY MODE
When the LVP configuration bit is ‘1’ (see Section 5.3),
the Low Voltage ICSP mode is enabled. Low Voltage
ICSP Program/Verify mode is entered by holding SCLK
and SDATA low, placing a logic high on PGM, and then
raising MCLR/VPP to VIH. In this mode, the RB5/PGM
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the Program-
ming/Verify mode places all unused I/Os in the high
impedance state.
FIGURE 2-4: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
FIGURE 2-5: HIGH LEVEL
PROGRAMMING FLOW
FIGURE 2-6: ENTERING LOW VOLTAGE
PROGRAM/ VERIFY MODE
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
VDD
D110
P13
Start
Program Memory
Program IDs
Program Data
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
PGM
P15
VDD
VIH
VIH
PIC18FXX2/XX8
DS39576C-page 6 2010 Microchip Technology Inc.
2.6 Serial Program/Verify Operation
The SCLK pin is used as a clock input pin and the
SDATA pin is used for entering command bits and data
input/output during serial operation. Commands and
data are transmitted on the rising edge of SCLK,
latched on the falling edge of SCLK, and are Least
Significant bit (LSb) first.
2.6.1 4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, SCLK is cycled four times. The commands
needed for programming and verification are shown in
Table 2-3.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Figure 2-4. The 4-bit com-
mand is shown MSb first. The command operand, or
“Data Payload”, is shown <MSB><LSB>. Figure 2-7
demonstrates how to serially present a 20-bit
command/operand to the device.
2.6.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to setup
registers as appropriate for use with other commands.
TABLE 2-3: COMMANDS FOR
PROGRAMMING
TABLE 2-4: SAMPLE COMMAND
SEQUENCE
FIGURE 2-7: TABLE WRITE, POST INCREMENT TIMING (1101)
Description 4-Bit
Command
Core Instruction
(Shift in16-bit instruction) 0000
Shift out TABLAT register 0010
Table Read 1000
Table Read, post-increment 1001
Table Read, post-decrement 1010
Table Read, pre-increment 1011
Table Write 1100
Table Write, post-increment by 2 1101
Table Write, post-decrement by 2 1110
Table Write, start programming 1111
4-Bit
Command Data
Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2
1234
SCLK
P5
SDATA
SDATA = Input
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1011
1234
nnnn
P3
P2 P2A
000000 010001111 0
04C3
P4
4-bit Command 16-bit Data Payload
P2B
2010 Microchip Technology Inc. DS39576C-page 7
PIC18FXX2/XX8
3.0 DEVICE PROGRAMMING
3.1 High Voltage ICSP Bulk Erase
Erasing code or data EEPROM is accomplished by
writing an “erase option” to address 3C0004h. Code
memory may be erased portions at a time, or the user
may erase the entire device in one action. “Bulk Erase”
operations will also clear any code protect settings
associated with the memory block erased. Erase
options are detailed in Table 3-1.
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed opera-
tion. Once the erase has started (falling edge of the 4th
SCLK after the WRITE command), serial execution will
cease until the erase completes (parameter P11). Dur-
ing this time, SCLK may continue to toggle, but SDATA
must be held low.
The code sequence to erase the entire device is shown
in Figure 3-2 and the flowchart is show in Figure 3-1.
TABLE 3-2: BULK ERASE COMMAND
SEQUENCE
FIGURE 3-1: BULK ERASE FLOW
FIGURE 3-2: BULK ERASE TIMING
Description Data
Chip Erase 80h
Erase Data EEPROM 81h
Erase Boot Block 83h
Erase Panel 1 88h
Erase Panel 2 89h
Erase Panel 3 8Ah
Erase Panel 4 8Bh
Note: A bulk erase is the only way to reprogram
code protect bits from an on state to an off
state.
4-Bit
Command Data
Payload Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
00 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
erase entire device.
NOP
Hold SDATA low until
erase completes.
Start
Done
Write 80h
to Erase
Entire Device
Load Address
Pointer to
3C0004h
Delay P11+P10
Time
n
1234 121516 123
SCLK
P5 P5A
SDATA
SDATA = Input
00011
P11
P10
Erase Time
00 0 000 0 0
12
00
4
0
12 1516
P5
123
P5A
4
0000
n
4-bit Command 4-bit Command 4-bit Command
NOP
16-bit
Data Payload 16-bit
Data Payload
PIC18FXX2/XX8
DS39576C-page 8 2010 Microchip Technology Inc.
3.1.1 LOW VOLTAGE ICSP BULK ERASE
When using low voltage ICSP, the part must be sup-
plied by the voltage specified in parameter D111, if a
bulk erase is to be executed. All other bulk erase details
as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the bulk erase
limit, refer to the erase methodology described in
Sections 3.1.2 and 3.2.2.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the bulk erase
limit, follow the methodology described in Section 3.4
and write ones to the array.
3.1.2 ICSP MULTI-PANEL SINGLE ROW
ERASE
Irrespective of whether high or low voltage ICSP is
used, it is possible to erase single row (64 bytes of
data) in all panels at once. For example, in the case of
a 64-Kbyte device (8 panels), 512 bytes through 64
bytes in each panel, can be erased simultaneously dur-
ing each erase sequence. In this case, the offset of the
erase within each panel is the same (see Figure 3-5).
Multi-Panel Single Row Erase is enabled by appropri-
ately configuring the Programming Control register
located at 3C0006h.
The multi-panel single row erase duration is externally
timed and is controlled by SCLK. After a “Start Pro-
gramming” command is issued (4-bit command,
1111’), a NOP is issued, where the 4th SCLK is held
high for the duration of the programming time, P9.
After SCLK is brought low, the programming sequence
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX2/XX8
device is shown in Table 3-3. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18FXX2/XX8 device. The timing diagram
that details the “Start Programming” command, and
parameters P9 and P10 is shown in Figure 3-6.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
2010 Microchip Technology Inc. DS39576C-page 9
PIC18FXX2/XX8
TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE
FIGURE 3-3: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
0000
8E A6
8C A6
86 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel erase.
Step 3: Direct access to code memory and enable erase.
0000
0000
0000
0000
0000
0000
8E A6
9C A6
88 A6
6A F8
6A F7
6A F6
BSF EECON1, EEPGD
BCF EECON1, CFGS
BSF EECON1, FREE
CLRF TBLPTRU
CLRF TBLPTRH
CLRF TBLPTRL
Step 4: Erase single row of all panels at an offset.
1111
0000
<DummyLSB>
<DummyMSB>
00 00
Write 2 dummy bytes and start programming.
NOP - hold SCLK high for time P9.
Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.
Done
Start
Delay P9 + P10
Time for Erase
to Occur
All
panels
done?
No
Yes
Addr = 0
Configure
Device for
Multi-Panel Erase
Addr = Addr + 64
Start Erase Sequence
and Hold SCLK High
Until Done
PIC18FXX2/XX8
DS39576C-page 10 2010 Microchip Technology Inc.
3.2 Code Memory Programming
Programming code memory is accomplished by first
loading data into the appropriate write buffers and then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-2) has an 8-byte
deep write buffer that must be loaded prior to initiating
a write sequence. The actual memory write sequence
takes the contents of these buffers and programs the
associated EEPROM code memory.
Typically, all of the program buffers are written in paral-
lel (Multi-Panel Write mode). In other words, in the case
of a 32-Kbyte device (4 panels with an 8-byte buffer per
panel), 32 bytes will be simultaneously programmed
during each programming sequence. In this case, the
offset of the write within each panel is the same (see
Figure 3-4). Multi-Panel Write mode is enabled by
appropriately configuring the programming control
register located at 3C0006h.
The programming duration is externally timed and is
controlled by SCLK. After a “Start Programming” com-
mand is issued (4-bit command,1111’), a NOP is
issued, where the 4th SCLK is held high for the
duration of the programming time, P9.
After SCLK is brought low, the programming sequence
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX2/XX8
device is shown in Figure 3-4. The flowchart shown in
Figure 3-5 depicts the logic necessary to completely
write a PIC18FXX2/XX8 device.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
Oflsm : TELPTR<12 3=""> Ollse‘ = TBLPTR<12 a="">
2010 Microchip Technology Inc. DS39576C-page 11
PIC18FXX2/XX8
FIGURE 3-4: ERASE AND WRITE BOUNDARIES
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 0
Offset = TBLPTR<12:6>
Panel 1
Erase Region
(64 bytes)
8-byte Write Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 1
Offset = TBLPTR<12:6>
Panel 2
Erase Region
(64 bytes)
8-byte Write Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = 2
Offset = TBLPTR<12:6>
Panel 3
Erase Region
(64 bytes)
8-byte Write Buffer
TBLPTR<2:0> = 0
TBLPTR<2:0> = 1
TBLPTR<2:0> = 2
TBLPTR<2:0> = 3
TBLPTR<2:0> = 4
TBLPTR<2:0> = 5
TBLPTR<2:0> = 6
TBLPTR<2:0> = 7
Offset = TBLPTR<12:3>
TBLPTR<21:13> = (n – 1)
Offset = TBLPTR<12:6>
Panel n
Erase Region
(64 bytes)
8-byte Write Buffer
Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.
PIC18FXX2/XX8
DS39576C-page 12 2010 Microchip Technology Inc.
TABLE 3-4: WRITE CODE MEMORY CODE SEQUENCE
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
0000
8E A6
8C A6
86 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel writes.
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Load write buffer for Panel 1.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1100
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes
Step 5: Repeat for Panel 2.
Step 6: Repeat for all but the last panel (N – 1).
Step 7: Load write buffer for last panel.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented by 8 in each panel at each iteration of
the loop.
2010 Microchip Technology Inc. DS39576C-page 13
PIC18FXX2/XX8
FIGURE 3-5: PROGRAM CODE MEMORY FLOW
FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
Start Write Sequence
All
locations
done?
No
Done
Start
Yes
Delay P9+P10 Time
for Write to Occur
Load 8 Bytes
to Panel N Write
Buffer at <Addr>
All
panel buffers
written?
No
Yes
and Hold SCLK
High Until Done
N = 1
LoopCount = 0
Configure
Device for
Multi-Panel Writes
N = 1
LoopCount =
LoopCount + 1
N = N + 1
Panel Base Address =
(N – 1) x 2000h
Addr = Panel Base Address
+ (8 x LoopCount)
1234 12 1516 123 4
SCLK
P5A
SDATA
SDATA = Input
n
1111
34 65
P9
P10
Programming Time
nnn nn n n 0 0
12
000
16-bit
Data Payload
0
3
0
P5
4-bit Command 16-bit Data Payload 4-bit Command
PIC18FXX2/XX8
DS39576C-page 14 2010 Microchip Technology Inc.
3.2.1 SINGLE PANEL PROGRAMMING
The programming example presented in Section 3.2
utilizes multi-panel programming. This technique
greatly decreases the total amount of time necessary to
completely program a device and is the recommended
method of completely programming a device.
There may be situations, however, where it is advanta-
geous to limit writes to a single panel. In such cases,
the user only needs to disable the multi-panel write
feature of the device by appropriately configuring the
programming control register located at 3C0006h.
The single panel that will be written will automatically
be enabled, based on the value of the Table Pointer.
3.2.2 MODIFYING CODE MEMORY
All of the programming examples up to this point have
assumed that the device is blank prior to programming.
In fact, if the device is not blank, the direction has been
to completely erase the device via a Bulk Erase
operation (see Section 3.1) operation.
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device. In such a situation, erasing the entire device is
not a realistic option.
The minimum amount of data that can be written to the
device is 8 bytes. This is accomplished by placing the
device in Single Panel Write mode (see Section 3.2.1),
loading the 8-byte write buffer for the panel, and then
initiating a write sequence. In this case, however, it is
assumed that the address space to be written already
has data in it (i.e., it is not blank).
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
must be placed in Single Panel Write mode. The
EECON1 register must then be used to erase the
64-byte target space prior to writing the data.
When using the EECON1 register to act on code mem-
ory, the EEPGD bit must be set (EECON1<7> = 1) and
the CFGS bit must be cleared (EECON1<6> = 0). The
WREN bit must be set (EECON1<2> = 1) to enable
writes of any sort (e.g., erases), and this must be done
prior to initiating a write sequence. The FREE bit must
be set (EECON1<4> = 1) in order to erase the program
space being pointed to by the Table Pointer. The erase
sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then, AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The erase will begin on the falling edge of the 4th SCLK
after the WR bit is set.
After the erase sequence terminates, SCLK must still
be held low for the time specified by parameter P10 to
allow high voltage discharge of the memory array.
Note: For single panel programming, the user
must still fill the 8-byte write buffer for the
given panel.
2010 Microchip Technology Inc. DS39576C-page 15
PIC18FXX2/XX8
TABLE 3-5: MODIFYING CODE MEMORY
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
8E A6
8C A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single-panel writes.
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 5: Enable memory writes and setup an erase.
0000
0000
84 A6
88 A6
BSF EECON1, WREN
BSF EECON1, FREE
Step 6: Perform required sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 55h
MOVWF EECON2
MOVLW 0AAh
MOVWF EECON2
Step 7: Initiate erase.
0000
0000
82 A6
00 00
BSF EECON1, WR
NOP
Step 8: Wait for P11+P10 and then disable writes.
0000 94 A6 BCF EECON1, WREN
Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer.
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.
MMW m , J W, mmmmfl—gl fix /—5
PIC18FXX2/XX8
DS39576C-page 16 2010 Microchip Technology Inc.
3.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, EEDATA with the data to be
written, and initiating a memory write by appropriately
configuring the EECON1 and EECON2 registers. A
byte write automatically erases the location and writes
the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to enable writes of any sort, and this
must be done prior to initiating a write sequence. The
write sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then, AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The write will begin on the falling edge of the 4th SCLK
after the WR bit is set.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-7: PROGRAM DATA FLOW
FIGURE 3-8: DATA EEPROM WRITE TIMING
Start
Start Write
Set Data
Done
No
Yes
Done?
Enable Write
Unlock Sequence
55h - EECON2
AAh - EECON2
Sequence
Set Address
WR bit
clear? No
Yes
n
SCLK
SDATA
SDATA = Input
0000
BSF EECON1, WR4-bit Command
1234 121516
P5 P5A
P10
12
n
Poll WR bit, Repeat Until Clear
16-bit Data
Payload
1234 121516 123
P5 P5A
41 2 15 16
P5 P5A
0000
MOVF EECON1, W, 04-bit Command
0000
4-bit Command Shift Out Data
MOVWF TABLAT
SCLK
SDATA
(see below)
(see Figure 4-6)
SDATA = Input SDATA = Output
Poll WR bit
2010 Microchip Technology Inc. DS39576C-page 17
PIC18FXX2/XX8
TABLE 3-6: PROGRAMMING DATA MEMORY
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Load the data to be written.
0000
0000
0E <Data>
6E A8
MOVLW <Data>
MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 A6 BSF EECON1, WREN
Step 5: Perform required sequence.
0000
0000
0000
0000
0E 55
6E A7
0E AA
6E A7
MOVLW 0X55
MOVWF EECON2
MOVLW 0XAA
MOVWF EECON2
Step 6: Initiate write.
0000 82 A6 BSF EECON1, WR
Step 7: Poll WR bit, repeat until the bit is clear.
0000
0000
0010
50 A6
6E F5
<LSB><MSB>
MOVF EECON1, W, 0
MOVWF TABLAT
Shift out data(1)
Step 8: Disable writes.
0000 94 A6 BCF EECON1, WREN
Repeat steps 2 through 8 to write more data.
Note 1: See Figure 4-4 for details on Shift Out Data timing.
PIC18FXX2/XX8
DS39576C-page 18 2010 Microchip Technology Inc.
3.4 ID Location Programming
The ID locations are programmed much like the code
memory, except that multi-panel writes must be
disabled. The single panel that will be written will auto-
matically be enabled, based on the value of the Table
Pointer. The ID registers are mapped in addresses
200000h through 200007h. These locations read out
normally, even after code protection.
Figure 3-7 demonstrates the code sequence required
to write the ID locations.
TABLE 3-7: WRITE ID SEQUENCE
In order to modify the ID locations, refer to the
methodology described in Section 3.2.2, “Modifying
Code Memory”. As with code memory, the ID locations
must be erased before modified.
Note: For single panel programming, the user
must still fill the 8-byte data buffer for the
panel.
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
8E A6
8C A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 00h to 3C0006h to enable single panel writes.
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 4: Load write buffer. Panel will be automatically determined by address.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
<LSB><MSB>
00 00
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and post-increment address by 2
Write 2 bytes and start programming
NOP - hold SCLK high for time P9
2010 Microchip Technology Inc. DS39576C-page 19
PIC18FXX2/XX8
3.5 Boot Block Programming
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.4).
Multi-panel writes must be disabled so that only
addresses in the range 0000h to 01FFh will be written.
The code sequence detailed in Figure 3-7 should be
used, except that the address data used in “Step 3” will
be in the range 000000h to 0001FFh.
3.6 Configuration Bits Programming
Unlike code memory, the configuration bits are pro-
grammed a byte at a time. The “Table Write, Begin Pro-
gramming” (4-bit command, ‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses,
and the MSB will be written to odd addresses. The
code sequence to program two consecutive
configuration locations is shown in Figure 3-8.
TABLE 3-8: SET ADDRESS POINTER TO CONFIGURATION LOCATION
FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
8E A6
8C A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Position the program counter(1).
0000
0000
EF 00
F8 00
GOTO 100000h
Step 3(2): Set Table Pointer for config byte to be written. Write even/odd addresses.
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table writes. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 100000h).
2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
bits. Always write all the configuration bits before enabling the write protection for configuration bits.
Load Even
Configuration
Start
Program Program
MSB
Done
Delay P9 Time
for Write
Delay P9 Time
for Write
LSB
Load Odd
Configuration
Address Address
Done
Start
PIC18FXX2/XX8
DS39576C-page 20 2010 Microchip Technology Inc.
4.0 READING THE DEVICE
4.1 Read Code Memory, ID Locations,
and Configuration Bits
Code memory is accessed one byte at a time, via the
4-bit command,1001’ (Table Read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
Table Latch and then serially output on SDATA.
The 4-bit command is shifted in LSb first. The Read is
executed during the next 8 clocks, then shifted out on
SDATA during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
SCLK of the operand to allow SDATA to transition from
an input to an output. During this time, SCLK must be
held low (see Table 4-1). This operation also
increments the Table Pointer pointer by one, pointing to
the next byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and configuration registers.
TABLE 4-1: READ CODE MEMORY SEQUENCE
FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4-Bit
Command Data Payload Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.
1001 00 00 TBLRD *+
1234
SCLK
P5
SDATA
SDATA = Input
Shift Data Out
P6
SDATA = Output
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-bit Command
1001
SDATA = Input
LSb MSb
123456
1234
nnnn
P14
2010 Microchip Technology Inc. DS39576C-page 21
PIC18FXX2/XX8
4.2 Verify Code Memory and ID
locations
The verify step involves reading back the code memory
space and comparing against the copy held in the pro-
grammer’s buffer. Memory reads occur a single byte at
a time, so two bytes must be read to compare against
the word in the programmer’s buffer. Refer to
Section 4.1 for implementation details of reading code
memory.
The Table Pointer must be manually set to 200000h
(base address of the ID locations) once the code mem-
ory has been verified. The post-increment feature of
the Table Read 4-bit command may not be used to
increment the Table Pointer beyond 1FFFFFh.
FIGURE 4-2: VERIFY CODE MEMORY FLOW
Read Low Byte
Read High Byte
Does
word = expect
data? Failure,
Report
Error
All
code memory
verified?
No
Yes
No
Set Pointer = 0
Start
Set Pointer = 200000h
Yes
Read Low Byte
Read High Byte
Does
word = expect
data? Failure,
Report
Error
All
ID locations
verified?
No
Yes
Done
Yes
No
PIC18FXX2/XX8
DS39576C-page 22 2010 Microchip Technology Inc.
4.3 Verify Configuration Bits
A configuration address may be read and output on
SDATA via the 4-bit command, ‘1001. Configuration
data is read and written in a bytewise fashion, so it is
not necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 for implementation details of reading
configuration data.
4.4 Read Data EEPROM Memory
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is read by loading EEADR with the
desired memory location and initiating a memory read
by appropriately configuring the EECON1 register. The
data will be loaded into EEDATA, where it may be seri-
ally output on SDATA via the 4-bit command, ‘0010
(shift out data holding register). A delay of P6 must be
introduced after the falling edge of the 8th SCLK of the
operand to allow SDATA to transition from an input to
an output. During this time, SCLK must be held low
(see Figure 4-4).
The command sequence to read a single byte of data
is shown in Figure 4-2.
FIGURE 4-3: READ DATA EEPROM
FLOW
TABLE 4-2: READ DATA EEPROM MEMORY
Start
Set
Address
Read
Byte
Done
No
Yes
Done?
Move to TABLAT
Shift Out Data
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Initiate a memory read.
0000 80 A6 BSF EECON1, RD
Step 4: Load data into the serial data holding register.
0000
0000
0010
50 A8
6E F5
<LSB><MSB>
MOVF EEDATA, W, 0
MOVWF TABLAT
Shift Out Data(1)
Note 1: The <LSB> is undefined. The <MSB> is the data.
"w“ 7 " v
2010 Microchip Technology Inc. DS39576C-page 23
PIC18FXX2/XX8
FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
4.5 Verify Data EEPROM
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on SDATA via the 4-bit command, ‘0010’ (shift
out data holding register). The result may then be
immediately compared to the appropriate data in the
programmer’s memory for verification. Refer to
Section 4.4 for implementation details of reading data
EEPROM.
4.6 Blank Check
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations,
and configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’. So,
“Blank Checking” a device merely means to verify that
all bytes read as FFh, except the configuration bits.
Unused (reserved) configuration bits will read ‘0’ (pro-
grammed). Refer to Table 5-2 for blank configuration
expect data for the various PIC18FXX2/XX8 devices.
If it is determined that the device is not blank, then the
device should be Bulk Erased (see Section 3.1) before
any attempt to program is made.
Given that “Blank Checking” is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 and Section 4.2 for implementation details.
FIGURE 4-5: BLANK CHECK FLOW
1234
SCLK
P5
SDATA
SDATA = Input
Shift Data Out
P6
SDATA = Output
5678 1234
P5A
91011 13 15161412
Fetch Next 4-bit Command
0100
SDATA = Input
LSb MSb
123456
1234
nnnn
P14
Yes
No
Start
Blank Check Device
Is
device
blank? Continue
Abort
PIC18FXX2/XX8
DS39576C-page 24 2010 Microchip Technology Inc.
5.0 CONFIGURATION WORD
The PIC18FXX2/XX8 has several configuration words.
These bits can be set or cleared to select various
device configurations. All other memory areas should
be programmed and verified prior to setting configura-
tion words. These bits may be read out normally, even
after read or code protected.
5.1 ID Locations
A user may store identification information (ID) in eight
ID locations mapped in 200000h:200007h. It is
recommended that the most significant nibble of each
ID be 0Fh. In doing so, if the user code inadvertently
tries to execute from the ID space, the ID data will
execute as NOP.
5.2 Device ID Word
The device ID word for the PIC18FXX2/XX8 is located
at 3FFFFEh:3FFFFFh. These bits may be used by the
programmer to identify what device type is being pro-
grammed and read out normally, even after code or
read protected.
5.3 Low Voltage Programming
(LVP) Bit
The LVP bit in configuration register CONFIG4L
enables low voltage ICSP programming. The LVP bit
defaults to a ‘1’ from the factory.
If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed by entering the High Voltage ICSP mode,
where MCLR/VPP is raised to VIHH. Once the LVP bit is
programmed to a ‘0’, only the High Voltage ICSP mode
is available and only the High Voltage ICSP mode can
be used to program the device.
.
TABLE 5-1: DEVICE ID VALUE
Note 1: The normal ICSP mode is always avail-
able, regardless of the state of the LVP bit,
by applying VIHH to the MCLR/VPP pin.
2: While in Low Voltage ICSP mode, the RB5
pin can no longer be used as a general
purpose I/O. The RB5 pin should be held
low during normal operation to protect
against inadvertent ICSP mode entry.
Device Device ID Value
DEVID2 DEVID1
PIC18F242 04h 100x xxxx
PIC18F248 08h 000x xxxx
PIC18F252 04h 000x xxxx
PIC18F258 08h 010x xxxx
PIC18F442 04h 101x xxxx
PIC18F448 08h 001x xxxx
PIC18F452 04h 001x xxxx
PIC18F458 08h 011x xxxx
2010 Microchip Technology Inc. DS39576C-page 25
PIC18FXX2/XX8
TABLE 5-2: PIC18FXX2/XX8 CONFIGURATION BITS AND DEVICE IDS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Erased or
“Blank” Value
300000h CONFIG1L 0000 0000
300001h CONFIG1H —OSCEN—FOSC2FOSC1FOSC00010 0111
300002h CONFIG2L BORV1 BORV2 BOREN PWRTE 0000 1111
300003h CONFIG2H WDTPS2 WDTPS1 WDTPS0 WDTEN 0000 1111
300004h CONFIG3L 0000 0000
300005h CONFIG3H — — —CCP2MX*0000 0001
300006h CONFIG4L BKBUG — — —LVP—STVREN1000 0101
300007h CONFIG4H 0000 0000
300008h CONFIG5L CP3 CP2 CP1 CP0 0000 1111
300009h CONFIG5H CPD CPB 1100 0000
30000Ah CONFIG6L WRT3 WRT2 WRT1 WRT0 0000 1111
30000Bh CONFIG6H WRTD WRTB WRTC 1110 0000
30000Ch CONFIG7L EBTR3 EBTR2 EBTR1 EBTR0 0000 1111
30000Dh CONFIG7H —EBTRB 0100 0000
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1
* This bit only applies to the PIC18FXX2 devices.
PIC18FXX2/XX8
DS39576C-page 26 2010 Microchip Technology Inc.
TABLE 5-3: PIC18FXX2/XX8 BIT DESCRIPTION
Bit Name Configuration
Words Description
OSCEN CONFIG1H Low Power System Clock Option (Timer1) Enable bit
1 = Disabled
0 = Timer1 oscillator system clock option enabled
FOSC2:FOSC0 CONFIG1H Oscillator Selection bits
111 = RC oscillator w/ OSC2 configured as RA6
110 = HS oscillator w/ PLL enabled
101 = EC oscillator w/ OSC2 configured as RA6
100 = RC oscillator w/ OSC2 configured as “divide by 4 clock output”
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits
11 =V
BOR set to 2.0V
10 =V
BOR set to 2.7V
01 =V
BOR set to 4.2V
00 =V
BOR set to 4.5V
BOREN CONFIG2L Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTPS2:WDTPS0 CONFIG2H Watchdog Timer Postscaler Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
CCP2MX(1) CONFIG3H CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
BKBUG CONFIG4L Background Debugger Enable bit
1 = Background debugger disabled
0 = Background debugger enabled
LVP CONFIG4L Low Voltage Programming Enable bit
1 = Low voltage programming enabled
0 = Low voltage programming disabled
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Stack overflow/underflow will cause RESET
0 = Stack overflow/underflow will not cause RESET
Note 1: This bit only applies to the PIC18FXX2 devices.
2: These bits only apply to the PIC18FX52/X58 devices.
2010 Microchip Technology Inc. DS39576C-page 27
PIC18FXX2/XX8
CP0 CONFIG5L Code Protection bits (code memory area 0200h - 1FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP1 CONFIG5L Code Protection bits (code memory area 2000h - 3FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP2(2) CONFIG5L Code Protection bits (code memory area 4000h - 5FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CP3(2) CONFIG5L Code Protection bits (code memory area 6000h - 7FFFh)
1 = Code memory not code protected
0 = Code memory code protected
CPD CONFIG5H Code Protection bits (data EEPROM)
1 = Data EEPROM not code protected
0 = Data EEPROM code protected
CPB CONFIG5H Code Protection bits (boot block, memory area 0000h - 01FFh)
1 = Boot block not code protected
0 = Boot block code protected
WRT0 CONFIG6L Table Write Protection bit (code memory area 0200h - 1FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT1 CONFIG6L Table Write Protection bit (code memory area 2000h - 3FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT2(2) CONFIG6L Table Write Protection bit (code memory area 4000h - 5FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRT3(2) CONFIG6L Table Write Protection bit (code memory area 6000h - 7FFFh)
1 = Code memory not write protected
0 = Code memory write protected
WRTD CONFIG6H Table Write Protection bit (data EEPROM)
1 = Data EEPROM not write protected
0 = Data EEPROM write protected
WRTB CONFIG6H Table Write Protection bit (boot block, memory area 0000h - 01FFh)
1 = Boot block not write protected
0 = Boot block write protected
WRTC CONFIG6H Table Write Protection bit (Configuration registers)
1 = Configuration registers not write protected
0 = Configuration registers write protected
TABLE 5-3: PIC18FXX2/XX8 BIT DESCRIPTION (CONTINUED)
Bit Name Configuration
Words Description
Note 1: This bit only applies to the PIC18FXX2 devices.
2: These bits only apply to the PIC18FX52/X58 devices.
PIC18FXX2/XX8
DS39576C-page 28 2010 Microchip Technology Inc.
5.4 Embedding Configuration Word
Information in the HEX File
To allow portability of code, a PIC18FXX2/XX8 pro-
grammer is required to read the configuration word
locations from the HEX file. If configuration word infor-
mation is not present in the HEX file, then a simple
warning message should be issued. Similarly, while
saving a HEX file, all configuration word information
must be included. An option to not include the configu-
ration word information may be provided. When
embedding configuration word information in the HEX
file, it should start at address 300000h.
Microchip Technology Inc. feels strongly that this
feature is important for the benefit of the end customer.
5.5 Checksum Computation
The checksum is calculated by summing the following:
The contents of all code memory locations
The configuration word, appropriately masked
ID locations
The Least Significant 16-bits of this sum are the
checksum.
Table 5-4 describes how to calculate the checksum for
each device.
EBTR0 CONFIG7L Table Read Protection bit (code memory area 0200h - 01FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit (code memory area 2000h - 3FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR2(2) CONFIG7L Table Read Protection bit (code memory area 4000h - 5FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR3(2) CONFIG7L Table Read Protection bit (code memory area 6000h - 7FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (boot block, memory area 0000h - 01FFh)
1 = Boot block not protected from table reads executed in other blocks
0 = Boot block protected from table reads executed in other blocks
DEV10:DEV3 DEVID2 Device ID bits
These bits are used with the DEV2:DEV0 bits in the DEVID1 register to
identify part number.
DEV2:DEV0 DEVID1 Device ID bits
These bits are used with the DEV10:DEV3 bits in the DEVID2 register to
identify part number.
REV4:REV0 DEVID1 These bits are used to indicate the revision of the device.
TABLE 5-3: PIC18FXX2/XX8 BIT DESCRIPTION (CONTINUED)
Bit Name Configuration
Words Description
Note 1: This bit only applies to the PIC18FXX2 devices.
2: These bits only apply to the PIC18FX52/X58 devices.
Note 1: The checksum calculation differs depend-
ing on the code protect setting. Since the
code memory locations read out differently
depending on the code protect setting, the
table describes how to manipulate the
actual code memory values to simulate the
values that would be read from a protected
device. When calculating a checksum by
reading a device, the entire code memory
can simply be read and summed. The con-
figuration word and ID locations can
always be read.
Descnghon
2010 Microchip Technology Inc. DS39576C-page 29
PIC18FXX2/XX8
TABLE 5-4: CHECKSUM COMPUTATION
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
PIC18F242 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L &
0000)+(CFGW1H & 0027)+(CFGW2L + 000F)&(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
C2B4 C20A
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
C491 C437
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028E 289
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028E 289
PIC18F248 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L &
0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
C2B3 C209
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L & 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
C48F C435
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028C 287
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L & 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028C 287
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+ = Addition
& = Bitwise AND
Descnghon
PIC18FXX2/XX8
DS39576C-page 30 2010 Microchip Technology Inc.
PIC18F252 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM
(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
82D8 822E
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
84B7 845D
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
C2B4 C25A
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
02A8 02A3
PIC18F258 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM
(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
82D7 822D
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0000)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
84B5 845B
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
C2B2 C258
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
02A6 02A1
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+ = Addition
& = Bitwise AND
Descnghon
2010 Microchip Technology Inc. DS39576C-page 31
PIC18FXX2/XX8
PIC18F442 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L &
0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
C3B4 C20A
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
C491 C437
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028E 289
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028E 289
PIC18F448 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L &
0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)
C2B3 C209
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 0003)+(CFGW5H & 00C0)+(CFGW6L &
0003)+(CFGW6H & 00E0)+(CFGW7L & 0003)+(CFGW7H &
0040)+SUM(IDs)
C48F C435
Boot/Panel1/Panel2 (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028C 287
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 0003)+(CFGW5H &
00C0)+(CFGW6L & 0003)+(CFGW6H & 00E0)+(CFGW7L &
0003)+(CFGW7H & 0040)+SUM(IDs)
028C 287
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+ = Addition
& = Bitwise AND
Descnghon
PIC18FXX2/XX8
DS39576C-page 32 2010 Microchip Technology Inc.
PIC18F452 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM
(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
82D8 822E
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0001)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
84B7 845D
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0001)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
C2B4 C25A
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0001)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
02A8 02A3
PIC18F458 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+SUM
(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)
82D7 822D
Boot Block SUM(0200:1FFF)+SUM(2000:3FFF)+SUM(4000:5FFF)+SUM
(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L +
000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H &
0000)+(CFGW4L & 0085)+(CFGW4H & 0000)+(CFGW5L &
000F)+(CFGW5H & 00C0)+(CFGW6L & 000F)+(CFGW6H &
00E0)+(CFGW7L & 000F)+(CFGW7H & 0040)+SUM(IDs)
84B5 845B
Boot/Panel1/Panel2 SUM(4000:5FFF)+SUM(6000:7FFF)+(CFGW1L & 0000)+(CFGW1H &
0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L &
0000)+(CFGW3H & 0000)+(CFGW4L & 0085)+(CFGW4H &
0000)+(CFGW5L & 000F)+(CFGW5H & 00C0)+(CFGW6L &
000F)+(CFGW6H & 00E0)+(CFGW7L & 000F)+(CFGW7H &
0040)+SUM(IDs)
C2B2 C258
All (CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H &
000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L &
0085)+(CFGW4H & 0000)+(CFGW5L & 000F)+(CFGW5H &
00C0)+(CFGW6L & 000F)+(CFGW6H & 00E0)+(CFGW7L &
000F)+(CFGW7H & 0040)+SUM(IDs)
02A6 02A1
TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum Blank
Value
0xAA at 0
and Max
Address
Legend: Item Description
CFGW = Configuration Word
SUM[a:b] = Sum of locations a to b inclusive
SUM_ID = Bytewise sum of lower four bits of all customer ID locations
+ = Addition
& = Bitwise AND
2010 Microchip Technology Inc. DS39576C-page 33
PIC18FXX2/XX8
5.6 Embedding Data EEPROM
Information In the HEX File
To allow portability of code, a PIC18FXX2/XX8
programmer is required to read the data EEPROM
information from the HEX file. If data EEPROM infor-
mation is not present, a simple warning message
should be issued. Similarly, when saving a HEX file, all
data EEPROM information must be included. An option
to not include the data EEPROM information may be
provided. When embedding data EEPROM information
in the HEX file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
PIC18FXX2/XX8
DS39576C-page 34 2010 Microchip Technology Inc.
6.0 AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 10C to 50C unless otherwise indicated
Param
No. Sym Characteristic Min Max Units Conditions
D110 VIHH High Voltage Programming Voltage on
MCLR/VPP
9.00 13.25 V
D110A VIHLLow Voltage Programming Voltage on
MCLR/VPP
2.00 5.50 V
D111 VDD Supply Voltage during programming 2.00 5.50 V Normal
programming
4.50 5.50 V Bulk erase
operations
D112 IPP Programming Current on MCLR/VPP 300 A
D113 IDDP Supply Current during programming 5 mA
D031 VIL Input Low Voltage VSS 0.2 VSS V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage 0.6 V IOL = 8.5 mA
D090 VOH Output High Voltage VDD – 0.7 V IOH = -3.0 mA
D012 CIO Capacitive loading on I/O pin (SDATA) 50 pF To meet AC
specifications
P2 Tsclk Serial Clock (SCLK) period 100 ns VDD = 5.0V
1—sVDD = 2.0V
P2A TsclkL Serial Clock (SCLK) Low time 40 ns VDD = 5.0V
400 ns VDD = 2.0V
P2B TsclkH Serial Clock (SCLK) High time 40 ns VDD = 5.0V
400 ns VDD = 2.0V
P3 Tset1 Input Data Setup Time to serial clock 15 — ns
P4 Thld1 Input Data Hold Time from SCLK 15 — ns
P5 Tdly1 Delay between 4-bit command and
command operand 20 — ns
P5A Tdly1a Delay between 4-bit command
operand and next 4-bit command 20 — ns
P6 Tdly2 Delay between last SCLK of
command byte to first SCLK of read
of data word
20 — ns
P9 Tdly5 SCLK High time
(minimum programming time) 1—ms
P10 Tdly6 SCLK Low time after programming
(high voltage discharge time) 5—s
P11 Tdly7 Delay to allow self-timed data write or
bulk erase to occur 10 — ms
P12 Thld2 Input Data Hold time from
MCLR/VPP
2—s
P13 Tset2 VDD Setup time to MCLR/VPP 100 — ns
P14 Tvalid Data Out Valid from SCLK 10 — ns
P15 Tset3 PGM Setup time to MCLR/VPP 2—s
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS “5949:2002 =
2010 Microchip Technology Inc. DS39576C-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Q ‘MICROCHIP
DS39576C-page 36 2010 Microchip Technology Inc.
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01/05/10

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