FDMC8360LET40 Datasheet by ON Semiconductor

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September 2015
©2015 Fairchild Semiconductor Corporation
FDMC8360LET40 Rev.1.0 www.fairchildsemi.com
1
FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET
BottomTop
Pin 1
Pin 1
G
D
S
S
S
D
DD
S
S
S
G
D
D
D
D
Power33
FDMC8360LET40
N-Channel Shielded Gate Power Trench® MOSFET
40 V, 141 A, 2.1 mΩ
Features
Shielded Gate MOSFET Technology
Max rDS(on) = 2.1 mΩ at VGS = 10 V, ID = 27 A
Max rDS(on) = 3.1 mΩ at VGS = 4.5 V, ID = 22 A
High Performance Technology for Extremely Low rDS(on)
Termination is Lead-free
100% UIL Tested
RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates shielded gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Application
DC-DC Conversion
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 40 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous TC = 25 °C (Note 5) 141
A
-Continuous TC = 100 °C (Note 5) 100
-Continuous TA = 25 °C (Note 1a) 27
-Pulsed (Note 4) 658
EAS Single Pulse Avalanche Energy (Note 3) 253 mJ
PDPower Dissipation TC = 25 °C 75 W
Power Dissipation TA = 25 °C (Note 1a) 2.8
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +175 °C
RθJC Thermal Resistance, Junction to Case (Note 1) 2.0 °C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 53
Device Marking Device Package Reel Size Tape Width Quantity
FDMC8360LET FDMC8360LET40 Power33 13 ’’ 12 mm 3000 units
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2
©2015 Fairchild Semiconductor Corporation
FDMC8360LET40 Rev.1.0
FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min. Typ. Max. Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 40 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 20 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.7 3.0 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C -6 mV/°C
rDS(on) Static Drain to Source On Resistance
VGS = 10 V, ID = 27 A 1.4 2.1
mΩVGS = 4.5 V, ID = 22 A 2.1 3.1
VGS = 10 V, ID = 27 A, TJ = 150 °C 2.3 3.5
gFS Forward Transconductance VDD = 5 V, ID = 27 A 138 S
Ciss Input Capacitance VDS = 20 V, VGS = 0 V,
f = 1 MHz
3785 5300 pF
Coss Output Capacitance 1220 1710 pF
Crss Reverse Transfer Capacitance 57 80 pF
RgGate Resistance 0.1 0.8 1.6 Ω
td(on) Turn-On Delay Time
VDD = 20 V, ID = 27 A,
VGS = 10 V, RGEN = 6 Ω
14 26 ns
trRise Time 816ns
td(off) Turn-Off Delay Time 35 57 ns
tfFall Time 714ns
Qg(TOT) Total Gate Charge VGS = 0 V to 10 V
VDD = 20 V,
ID = 27 A
57 80 nC
Qg(TOT) Total Gate Charge VGS = 0 V to 4.5 V 27 38 nC
Qgs Gate to Source Charge 9.9 nC
Qgd Gate to Drain “Miller” Charge 8.1 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 27 A (Note 2) 0.8 1.3 V
VGS = 0 V, IS = 1.9 A (Note 2) 0.7 1.2 V
trr Reverse Recovery Time IF = 27 A, di/dt = 100 A/μs 47 76 ns
Qrr Reverse Recovery Charge 30 48 nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 253 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 13 A, VDD = 40 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 42 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
53°C/W when mounted on a
1 in2 pad of 2 oz copper
125°C/W when mounted on a
minimum pad
a) b)
G
DF
DS
SF
SS
G
DF
DS
SF
SS
/ PULSE DURATION : an f/ // // / b / PULSE DURATION : an J I PuLsE DufiATION : so PULSE DURATION : an
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3
©2015 Fairchild Semiconductor Corporation
FDMC8360LET40 Rev.1.0
FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted.
Figure 1.
0123
0
75
150
225
300
VGS = 4 V
VGS = 3.5 V
VGS = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
0 60 120 180 240 300
0
2
4
6
8
10
VGS = 3 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 4.5 V
VGS = 4 V
VGS = 10 V
VGS = 3.5 V
N o rmali z e d O n - R e s i s t a n c e
vs. Drain Current and Gate Voltage
Fi gu r e 3 . No rm a l i z e d O n Re s i s ta nc e
-75 -50 -25 0 25 50 75 100 125 150 175
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
ID = 27 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
vs. Junction Temperature Figure 4.
246810
0
5
10
15
20
TJ = 150 oC
ID = 27 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
O n- Re si st an ce vs . Ga t e to
Source Voltage
Figure 5. Transfer Characteristics
12345
0
60
120
180
240
300
TJ = 175 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.00.20.40.60.81.01.2
0.001
0.01
0.1
1
10
100
300
TJ = -55 oC
TJ = 25 oC
TJ = 175 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
S ou rc e t o D ra in Di o de
Forward Voltage vs. Source Current
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4
©2015 Fairchild Semiconductor Corporation
FDMC8360LET40 Rev.1.0
FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET
Figure 7.
0 1224364860
0
2
4
6
8
10
ID = 27 A
VDD = 25 V
VDD = 20 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
Gate Charge Characteristics Figure 8.
0.1 1 10 40
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
C a p a c i t a n c e v s . D r a i n
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100 500
1
10
100
TJ = 125 oC
TJ = 25 oC
TJ = 150 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
U n c l a m p e d I n d u c t i v e
Switching Capability Figure 10.
25 50 75 100 125 150 175
0
30
60
90
120
150
VGS = 6 V
RθJC = 2.0 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
M a x i m u m C o n t i n u o u s D r a i n
Current vs. Case Temperature
Figure 11. Forward Bias Safe
Operating Area
0.1 1 10 100 200
0.1
1
10
100
1000
CURVE BENT TO
MEASURED DATA
10 us
100 ms/DC
10 ms
1 ms
100 us
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 2.0 oC/W
TC = 25 oC
Figure 12.
10-5 10-4 10-3 10-2 10-1 1
10
100
1000
10000
100000
SINGLE PULSE
RθJC = 2.0 oC/W
TC = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
S i n g l e P u l s e M a x i m u m
Power Dissipation
Typical Characteristics TJ = 25°C unless otherwise noted.
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5
©2015 Fairchild Semiconductor Corporation
FDMC8360LET40 Rev.1.0
FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET
Figure 13. Junction-to-Case Transient Thermal Response Curve
10-5 10-4 10-3 10-2 10-1 1
0.001
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 2.0 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJC(t) + TC
Typical Characteristics TJ = 25°C unless otherwise noted.
\
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: PQFN08HREV1
8
1
5
4
41
85
LAND PATTERN
RECOMMENDATION
14
85
PKG
C
L
PKG
L
C
PKG L
C
L
C
SYM
PKG
C
L
A
B
SCALE: 2X
SEE
DETAIL A
3.40
3.20
3.40
3.20
1.95
0.65
0.37
0.27 (8X)
0.50
0.30
2.05
1.85
0.10 C A B
(0.34)
(2.27)(0.52 TYP)
0.25
0.15
0.80
0.70
0.10 C
0.08 C0.05
0.00 C
SEATING
PLANE
2.37 MIN
(0.45)
(0.40)
(0.65)
2.15 MIN
0.70 MIN
0.42 MIN
(8X)
1.95
0.65
PIN 1
INDICATOR
(0.33) TYP
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www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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