MCP2542/44FD,WFD Datasheet by Microchip Technology

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2016-2019 Microchip Technology Inc. DS20005514B-page 1
MCP2542FD/4FD,
MCP2542WFD/4WFD
Features
Supports CAN 2.0 and CAN with Flexible Data
Rate (CAN FD) Physical Layer Transceiver
Requirements
• Optimized for CAN FD at 2, 5 and 8 Mbps
Operation
- Maximum propagation delay: 120 ns
- Loop delay symmetry: -10%/+10% (2 Mbps)
• MCP2542FD/4FD:
- Wake-up on CAN activity, 3.6 µs filter time
• MCP2542WFD/4WFD:
- Wake-up on Pattern (WUP), as specified in
ISO 11898-2:2016, 3.6 µs activity filter time
Implements ISO 11898-2:2003, ISO
11898-5:2007, and ISO 11898-2:2016
Qualification: AEC-Q100 Rev. G, Grade 0 (-40°C
to +150°C)
Very Low Standby Current (4 µA, typical)
•V
IO Supply Pin to Interface Directly to CAN Con-
trollers and Microcontrollers with 1.8V to 5V I/O
CAN Bus Pins are Disconnected when Device is
Unpowered
- An unpowered node or brown-out event will
not load the CAN bus
- Device is unpowered if VDD or VIO drop
below its POR level
Detection of Ground Fault:
- Permanent Dominant detection on TXD
- Permanent Dominant detection on bus
Automatic Thermal Shutdown Protection
Suitable for 12V and 24V Systems
Meets or Exceeds Stringent Automotive Design
Requirements Including “Hardware Requirements
for LIN, CAN and FlexRay Interfaces in
Automotive Applications”, Version 1.3, May 2012
- Conducted emissions @ 2 Mbps with
Common-Mode Choke (CMC)
- Direct Power Injection (DPI) @ 2 Mbps with
CMC
Meets SAE J2962/2 “Communication Transceiver
Qualification Requirements - CAN
- Radiated emissions @ 2 Mbps without a
CMC
High Electrostatic Discharge (ESD) Protection on
CANH and CANL, meeting IEC61000-4-2 up
to ±13 kV
Temperature ranges:
- Extended (E): -40°C to +125°C
- High (H): -40°C to +150°C
Description
The MCP2542FD/4FD and MCP2542WFD/4WFD
CAN transceiver family is designed for high-speed
CAN FD applications up to 8 Mbps communication
speed. The maximum propagation delay was improved
to support longer bus length.
The device meets the automotive requirements for
CAN FD bit rates exceeding 2 Mbps, low quiescent
current, electromagnetic compatibility (EMC) and
electrostatic discharge (ESD).
Applications
CAN 2.0 and CAN FD networks in Automotive,
Industrial, Aerospace, Medical, and Consumer
applications.
Package Types
MCP2542FD
MCP2542WFD
8-Lead SOIC
V
DD
V
SS
R
XD
CANH
CANL
1
2
3
4
8
7
6
5V
IO
STBYT
XD
MCP2544FD
MCP2544WFD
8-Lead SOIC
V
DD
V
SS
R
XD
CANH
CANL
1
2
3
4
8
7
6
5NC
STBYT
XD
V
DD
V
SS
R
XD
CANH
CANL
1
2
3
4
8
7
6
5NC
STBYT
XD
EP
9
V
DD
V
SS
R
XD
CANH
CANL
1
2
3
4
8
7
6
5V
IO
STBYT
XD
EP
9
* Includes Exposed Thermal Pad (EP); see Table 1-1.
MCP2544FD
MCP2544WFD
3x3 DFN*
MCP2542FD
MCP2542WFD
3x3 DFN*
V
DD
V
SS
R
XD
CANH
CANL
1
2
3
4
8
7
6
5
V
IO
STBYT
XD
EP
9
V
DD
V
SS
R
XD
CANH
CANL
1
2
3
4
8
7
6
5
NC
STBYT
XD
EP
9
MCP2542FD
MCP2542WFD
2x3 TDFN*
MCP2544FD
MCP2544WFD
2x3 TDFN*
CAN FD Transceiver with Wake-Up Pattern (WUP) Option
Device VIO pin WUP Description
MCP2542FD Yes No
MCP2544FD No No Internal level shifter on digital I/O pins
MCP2542WFD Yes Yes Wake-Up on Pattern (see Section 1.6.5)
MCP2544WFD No Yes Internal level shifter on digital I/O pins; Wake-Up on Pattern
Note: For ordering information, see the Product Identification System section.
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 2 2016-2019 Microchip Technology Inc.
MCP2542FD/4FD, MCP2542WFD/4WFD Family Members
Block Diagram
Note 1: There is one receiver implemented. The receiver can operate in Low-Power or High-Speed mode.
2: Only MCP2542FD and MCP2542WFD have the VIO pin.
3: In the MCP2544FD and MCP2544WFD, the supply for the digital I/O is internally connected to VDD.
VDD
CANH
CANL
TXD
RXD
Driver
and
Slope Control
Thermal
Protection
POR
UVLO
Digital I/O
Supply
VIO
VSS
STBY
Permanent Dominant
Detect
VIO
VIO
Mode Control
Wake-Up
Filter
CANH
CANL
CANH
CANL
LP_RX
HS_RX
VDD
VDD
2016-2019 Microchip Technology Inc. DS20005514B-page 3
MCP2542FD/4FD, MCP2542WFD/4WFD
1.0 DEVICE OVERVIEW
The MCP2542FD/4FD and MCP2542WFD/4WFD
devices serve as the interface between a CAN protocol
controller and the physical bus. The devices provide
differential transmit and receive capability for the CAN
protocol controller. The devices are fully compatible
with the ISO 11898-2 and ISO 11898-5 standards, and
with ISO 11898-2:2016.
Excellent Loop Delay Symmetry supports data rates up
to 8 Mbps for CAN FD. The maximum propagation
delay was improved to support longer bus length.
Typically, each node in a CAN system must have a
device to convert the digital signals generated by a
CAN controller to signals suitable for transmission over
the bus cabling (differential output). It also provides a
buffer between the CAN controller and the high-voltage
spikes that can be generated on the CAN bus by
outside sources.
The MCP2542FD/4FD wakes up on CAN activity (basic
wake-up). The CAN activity filter time is 3.6 µs maximum.
The MCP2542WFD/4WFD wakes up after receiving
two consecutive dominant states separated by a reces-
sive state: WUP. The minimum duration of each domi-
nant and recessive state is tFILTER. The complete WUP
has to be detected within tWAKE(TO).
1.1 Transmitter Function
The CAN bus has two states: Dominant and
Recessive. A Dominant state occurs when the
differential voltage between CANH and CANL is
greater than VDIFF(D)(I). A Recessive state occurs
when the differential voltage is less than VDIFF(R)(I).
The Dominant and Recessive states correspond to the
Low and High states of the TXD input pin, respectively.
However, a Dominant state initiated by another CAN
node will override a Recessive state on the CAN bus.
1.2 Receiver Function
In Normal mode, the RXD output pin reflects the
differential bus voltage between CANH and CANL. The
Low and High states of the RXD output pin correspond
to the Dominant and Recessive states of the CAN bus,
respectively.
1.3 Internal Protection
CANH and CANL are protected against battery short
circuits and electrical transients that can occur on the
CAN bus. This feature prevents destruction of the
transmitter output stage during such a fault condition.
The device is further protected from excessive current
loading by thermal shutdown circuitry that disables the
output drivers when the junction temperature exceeds
a nominal limit of +175°C.
All other parts of the chip remain operational, and the
chip temperature is lowered due to the decreased
power dissipation in the transmitter outputs. This
protection is essential to protect against bus line
short-circuit-induced damage. Thermal protection is
only active during Normal mode.
1.4 Permanent Dominant Detection
The MCP2542FD/4FD and MCP2542WFD/4WFD
device prevents two conditions:
Permanent Dominant condition on TXD
Permanent Dominant condition on the bus
In Normal mode, if the MCP2542FD/4FD and
MCP2542WFD/4WFD detects an extended Low state
on the TXD input, it will disable the CANH and CANL
output drivers in order to prevent the corruption of data
on the CAN bus. The drivers will remain disabled until
TXD goes High. The high-speed receiver is active and
data on the CAN bus is received on RXD.
In Standby mode, if the MCP2542FD/4FD and
MCP2542WFD/4WFD detects an extended dominant
condition on the bus, it will set the RXD pin to a
Recessive state. This allows the attached controller to
go to Low-Power mode until the dominant issue is
corrected. RXD is latched High until a Recessive state
is detected on the bus and the Wake-Up function is
enabled again.
1.5 Power-On Reset (POR) and
Undervoltage Detection
The MCP2542FD/4FD and MCP2542WFD/4WFD
have POR detection on both supply pins: VDD and VIO.
Typical POR thresholds to deassert the Reset are 1.2V
and 3.0V for VIO and VDD, respectively.
When the device is powered on, CANH and CANL
remain in a high-impedance state until VDD exceeds its
undervoltage level. Once powered on, CANH and
CANL will enter a high-impedance state if the voltage
level at VDD drops below the undervoltage level,
providing voltage brown-out protection during normal
operation.
In Normal mode, the receiver output is forced to
Recessive state during an undervoltage condition on
VDD. In Standby mode, the low-power receiver is
designed to work down to 1.7V VIO. Therefore, the
low-power receiver remains operational down to VPORL
on VDD (MCP2544FD and MCP2544WFD). The
MCP2542FD and MCP2542WFD transfers data to the
RXD pin down to 1.7V on the VIO supply.
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 4 2016-2019 Microchip Technology Inc.
1.6 Mode Control
The main difference between the MCP2542FD/4FD
and MCP2542WFD/4WFD is the wake-up method.
Figure 1-1 shows the state diagram of the
MCP2542FD/4FD. The devices wake up on CAN activity.
Figure 1-2 shows the state diagram of the
MCP2542WFD/4WFD. The devices wake up on a
WUP.
1.6.1 UNPOWERED MODE (POR)
The MCP2542FD/4FD and MCP2542WFD/4WFD
enter Unpowered mode under the following conditions:
After powering up the device, or
•If VDD drops below VPORL, or
•If VIO drops below VPORL_VIO.
In Unpowered mode, the CAN bus will be biased to
ground using a high impedance. The
MCP2542FD/4FD and MCP2542WFD/4WFD are not
able to communicate on the bus or detect a wake-up
event.
1.6.2 WAKE MODE
The MCP2542FD/4FD and MCP2542WFD/4WFD
transitions from Unpowered mode to Wake mode
when VDD and VIO are above their PORH levels. From
Normal mode, the device will also enter Wake mode if
VDD is smaller than VUVL, or if the band gap output
voltage is not within valid range. Additionally, the
device will transition from Standby mode to Wake
mode if STBY is pulled Low.
In Wake mode, the CAN bus is biased to ground and
RXD is always high.
1.6.3 NORMAL MODE
When VDD exceeds VUVH, the band gap is within valid
range and TXD is High, the device transitions into
Normal mode. During POR, when the microcontroller
powers up, the TXD pin could be unintentionally pulled
down by the microcontroller powering up. To avoid
driving the bus during a POR of the microcontroller,
the transceiver proceeds to Normal mode only after
TXD is high.
In Normal mode, the driver block is operational and
can drive the bus pins. The slopes of the output
signals on CANH and CANL are optimized to reduce
Electromagnetic Emissions (EME). The CAN bus is
biased to VDD/2.
The high-speed differential receiver is active.
1.6.4 STANDBY MODE
The device may be placed in Standby mode by
applying a high level to the STBY pin. In Standby
mode, the transmitter and the high-speed part of the
receiver are switched off to minimize power
consumption.
The low-power receiver and the wake-up block are
enabled in order to monitor the bus for activity. The
CAN bus is biased to ground.
The RXD pin remains HIGH until a wake-up event has
occurred.
The MCP2542FD/4FD uses Basic Wake-Up: one
dominant phase for a minimum time of tFILTER will
wake up the device.
The MCP2542WFD/4WFD will only wake up if it
detects a complete WUP. The WUP method is
described in the next section.
After a wake-up event was detected, the CAN
controller gets interrupted by a negative edge on the
RXD pin.
The CAN controller must put the MCP2542FD/4FD and
MCP2542WFD/4WFD back into Normal mode by
deasserting the STBY pin in order to enable
high-speed data communication.
The CAN bus Wake-Up function requires both supply
voltages, VDD and VIO, to be in valid range.
1.6.5 REMOTE WAKE-UP VIA CAN BUS (WUP)
The MCP2542WFD/4WFD wakes up from
Standby/Silent mode when a dedicated wake-up pat-
tern (WUP) is detected on the CAN bus. The wake-up
pattern is specified in ISO 11898-6 and ISO
11898-2:2016 (see Figure 1-2 and Figure 2-11).
The Wake-Up Pattern consists of three events:
a Dominant phase of at least tFILTER, followed by
a Recessive phase of at least tFILTER, followed by
a Dominant phase of at least tFILTER
The complete pattern must be received within
tWAKE(TO). Otherwise, the internal wake-up logic is
reset and the complete wake-up pattern must be
retransmitted in order to trigger a wake-up event.
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2016-2019 Microchip Technology Inc. DS20005514B-page 5
MCP2542FD/4FD, MCP2542WFD/4WFD
FIGURE 1-1: MCP2542FD/4FD STATE DIAGRAM: BASIC WAKE-UP
VDD >VPORH
And
VIO >VPORH_VIO
And
STBY High
Bandgap not OK
Or
VDD <VUVL
TXD High
And
Bandgap OK
And
VDD >VUVH
Bus Recessive
Bus Dominant > tPDT
STBY Low
TXD High
And
T < TJ(SD)-TJ(HYST)
TXD Low > TPDT
Or
T>TJ(SD)
VDD >VPORH
And
VIO >VPORH_VIO
And
STBY Low
Normal
CAN Driven
Common mode VDD/2
HS RX ON
Wake-Up Disabled
RXD =f(HS RX)
TXD Time Out
CAN Recessive
Common mode VDD/2
HS RX ON
Wake-Up Disabled
5;' I+65;
UnSowered (POR)
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Disabled
RXD High
Bandgap OFF
From any
Vtate
Standby
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Enabled
RXD =f(LP RX)
Stop Bandgap
Bus Dominant
Time Out
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Disabled
RXD High
Wake
Start Bandgap
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Disabled
RXD High
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MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 6 2016-2019 Microchip Technology Inc.
FIGURE 1-2: MCP2542WFD/4WFD STATE DIAGRAM: WAKE-UP
tWAKE(TO)
Expired
Bus Recessive
Bus Dominant > tFI LT ER
Bus Recessive > tFI LTER
Bus Dominant > tFI LT ER
Bandgap Not Ok
Or
VDD < VUVL
TXD High
And
Bandgap OK
And
VDD > VUVH
Bus Dominant > tPDT
STBY High
TXD High
And
T < TJ(SD)-TJ(HYST)
TXD Low > TPDT
Or
T > TJ(SD)
VDD > VPORH
And
VIO > VPORH_VIO
And
STBY Low
Normal
CAN Driven
Common mode VDD/2
HS RX ON
Wake-Up Disabled
RXD = f(HS RX)
TXD Time Out
CAN Recessive
Common mode VDD/2
HS RX ON
Wake-Up Disabled
RXD = f(HS RX)
UnPowered (POR)
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Disabled
RXD High
Bandgap OFF
From any
State
Standby Init
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Enabled
RXD High
Stop Bandgap
Wake
Start Bandgap
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Disabled
RXD High
Standby 1
Start tWAKE TIME OUT
RXD High
Standby 2
RXD High
Standby/Receiving
CAN High Impedance
Common mode tied to GND
HS RX OFF
RXD = f(LP RX)
Standby
Bus Dominant
Time Out
CAN High Impedance
Common mode tied to GND
HS RX OFF
Wake-Up Disabled
RXD High
Standby 3
RXD High
PATTERN
2016-2019 Microchip Technology Inc. DS20005514B-page 7
MCP2542FD/4FD, MCP2542WFD/4WFD
1.7 Pin Descriptions
The description of the pins are listed in Table 1-1.
TABLE 1-1: MCP2542/4FD AND MCP2542/4WFD PIN DESCRIPTIONS
MCP2542FD
MCP2542WFD
3x3 DFN,
2x3TDFN
MCP2542FD
MCP2542WFD
SOIC
MCP2544FD
MCP2544WFD
3x3 DFN,
2x3TDFN
MCP2544FD
MCP2544WFD
SOIC
Symbol Pin Function
1111TXD Transmit Data Input
2222VSS Ground
3333VDD Supply Voltage
4444RXD Receive Data Output
5 5 NC No Connect
5 5 — VIO Digital I/O Supply Pin
6666CANL CAN Low-Level Voltage I/O
7777CANH CAN High-Level Voltage I/O
8888STBY Standby Mode Input
9 — 9 — EP Exposed Thermal Pad
1.7.1 TRANSMITTER DATA
INPUT PIN (TXD)
The CAN transceiver drives the differential output pins
CANH and CANL according to TXD. It is usually
connected to the transmitter data output of the CAN
controller device. When TXD is Low, CANH and CANL
are in the Dominant state. When TXD is High, CANH
and CANL are in the Recessive state, provided that
another CAN node is not driving the CAN bus with a
Dominant state. TXD is connected from an internal
pull-up resistor (nominal 33 k) to VIO in the
MCP2542FD and MCP2542WFD, and to VDD in the
MCP2544FD and MCP2544WFD.
1.7.2 GROUND SUPPLY PIN (VSS)
Ground supply pin.
1.7.3 SUPPLY VOLTAGE PIN (VDD)
Positive supply voltage pin. Supplies transmitter and
receiver, including the wake-up receiver.
1.7.4 RECEIVER DATA OUTPUT PIN (RXD)
RXD is a CMOS-compatible output that drives High or
Low depending on the differential signals on the CANH
and CANL pins, and is usually connected to the
receiver data input of the CAN controller device. RXD is
High when the CAN bus is Recessive, and Low in the
Dominant state. RXD is supplied by VIO in the
MCP2542FD and MCP2542WFD and by VDD in the
MCP2544FD and MCP2544WFD.
1.7.5 NC PIN (MCP2544FD AND
MCP2544WFD)
No Connect. This pin can be left open or connected to
VSS.
1.7.6 VIO PIN (MCP2542FD AND
MCP2542WFD)
Supply for digital I/O pins. In the MCP2544FD and
MCP2544WFD, the supply for the digital I/O (TXD, RXD
and STBY) is internally connected to VDD.
1.7.7 DIGITAL I/O
The MCP2542FD/4FD and MCP2542WFD/4WFD
enable easy interfacing to MCU with I/O ranges from
1.8V to 5V.
1.7.7.1 MCP2544FD and MCP2544WFD
The VIH(MIN) and VIL(MAX) for STBY and TXD are
independent of VDD. They are set at levels that are
compatible with 3V and 5V microcontrollers.
The RXD pin is always driven to VDD, therefore a 3V
microcontroller will need a 5V tolerant input.
1.7.7.2 MCP2542FD and MCP2542WFD
VIH and VIL for STBY and TXD depend on VIO. The
RXD pin is driven to VIO.
1.7.8 CAN LOW PIN (CANL)
The CANL output drives the Low side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANL disconnects from the
bus when MCP2542FD/4FD and
MCP2542WFD/4WFD are not powered.
1.7.9 CAN HIGH PIN (CANH)
The CANH output drives the high side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANH disconnects from the
bus when MCP2542FD/4FD and
MCP2542WFD/4WFD are not powered.
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 8 2016-2019 Microchip Technology Inc.
1.7.10 STANDBY MODE INPUT PIN (STBY)
This pin selects between Normal or Standby mode. In
Standby mode, the transmitter and high-speed receiver
are turned off, only the low-power receiver and wake-up
filter are active. STBY is connected from an internal
MOS pull-up resistor to VIO in the MCP2542FD and
MCP2542WFD, and to VDD in the MCP2544FD and
MCP2544WFD. The value of the MOS pull-up resistor
depends on the supply voltage. Typical values are
660 k for 5V, 1.1 M for 3.3V and 4.4 M for 1.8V.
1.7.11 EXPOSED THERMAL PAD (EP)
It is recommended to connect this pad to VSS to
enhance electromagnetic immunity and thermal
resistance.
XZ —IH
2016-2019 Microchip Technology Inc. DS20005514B-page 9
MCP2542FD/4FD, MCP2542WFD/4WFD
1.8 Typical Applications
In order to meet the EMC/EMI requirements, a
Common Mode Choke (CMC) may be required for data
rates greater than 1 Mbps. Figure 1-3 and Figure 1-4
illustrate examples of typical applications of the
devices.
FIGURE 1-3: MCP2544WFD
5V LDO
VBAT
VDD VDD
TXD
RXD
STBY
CANTX
CANRX
RBX
VSS VSS
PIC® MCU
MCP2544WFD
NC
CANH
CANL
0.1 µF
CANH
CANL
4700 pF
60
60
WITH NC AND SPLIT TERMINATION
FIGURE 1-4: MCP2542FD WITH VIO PIN
3.3V LDO
V
DD
V
DD
TXD
RXD
STBY
CANTX
CANRX
RBX
V
SS
V
SS
PIC® MCU
MCP2542FD
CANH
CANL
5V LDO
V
BAT
V
IO
0.1 µF
0.1 µF
CANH
CANL
120
EN
RBX
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 10 2016-2019 Microchip Technology Inc.
NOTES:
\\\\\\\\\
2016-2019 Microchip Technology Inc. DS20005514B-page 11
MCP2542FD/4FD, MCP2542WFD/4WFD
2.0 ELECTRICAL
CHARACTERISTICS
2.1 Terms and Definitions
A number of terms are defined in ISO 11898 that are
used to describe the electrical characteristics of a CAN
transceiver device. These terms and definitions are
summarized in this section.
2.1.1 BUS VOLTAGE
VCANL and VCANH denote the voltages of the bus line
wires CANL and CANH relative to the ground of each
individual CAN node.
2.1.2 COMMON MODE BUS VOLTAGE
RANGE
Boundary voltage levels of VCANL and VCANH with
respect to ground, for which proper operation will occur,
if up to the maximum number of CAN nodes are
connected to the bus.
2.1.3 DIFFERENTIAL INTERNAL
CAPACITANCE, CDIFF
(OF A CAN NODE)
Capacitance seen between CANL and CANH during
the Recessive state when the CAN node is
disconnected from the bus (see Figure 2-1).
2.1.4 DIFFERENTIAL INTERNAL
RESISTANCE, RDIFF
(OF A CAN NODE)
Resistance seen between CANL and CANH during the
Recessive state when the CAN node is disconnected
from the bus (see Figure 2-1).
2.1.5 DIFFERENTIAL VOLTAGE, VDIFF
(OF CAN BUS)
Differential voltage of the two-wire CAN bus, with value
equal to VDIFF = VCANH – VCANL.
2.1.6 INTERNAL CAPACITANCE, CIN
(OF A CAN NODE)
Capacitance seen between CANL (or CANH) and
ground during the Recessive state when the CAN node
is disconnected from the bus (see Figure 2-1).
2.1.7 INTERNAL RESISTANCE, RIN
(OF A CAN NODE)
Resistance seen between CANL (or CANH) and
ground during the Recessive state when the CAN node
is disconnected from the bus (see Figure 2-1).
FIGURE 2-1: PHYSICAL LAYER
DEFINITIONS
RIN
RIN RDIFF
CIN CIN
CDIFF
CANL
CANH
GROUND
ECU
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 12 2016-2019 Microchip Technology Inc.
2.2 Absolute Maximum Ratings†
VDD.............................................................................................................................................................................7.0V
VIO ..............................................................................................................................................................................7.0V
DC Voltage at TXD, RXD, STBY and VSS.............................................................................................-0.3V to VIO + 0.3V
DC Voltage at CANH and CANL .................................................................................................................. -58V to +58V
Transient Voltage on CANH and CANL (ISO-7637) (Figure 2-5) ............................................................. -150V to +100V
Differential Bus Input Voltage VDIFF(I) (t = 60 days, continuous)....................................................................-5V to +10V
Differential Bus Input Voltage VDIFF(I) (1000 pulses, t = 0.1 ms, VCANH = +18V) .....................................................+17V
Dominant State Detection VDIFF(I) (10000 pulses, t = 1 ms).......................................................................................+9V
Storage temperature ...............................................................................................................................-55°C to +150°C
Operating ambient temperature ..............................................................................................................-40°C to +150°C
Virtual Junction Temperature, TVJ (IEC60747-1) ....................................................................................-40°C to +190°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on CANH and CANL pins (IEC 61000-4-2) ...................................................................................±13 kV
ESD protection on CANH and CANL pins (IEC 801; Human Body Model)..............................................................±8 kV
ESD protection on all other pins (IEC 801; Human Body Model).............................................................................±4 kV
ESD protection on all pins (IEC 801; Machine Model) ............................................................................................±400V
ESD protection on all pins (IEC 801; Charge Device Model)..................................................................................±750V
† Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2016-2019 Microchip Technology Inc. DS20005514B-page 13
MCP2542FD/4FD, MCP2542WFD/4WFD
TABLE 2-1: DC CHARACTERISTICS
DC Specifications Electrical Characteristics: Unless otherwise indicated, Extended (E): TAMB = -40°C
to +125°C and High (H): T
AMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.7V to 5.5V (Note 2), RL = 60CL = 100 pF; unless
otherwise specified.
Parameter Sym. Min. Typ. Max. Units Conditions
Supply
VDD Pin
Voltage Range VDD 4.5 5.5 V
Supply Current IDD 2.5 5mA Recessive; VTXD = VDD
55 70 Dominant; VTXD = 0V
Standby Current IDDS — 4 15 µA MCP2544FD and
MCP2544WFD,
Bus Recessive
— 4 16 MCP2542FD and
MCP2542WFD, Includes IIO
Maximum Supply Current IDDMAX 95 140 mA Fault condition: VTXD = VSS;
VCANH = VCANL = -5V to +18V
(Note 1)
High Level of the POR
Comparator for VDD
VPORH 3.0 3.95 VNote 1
Low Level of the POR
Comparator for VDD
VPORL 1.0 2.0 3.2 VNote 1
Hysteresis of POR
Comparator for VDD
VPORD 0.2 0.9 2.0 VNote 1
High Level of the UV
Comparator for VDD
VUVH 4.0 4.25 4.4 V
Low Level of the UV
Comparator for VDD
VUVL 3.6 3.8 4.0 V
Hysteresis of UV comparator VUVD 0.4 VNote 1
VIO Pin
Digital Supply Voltage Range VIO 1.7 5.5 V
Supply Current on VIO IIO — 7 20 µA Recessive; VTXD = VIO
200 400 Dominant; VTXD = 0V
Standby Current IDDS 0.3 2µA Bus Recessive (Note 1)
High Level of the POR
Comparator for VIO
VPORH_VIO 0.8 1.2 1.7 V
Low Level of the POR
Comparator for VIO
VPORL_VIO 0.7 1.1 1.4 V
Hysteresis of POR
Comparator for VIO
VPORD_VIO 0.2 V
Bus Line (CANH; CANL) Transmitter
CANH; CANL:
Recessive Bus Output Voltage
VO(R)2.0 0.5 VDD 3.0 VVTXD = VDD; No load
CANH; CANL:
Bus Output Voltage in Standby
VO(S)-0.1 0.0 +0.1 VSTBY = VTXD = VDD; No load
Note 1: Characterized; not 100% tested.
2: Only MCP2542FD and MCP2542WFD have a VIO pin. For the MCP2544FD and MCP2544WFD, VIO is
internally connected to VDD.
3: -12V to 12V is ensured by characterization, and tested from -2V to 7V.
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 14 2016-2019 Microchip Technology Inc.
Recessive Output Current IO(R)-5 +5 mA -24V < VCAN < +24V
CANH: Dominant Output
Voltage
VO(D)2.75 3.50 4.50 VTXD = 0; RL = 50 to 65
CANL: Dominant Output
Voltage
0.50 1.50 2.25 RL = 50 to 65
Driver Symmetry
(VCANH+VCANL)/VDD
VSYM 0.9 1.0 1.1 V1 MHz square wave,
Recessive and Dominant
states, and transition (Note 1)
Dominant: Differential Output
Voltage
VO(DIFF)(D)1.5 2.0 3.0 V VTXD = VSS; RL = 50 to 65
(Figure 2-2, Figure 2-4,
Section 3.0) (Note 1)
1.4 2.0 3.3 VTXD = VSS; RL = 45 to 70
(Figure 2-2, Figure 2-4,
Section 3.0) (Note 1)
1.3 2.0 3.3 VTXD = VSS; RL = 40 to 75
(Figure 2-2, Figure 2-4)
1.5 5.0 VTXD = VSS; RL = 2240
(Figure 2-2, Figure 2-4,
Section 3.0) (Note 1)
Recessive:
Differential Output Voltage
VO(DIFF)(R)-500 050 mV VTXD = VDD, no load, Normal.
(Figure 2-2, Figure 2-4)
VO(DIFF)(S)-200 0200 VTXD = VDD,no load, Standby.
Figure 2-2, Figure 2-4
CANH: Short-Circuit
Output Current
IO(SC)-115 -85 mA VTXD = VSS; VCANH = -3V;
CANL: floating
CANL: Short Circuit
Output Current
75 +115 mA VTXD = VSS; VCANL = +18V;
CANH: floating
Bus Line (CANH; CANL) Receiver
Recessive Differential
Input Voltage
VDIFF(R)(I)-4.0 +0.5 VNormal Mode;
-12V < V(CANH, CANL) < +12V;
see Figure 2-6 (Note 3)
-4.0 +0.4 Standby Mode;
-12V < V(CANH, CANL) < +12V;
see Figure 2-6 (Note 3)
Dominant Differential
Input Voltage
VDIFF(D)(I)0.9 9.0 VNormal Mode;
-12V < V(CANH, CANL) < +12V;
see Figure 2-6 (Note 3)
1.1 9.0 Standby Mode;
-12V < V(CANH, CANL) < +12V;
see Figure 2-6 (Note 3)
TABLE 2-1: DC CHARACTERISTICS (CONTINUED)
DC Specifications Electrical Characteristics: Unless otherwise indicated, Extended (E): TAMB = -40°C
to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.7V to 5.5V (Note 2), RL = 60CL = 100 pF; unless
otherwise specified.
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Characterized; not 100% tested.
2: Only MCP2542FD and MCP2542WFD have a VIO pin. For the MCP2544FD and MCP2544WFD, VIO is
internally connected to VDD.
3: -12V to 12V is ensured by characterization, and tested from -2V to 7V.
2016-2019 Microchip Technology Inc. DS20005514B-page 15
MCP2542FD/4FD, MCP2542WFD/4WFD
Differential
Receiver Threshold
VTH(DIFF)0.5 0.7 0.9 VNormal Mode;
-12V < V(CANH, CANL) < +12V;
see Figure 2-6 (Note 3)
0.4 0.7 0.9 Standby Mode;
-12V < V(CANH, CANL) < +12V;
see Figure 2-6 (Note 3)
Differential
Input Hysteresis
VHYS(DIFF)30 200 mV Normal mode, see Figure 2-6,
(Note 1)
Single Ended
Input Resistance
RCAN_H,
RCAN_L
6 50 kNote 1
Internal
Resistance Matching
mR=2*(RCANH-RCANL)/(RCANH+RCANL)
mR-3 0+3 % VCANH = VCANL (Note 1)
Differential Input
Resistance
RDIFF 12 25 100 kNote 1
Internal Capacitance CIN 20 pF 1 Mbps (Note 1)
Differential
Internal Capacitance
CDIFF 10 pF 1 Mbps (Note 1)
CANH, CANL:
Input Leakage
ILI -5 +5 µA VDD = VTXD = VSTBY = 0V.
For MCP2542FD and
MCP2542WFD, VIO = 0V.
VCANH = VCANL = 5 V.
Digital Input Pins (TXD, STBY)
High-Level Input Voltage VIH 2.0 VDD + 0.3 VMCP2544FD and
MCP2544WFD
0.7 VIO — VIO + 0.3 MCP2542FD and
MCP2542WFD
Low-Level Input Voltage VIL -0.3 0.8 VMCP2544FD and
MCP2544WFD
-0.3 0.3VIO MCP2542FD and
MCP2542WFD
High-Level Input Current IIH -1 +1 µA
TXD: Low-Level Input Current IIL(TXD)-270 -150 -30 µA
STBY: Low-Level Input
Current
IIL(STBY)-30 -1 µA
TABLE 2-1: DC CHARACTERISTICS (CONTINUED)
DC Specifications Electrical Characteristics: Unless otherwise indicated, Extended (E): TAMB = -40°C
to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.7V to 5.5V (Note 2), RL = 60CL = 100 pF; unless
otherwise specified.
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Characterized; not 100% tested.
2: Only MCP2542FD and MCP2542WFD have a VIO pin. For the MCP2544FD and MCP2544WFD, VIO is
internally connected to VDD.
3: -12V to 12V is ensured by characterization, and tested from -2V to 7V.
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 16 2016-2019 Microchip Technology Inc.
Receive Data (RXD) Output
High-Level Output Voltage VOH VDD - 0.4 V MCP2544FD and
MCP2544WFD: IOH = -2 mA;
typical -4 mA
VIO - 0.4 — — MCP2542FD and
MCP2542WFD:
VIO = 2.7V to 5.5V,
IOH = -1 mA;
VIO = 1.7V to 2.7V,
IOH = -0.5 mA,
typical -2 mA
Low-Level Output Voltage VOL 0.4 V IOL = 4 mA; typical 8 mA
Thermal Shutdown
Shutdown
Junction Temperature
TJ(SD)165 175 185 °C -12V < V(CANH, CANL) < +12V
(Note 1)
Shutdown
Temperature Hysteresis
TJ(HYST)15 30 °C -12V < V(CANH, CANL) < +12V
(Note 1)
TABLE 2-1: DC CHARACTERISTICS (CONTINUED)
DC Specifications Electrical Characteristics: Unless otherwise indicated, Extended (E): TAMB = -40°C
to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.7V to 5.5V (Note 2), RL = 60CL = 100 pF; unless
otherwise specified.
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Characterized; not 100% tested.
2: Only MCP2542FD and MCP2542WFD have a VIO pin. For the MCP2544FD and MCP2544WFD, VIO is
internally connected to VDD.
3: -12V to 12V is ensured by characterization, and tested from -2V to 7V.
2016-2019 Microchip Technology Inc. DS20005514B-page 17
MCP2542FD/4FD, MCP2542WFD/4WFD
FIGURE 2-2: PHYSICAL BIT REPRESENTATION AND SIMPLIFIED BIAS IMPLEMENTATION
CANH, CANL
Time
CANH
CANL
Normal Mode Standby Mode
Recessive Recess iveDominant
CANL
CANH
VDD/2 RXD
VDD
Normal
Standby
Mode
TABLE 2-2: AC CHARACTERISTICS
AC Characteristics Electrical Characteristics: Unless otherwise indicated, Extended (E):
TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.7V to 5.5V (Note 2), RL = 60CL = 100 pF.
Maximum VDIFF(D)(I) = 3V.
Param.
No. Parameter Sym. Min. Typ. Max. Units Conditions
1Bit Time tBIT 0.125 69.44 µs
2Nominal Bit Rate NBR 14.4 8000 kbps
3Delay TXD Low to Bus
Dominant
tTXD-BUSON 50 85 ns Note 1
4Delay TXD High to Bus
Recessive
tTXD-BUSOFF 40 85 ns Note 1
5Delay Bus Dominant to
RXD
tBUSON-RXD 70 85 ns Note 1
Note 1: Characterized, not 100% tested.
2: Only MCP2542FD and MCP2542WFD have a VIO pin. For the MCP2544FD and MCP2544WFD, VIO is
internally connected to VDD.
3: Characterized. Not in ISO 11898 2:2016.
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 18 2016-2019 Microchip Technology Inc.
6Delay Bus Recessive to
RXD
tBUSOFF-RXD 110 145 ns Note 1
7Propagation Delay TXD to
RXD
Worst Case of tLOOP(R)
and tLOOP(F) Figure 2-10
tTXD - RXD 90 120 ns
115 150 RL = 150,
CL = 200pF(Note 1)
7a Propagation Delay,
Rising Edge
tLOOP(R) — 90 120 ns
7b Propagation Delay,
Falling Edge
tLOOP(F) — 80 120 ns
8a Recessive Bit Time on
RXD – 1 Mbps,
Loop Delay Symmetry
(Note 3)
tBIT(RXD), 1M900 985 1100 ns tBIT(TXD) = 1000 ns
(Figure 2-10)
800 960 1255 tBIT(TXD) = 1000 ns
(Figure 2-10), RL = 150,
CL = 200pF (Note 1)
8b Recessive Bit Time on
RXD – 2 Mbps,
Loop Delay Symmetry
tBIT(RXD), 2M450 490 550 ns tBIT(TXD) = 500 ns
(Figure 2-10)
400 460 550 tBIT(TXD) = 500 ns
(Figure 2-10), RL = 150,
CL = 200pF(Note 1)
8c Recessive Bit Time on
RXD – 5 Mbps,
Loop Delay Symmetry
tBIT(RXD), 5M160 190 220 ns tBIT(TXD) = 200 ns
(Figure 2-10)
8d Recessive Bit Time on
RXD – 8 Mbps,
Loop Delay Symmetry
(Note 3)
tBIT(RXD), 8M85 100 135 ns tBIT(TXD) = 120 ns
(Figure 2-10) (Note 1)
9CAN Activity Filter Time
(Standby)
tFILTER 0.5 1.7 3.6 µs VDIFF(D)(I) = 1.2V to 3V
10 Delay Standby to Normal
Mode
tWAKE 7 30 µs Negative edge on STBY
11 Permanent Dominant
Detect Time
tPDT 0.8 1.9 5ms TXD = 0V
12 Permanent Dominant
Timer Reset
tPDTR 5 ns The shortest recessive
pulse on TXD or CAN bus
to reset Permanent
Dominant Timer
TABLE 2-2: AC CHARACTERISTICS (CONTINUED)
AC Characteristics Electrical Characteristics: Unless otherwise indicated, Extended (E):
TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.7V to 5.5V (Note 2), RL = 60CL = 100 pF.
Maximum VDIFF(D)(I) = 3V.
Param.
No. Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Characterized, not 100% tested.
2: Only MCP2542FD and MCP2542WFD have a VIO pin. For the MCP2544FD and MCP2544WFD, VIO is
internally connected to VDD.
3: Characterized. Not in ISO 11898 2:2016.
2016-2019 Microchip Technology Inc. DS20005514B-page 19
MCP2542FD/4FD, MCP2542WFD/4WFD
13a Transmitted Bit Time on
Bus – 1 Mbps
(Note 3)
tBIT(BUS), 1M870 1000 1060 ns tBIT(TXD) = 1000 ns
(Figure 2-10)
870 1000 1060 tBIT(TXD) = 1000 ns
(Figure 2-10),
RL = 150, CL = 200pF
(Note 1)
13b Transmitted Bit Time on
Bus – 2 Mbp
tBIT(BUS), 2M435 515 530 ns tBIT(TXD) = 500 ns
(Figure 2-10)
435 480 550 tBIT(TXD) = 500 ns
(Figure 2-10) RL = 150,
CL = 200pF (Note 1)
13c Transmitted Bit Time on
Bus – 5 Mbps
tBIT(BUS), 5M155 200 210 ns tBIT(TXD) = 200ns
(Figure 2-10) (Note 1)
13d Transmitted Bit Time on
Bus - 8Mbps
(Note 3)
tBIT(BUS), 8M100 125 140 ns tBIT(TXD) = 120 ns
(Figure 2-10) (Note 1)
14a Receiver Timing
Symmetry – 1 Mbps
(Note 3)
tDIFF(REC), 1M
=
tBIT(RXD)
-
tBIT(BUS)
-65 040 ns tBIT(TXD) = 1000 ns
(Figure 2-10)
-130 080 tBIT(TXD) = 1000ns
(Figure 2-10), RL = 150,
CL = 200pF (Note 1)
14b Receiver Timing
Symmetry – 2 Mbps
tDIFF(REC), 2M-65 040 ns tBIT(TXD) = 500 ns
(Figure 2-10)
-70 040 tBIT(TXD) = 500 ns
(Figure 2-10), RL = 150,
CL = 200pF (Note 1)
14c Receiver Timing
Symmetry – 5 Mbps
tDIFF(REC), 5M-45 015 ns tBIT(TXD) = 200 ns
(Figure 2-10) (Note 1)
14d Receiver Timing
Symmetry – 8 Mbps
(Note 3) tDIFF(REC),8M
tDIFF(REC), 8M-45 010 ns tBIT(TXD) = 120 ns
(Figure 2-10) (Note 1)
15 WUP Time Out tWAKE(TO) 1 1.9 5ms MCP2542WFD/4WFD
(Figure 2-11)
16 Delay Bus
Dominant/Recessive to
RXD (Standby mode)
tBUS-RXD(S) — 0.5 µs
TABLE 2-2: AC CHARACTERISTICS (CONTINUED)
AC Characteristics Electrical Characteristics: Unless otherwise indicated, Extended (E):
TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.7V to 5.5V (Note 2), RL = 60CL = 100 pF.
Maximum VDIFF(D)(I) = 3V.
Param.
No. Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Characterized, not 100% tested.
2: Only MCP2542FD and MCP2542WFD have a VIO pin. For the MCP2544FD and MCP2544WFD, VIO is
internally connected to VDD.
3: Characterized. Not in ISO 11898 2:2016.
Load Condi‘ion 1 Load Condi‘ion 2 i i i i
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 20 2016-2019 Microchip Technology Inc.
FIGURE 2-3: TEST LOAD CONDITIONS
FIGURE 2-4:
Test Circuit for Electrical Characteristics
GND
RXD
TXD
RLCL
15 pF
CANH
CANL
CAN
Transceiver
0.1 µF
VDD
STBY
Note: On MCP2544FD and MCP2544WFD, VIO is connected to VDD.
FIGURE 2-5: TEST CIRCUIT FOR AUTOMOTIVE TRANSIENTS
GND
RXD
TXD
RL
1000 pF
1000 pF
Note 1: On MCP2544FD and MCP2544WFD, VIO is connected to VDD.
2: The wave forms of the applied transients shall be in accordance with ISO-7637,
Part 1, test pulses 1, 2, 3a and 3b.
CANH
CANL
CAN
Transceiver
Transient
Generator
STBY
2016-2019 Microchip Technology Inc. DS20005514B-page 21
MCP2542FD/4FD, MCP2542WFD/4WFD
FIGURE 2-6: HYSTERESIS OF THE RECEIVER
VOH
VOL
0.5 0.9
VDIFF (H)(I)
VDIFF (V)
RXD (receive data
output voltage)
VDIFF (R)(I)VDIFF (D)(I)
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 22 2016-2019 Microchip Technology Inc.
2.3 Timing Diagrams and Specifications
FIGURE 2-7: TIMING DIAGRAM FOR AC CHARACTERISTICS
3
74
7
0V
VDD
TXD (transmit data
input voltage)
VDIFF (CANH,
CANL differential
voltage)
RXD (receive data
output voltage) 5
6
FIGURE 2-8: TIMING DIAGRAM FOR WAKEUP FROM STANDBY
TXD
STBY
VCANH
VCANL
10
FIGURE 2-9: PERMANENT DOMINANT TIMER RESET DETECT
30 | —> <— —=""> 500 mV + <—>
2016-2019 Microchip Technology Inc. DS20005514B-page 23
MCP2542FD/4FD, MCP2542WFD/4WFD
FIGURE 2-10: TIMING DIAGRAM FOR LOOP DELAY SYMMETRY
TXD
5*tBIT(TXD)
TBIT(TXD)
tBIT(RXD)
RXD
8
30%
70%
30%
70%
30%
VDIFF_BUS
tBIT(BUS)
13
500 mV 900 mV
tLOOP(R)
tLOOP(F)
FIGURE 2-11: TIMING DIAGRAM FOR WAKE-UP PATTERN
CANH
tFI LT ER
(9)
RXD
CANL
tFILT ER
(9)
tFI LT ER
(9)
t < tWAKE(TO) (15)
tBUS-RXD(S)
(16)
tBUS-RXD(S)
(16)
(WUP)
TABLE 2-3: THERMAL SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Units Test Conditions
Temperature Ranges
Specified Temperature Range TA-40 +125 C
-40 +150
Operating Temperature Range TA-40 +150 C
Storage Temperature Range TA-65 +155 C
Package Thermal Resistances
Thermal Resistance, 8LD DFN (3x3) JA 56.7 C/W
Thermal Resistance, 8LD SOIC JA 149.5 C/W
Thermal Resistance, 8LD TDFN (2x3) JA 53 C/W
H+ 4H H+
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 24 2016-2019 Microchip Technology Inc.
3.0 TYPICAL PERFORMANCE CURVES
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
40 45 50 55 60 65 70 75
Dominant Differential Output (V)
RL (ɏ)
VDD = 4.5 V
-40
25
150
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
FIGURE 3-1: Dominant Differential Output
vs. RL (VDD = 4.5V).
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
40 45 50 55 60 65 70 75
Dominant Differential Output (V)
RL (ɏ)
VDD = 5.0 V
-40
25
150
FIGURE 3-2: Dominant Differential Output
vs. RL (VDD = 5.0V).
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
40 45 50 55 60 65 70 75
Dominant Differential Output (V)
RL (ɏ)
VDD = 5.5 V
-40
25
150
FIGURE 3-3: Dominant Differential Output
vs. RL (VDD = 5.5V).
2016-2019 Microchip Technology Inc. DS20005514B-page 25
MCP2542FD/4FD, MCP2542WFD/4WFD
NOTES:
THHH XXXXXXXX
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 26 2016-2019 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
Example:
8-Lead DFN (03x03x0.9 mm)
Part Number Code
MCP2542FD-E/MF DAEK
MCP2542FDT-H/MF DAEK
MCP2542FD-H/MF DAEK
MCP2542FDT-E/MF DAEK
MCP2542WFD-E/MF DAEH
MCP2542WFDT-H/MF DAEH
MCP2542WFD-H/MF DAEH
MCP2542WFDT-E/MF DAEH
MCP2544FD-E/MF DAEJ
MCP2544FDT-H/MF DAEJ
MCP2544FD-H/MF DAEJ
MCP2544FDT-E/MF DAEJ
MCP2544WFD-E/MF DAEG
MCP2544WFDT-H/MF DAEG
MCP2544WFD-H/MF DAEG
MCP2544WFDT-E/MF DAEG
DAEK
1538
256
Example:
8-Lead SOIC (150 mil)
MCP2542W
SN 1538
256
3
e
Part Number Code
MCP2542WFD-E/SN MCP2542W
MCP2542WFDT-H/SN MCP2542W
MCP2542WFD-H/SN MCP2542W
MCP2542WFDT-E/SN MCP2542W
MCP2542FD-E/SN MCP2542
MCP2542FDT-H/SN MCP2542
MCP2542FD-H/SN MCP2542
MCP2542FDT-E/SN MCP2542
MCP2544WFD-E/SN MCP2544W
MCP2544WFDT-H/SN MCP2544W
MCP2544WFD-H/SN MCP2544W
MCP2544WFD-E/SN MCP2544W
MCP2544FD-E/SN MCP2544
MCP2544FDT-H/SN MCP2544
MCP2544FD-H/SN MCP2544
MCP2544FDT-E/SN MCP2544
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC®designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC® designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.
3
e
3
e
LJ u u u XXX YWW LNN r1 r1 r1 r1 u u u u L L r1 r1 r1 r1 \le \PIN1
Example:8-Lead TDFN (02x03x0.8 mm) Part Number Code
MCP2542FDT-E/MNY ACR
MCP2542FDT-H/MNY ACR
MCP2542WFDT-E/MNY ACP
MCP2542WFDT-H/MNY ACP
MCP2544FDT-E/MNY ACQ
MCP2544FDT-H/MNY ACQ
MCP2544WFDT-E/MNY ACN
MCP2544WFDT-H/MNY ACN
ACQ
607
25
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC®designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC® designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.
2016-2019 Microchip Technology Inc. DS20005514B-page 27
MCP2542FD/4FD, MCP2542WFD/4WFD
8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9mm Body [DFN] TOP VIEW (DATUM A) (DATUM B) N _. |._ gXb 4} 0.0703 C A\a| 0.05® c BOTTOM VIEW Mlcmchlp Technology Drawmg No CD4-062C Shee| 1 or;
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 28 2016-2019 Microchip Technology Inc.
8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9mm Body [DFN] NOTE 2 Unlzs MILLIMETERS Dlmenslon lelts MN | NOM \ MAX Number ol Flns N 5 Pltch e o 65 550 Overall Helgh| A 0.80 o 90 1 co Slandolt A1 0.00 o 02 o 05 Contact Thlckness A3 0 20 REF Overall Lenglh D 3 ac ESC Exposed Pad Wldm E2 1.34 | - l 1 60 Overall Width E 3 oo asc Exposed Pad Length D2 1.50 . 2 40 Contact Wldtn e 0.25 o 30 o 35 Contact Lengtn L n 20 o 30 o 55 Contact-to—Exposed Fad K o 20 - - Notes. 1. Pm 1 visual lndex teatme may vary, but must be located wl‘hin me natened area. 2 Package may have one Dr mare exposed 11E bars at ends 3. Package ls saw singulaled 4. Dlmenslonlng and toleranCing perASME Y14.5M BSC: Basic Dlmenslorl. Theorehcally exact value shown wilhoul tolerances. REF Relerence Dimension, usually wlthout tolerance. lor infurmaticn purposes only Mlcrochlp Technology Drawlng No comoszc Sheet 2 ol 2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2019 Microchip Technology Inc. DS20005514B-page 29
MCP2542FD/4FD, MCP2542WFD/4WFD
8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9mm Body [DFN] W2 *\ \“G LELDDD‘ Ct T2 WEEDS Tm RECOMMENDED LAND PATTERN Umts M‘LUMETERS Dimenswon ants MIN \ NOM \ MAX Contact Push E u 65 530 Optlunat Center Pad Wwdth W2 2 40 Optiona‘ Center Pad Length T2 1 55 Contact Pad Spacing (:1 3.10 Contact Pad Wwdth (X5) X1 0 35 Cuntact Pad Length (x5) Y1 o 65 Distance Between Pads G 0.30 Notes. 1. Dwmensiomng and Iolerancing per ASME v14 5M BSC' Baslc Dlmenswun Themet‘cal‘y exact Vatue shown wlthuut tolerances chrocmp Tecnnology Drawmg No 004720628
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 30 2016-2019 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] o m A A2 NIX "7 j—‘SEATING PLANE A1 _ SIDE VIEW VIEW A-A Mlcrocmp Technology Drawmg No 00470570 Sheet 1 0V 2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2019 Microchip Technology Inc. DS20005514B-page 31
MCP2542FD/4FD, MCP2542WFD/4WFD
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Unlls MlLLlMETERS Dlmension lells MIN | NOM | MAX Number ol Plns N B Pllcl'l e 1.27 350 Overall Height A - - 1 75 Molded Package Thlckness A2 1 25 , , Slandu" § A1 0 10 - D 25 Overall Width E 6.00 350 Molded Package Width E1 3 90 BSC Overall Length D 4.90 BSC Chamier (Opllunal) h D 25 - D 50 Foot Length L o 40 , 1 27 Foalprim L1 1 04 REF Foot Angle w 0° , a” Lead Thlckness C D 17 , D 25 Lead Width b o 31 , u 51 Mold Drall Angle Top :1 5° , 15“ Mold Drall Angle Botlom 5 5° , 15° Mates: 1 Pln1vlsuallndexleature may vary, but must be located wl|hin lhe hatched area. 2 §Slgnificanl Characterisllc 3 DlmenSlons D and E1 do not lnclude rnald flash or protruslons Mold llash or prolmsmns shall hm exceed 015mm per Slde 4 Dlmenslonlng and loleranclng per ASME v14 5M BSC Baslc Dlmension. Theoretically exact value shown wllhoul tolerances. REF Relerenee Dlmenslon‘ usually wllhoul lalerance‘ tor .nlorrnahan purpuses unly Mlcrochip Technology Drawmg No. c047057c Sheet 2 ol 2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 32 2016-2019 Microchip Technology Inc.
Nales DUE ULJ / SILK SCREEN LJ DUE: Y1 «X1 RECOMMENDED LAND PATTERN Umts M‘LLIMETERS mmensmn mewls MN | NCM | MAX Contact Pwtch E 1 27 BSC Comacl Fad Spacmg C 5 4D Contad Pad Widlh (xx) x1 0.50 Contad Pad Length (x3) Y1 1.55 1 Dwmenswoning and tolerancmg per ASME v14 5M ESC Eas‘c D‘mensmn Theorehcal‘y exact Va‘ue shown wllhout to‘erances Microchip Techno‘ogy Drawmg Na C0472057A
 !"#$%
& !"#$%&"'""($)%
*++&&&!!+$
2016-2019 Microchip Technology Inc. DS20005514B-page 33
MCP2542FD/4FD, MCP2542WFD/4WFD
8-Lead Plastic Dual Flat, No Lead Package (MN) — 2x3x0.75mm Body [TDFN] NOTE1 { 2x Q 0.15 c X E- 0 TOP VIEW // 0.10 c ‘ A SEAT‘NG PLANE u“ f A3, SIDE VIEW [)2 EXPOSED J m: BXb $ BOTTOM VIEW Microchip Technology Drawmg No. (204-1290 SheeH 0f2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 34 2016-2019 Microchip Technology Inc.
8-Lead Plastic Dual Flat, No Lead Package (MN) — 2x3x0.75mm Body [TDFN] NOTE 2 Units MILLIMETERS Dimension Limits MIN l NOM l MAX Number of Pins N 8 Pitch e 0.50 1330 Overall Heighl A 0.70 0 75 0 BO Standoff A1 0.00 0 02 0 05 Conlact Thickness A3 0 20 REF Overall Lenglh D 2.00 BSC Overall Width E 3.00 BSC Exposed Pad Length D2 1 20 - 1 60 Exposed Pad Width E2 1 20 - 1 60 Conlact Widlh b 0.20 0 25 0 30 Conlact Lenglh L 0.25 0 30 0 45 ConlacHwExpused Pad K 0.20 , , Notes: 1. Pin 1 Visual index fealure may vary, but musl be leased Wlii’lln the hatched area 2. Package may have one or more expused lie bars al ends. 3. Package is saw singuiated 4 Dimensioning and toierancing per ASME Y‘i4 5M ESC Basic Dlmenslnn. Thenreilcally exacl Value shown wlihoul tolerances REF Reierence Dimension. usually wllhoul loierance. ior informalion purposes only Microchip Technology Drawing No. C047129C Sheel 2 of 2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2019 Microchip Technology Inc. DS20005514B-page 35
MCP2542FD/4FD, MCP2542WFD/4WFD
Notes. W2 W6“ }DD C1 *EDDD .14? S‘LK SCREEN Y RECOMMENDED LAND PATTERN Umls M‘LLIMETERS Dtmenstan L‘m‘ls MIN | NCAA | MAX Cunlact Pttcn E 0.50 580 omianat Center Pad Width W2 1.45 Optionat Center Pad Length T2 1.36 Contact Pad Spacing (:1 3.00 Contact Pad with (x3) x1 0 30 Cunlact Pad Length (x3) W 0.75 Dtstance Between Pads :3 0.20 1. Dimensmmng and Iolerancing per ASME Y14.5M BSC: Basic Dtmension. Theoreuca‘ly exact value shown witnout tolerances. Mtcmcm p Technotogy Drawtng N0 00411ng
'()*+,--./ !"0'(%
& !"#$%&"'""($)%
*++&&&!!+$
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 36 2016-2019 Microchip Technology Inc.
2016-2019 Microchip Technology Inc. DS20005514B-page 37
MCP2542FD/4FD, MCP2542WFD/4WFD
NOTES:
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 38 2016-2019 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision B (March 2019)
Changed High-Level Input Voltage for
MCP2544FD and MCP2544WFD from VIO-0.3 to
VDD-0.3 in TABLE 2-1: “DC Characteristics”.
Fixed SOIC package markings in Section 4.1
“Package Marking Information”.
Clarified that MCP2544FD/4FD is a CAN FD
Transceiver without WUP Option in Section
“Product Identification System”.
Minor typographical corrections.
Revision A (February 2016)
Initial release of this document.
PART No. L)? 41x v
2016-2019 Microchip Technology Inc. DS20005514B-page 39
MCP2542FD/4FD, MCP2542WFD/4WFD
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP2542FD-E/MF: Extended Tempera-
ture, 8-lead, Plastic
Dual Flat No Lead
DFN package.
b) MCP2544WFD-H/MF:High Temperature,
8-lead, Plastic Dual
Flat No Lead DFN
package.
c) MCP2542WFDT-H/SN:Tape and Reel, High
Temperature,
8-lead, Plastic Small
Outline SOIC pack-
age.
d) MCP2544WFDT-E/SN:Tape and Reel,
Extended Tempera-
ture, 8-lead, Plastic
Small Outline SOIC
package.
e) MCP2542FDT-E/MNY:Tape and Reel,
Extended Tempera-
ture, 8-lead, Plastic
Dual Flat No Lead
TDFN package.
f) MCP2544WFDT-H/MNY:Tape and Reel,
High Temperature,
8-lead, Plastic Dual
Flat No Lead TDFN
package.
Note1: Tape and Reel identifier only appears
in the catalog part number description.
This identifier is used for ordering
purposes and is not printed on the
device package. Check with your
Microchip Sales Office for package
availability with the Tape and Reel
option.
[X](1)
Tape and Reel
Option
Device: MCP2542FD/4FD: CAN FD Transceiver
without WUP Option
MCP2542WFD/4WFD: CAN FD Transceiver with
WUP Option
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range:
E= -40C to+125C (Extended)
H= -40C to +150°C (High)
Package: MF = Plastic Dual Flat No Lead Package -
3x3x0.9 mm Body (DFN), 8-lead
MNY = Plastic Dual Flat No Lead Package -
2x3x0.75 mm Body (TDFN), 8-lead
SN = Plastic Small Outline (SN) - Narrow,
3.90 mm, Body (SOIC), 8-lead
MCP2542FD/4FD, MCP2542WFD/4WFD
DS20005514B-page 40 2016-2019 Microchip Technology Inc.
NOTES:
YSTEM
2016-2019 Microchip Technology Inc. DS20005514B-page 41
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4308-7
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
6‘ ‘MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS20005514B-page 42 2016-2019 Microchip Technology Inc.
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08/15/18

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IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8TDFN
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8SOIC
IC TRANSCEIVER 1/1 8DFN
IC TRANSCEIVER 1/1 8DFN
IC TRANSCEIVER 1/1 8TDFN
IC TRANSCEIVER 1/1 8DFN
IC TRANSCEIVER 1/1 8TDFN
IC TRANSCEIVER 1/1 8DFN