ADP5075 Datasheet by Analog Devices Inc.

View All Related Products | Download PDF Datasheet
ANALOG DEVICES 800 mA, DB-to-DB Inverting Regulator ADP5075 Documenl Feedback
800 mA, DC-to-DC Inverting Regulator
Data Sheet
ADP5075
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©20152017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Wide input voltage range: 2.85 V to 15 V
Adjustable negative output to VIN39 V
Integrated 800 mA main switch
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Precision enable control
UVLO, OCP, OVP, and TSD protection
1.61 mm × 2.18 mm, 12-ball WLCSP
−40°C to +125°C junction temperature range
Supported by the ADIsimPower tool set
APPLICATIONS
Bipolar amplifiers, analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and multiplexers
Charge coupled device (CCD) bias supplies
Optical module supplies
Radio frequency (RF) power amplifier (PA) bias
TYPICAL APPLICATION CIRCUIT
ADP5075
R
C
C
C
COMP
C
VREG
VREG
SS
EN
GND
AVIN
PVIN
C
IN
V
IN
L1
SLEW
SYNC/FREQ
FB
SW
VREF
D1
R
FB
R
FT
V
OUT
C
VREF
C
OUT
12819-001
ON
OFF
Figure 1.
GENERAL DESCRIPTION
The ADP5075 is a high performance dc-to-dc inverting regulator
used to generate negative supply rails.
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch enables the generation of
an adjustable negative output voltage down to 39 V below the input
voltage.
The ADP5075 operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The ADP5075 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. The regulator implements
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
The ADP5075 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, the regulator completely disconnects the load from the
input supply to provide a true shutdown.
Other key safety features in the ADP5075 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5075 is available in a 12-ball WLCSP and is rated for a
−40°C to +125°C junction temperature range.
Table 1. Related Devices
Device
Boost
Switch (A)
Inverter
Switch (A) Package
ADP5070 1.0 0.6 20-lead LFCSP (4 mm ×
4 mm) and 20-lead TSSOP
ADP5071
2.0
1.2
4 mm) and 20-lead TSSOP
ADP5075 Not
applicable
0.8 12-ball WLCSP
(1.61 mm × 2.18 mm)
ADP5075 Data Sheet
Rev. B | Page 2 of 19
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
PWM Mode ................................................................................. 11
PSM Mode ................................................................................... 11
Undervoltage Lockout (UVLO) ............................................... 11
Oscillator and Synchronization ................................................ 11
Internal Regulators ..................................................................... 11
Precision Enabling...................................................................... 11
Soft Start ...................................................................................... 12
Slew Rate Control ....................................................................... 12
Current-Limit Protection ............................................................ 12
Overvoltage Protection .............................................................. 12
Thermal Shutdown .................................................................... 12
Applications Information .............................................................. 13
ADIsimPower Design Tool ....................................................... 13
Component Selection ................................................................ 13
Common Applications .............................................................. 16
Layout Considerations ............................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
9/2017Rev. A to Rev. B
Changes to Table 9 .......................................................................... 17
8/2015Rev. 0 to Rev. A
Changes to General Description Section and Figure 1 ............... 1
Change to Figure 23 ....................................................................... 11
7/2015Revision 0: Initial Version
Table 2‘
Data Sheet ADP5075
Rev. B | Page 3 of 19
SPECIFICATIONS
PVIN = AVIN = 2.85 V to 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA =
25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
V
IN
2.85
15
V
PVIN, AVIN
QUIESCENT CURRENT
Operating Quiescent Current
PVIN, AVIN (Total) IQ 1.8 4.0 mA No switching, EN = high, PVIN = AVIN =
5 V
Shutdown Current ISHDN 5 10 µA No switching, EN = low, PVIN = AVIN = 5 V
UVLO
System UVLO Threshold AVIN
Rising VUVLO_RISING 2.8 2.85 V
Falling VUVLO_FALLING 2.5 2.55 V
Hysteresis VHYS 0.25 V
OSCILLATOR CIRCUIT
Switching Frequency fSW 1.130 1.200 1.270 MHz SYNC/FREQ = low
2.240 2.400 2.560 MHz SYNC/FREQ = high (connect to VREG)
SYNC/FREQ Input
Input Clock Range fSYNC 1.000 2.600 MHz
Input Clock Minimum On Pulse Width tSYNC_MIN_ON 100 ns
Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns
Input Clock High Logic VH (SYNC) 1.3 V
Input Clock Low Logic VL (SYNC) 0.4 V
PRECISION ENABLING (EN)
High Level Threshold VTH_H 1.125 1.15 1.175 V
Low Level Threshold
V
TH_L
1.025
1.05
1.075
V
Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to achieve ISHDN
Pull-Down Resistance REN 1.48 MΩ
INTERNAL REGULATOR
VREG Output Voltage VREG 4.25 V
INVERTING REGULATOR
Reference Voltage
V
REF
1.60
V
Accuracy 0.5 +0.5 % TJ = 25°C
1.5 +1.5 % TJ = −40°C to +125°C
Feedback Voltage VREFVFB 0.8 V
Accuracy 0.5 +0.5 % TJ = 25°C
1.5
+1.5
%
T
J
= −40°C to +125°C
Feedback Bias Current IFB 0.1 µA
Overvoltage Protection Threshold VOV 0.74 V At the FB pin after soft start is complete
Load Regulation (VREF − VFB)/
ILOAD
0.0004 %/mA ILOAD = 5 mA to 75 mA
Line Regulation (VREF − VFB)/
VPVIN
0.003 %/V VPVIN = 2.85 V to 14.5 V, ILOAD = 15 mA
EA Transconductance gM 270 300 330 µA/V
Power FET On Resistance RDS (ON) 330 mΩ
Power FET Maximum Drain Source Voltage VDS (MAX) 39 V
Current-Limit Threshold ILIM 800 880 960 mA
Minimum On Time 60 ns
Minimum Off Time 50 ns
ADP5075 Data Sheet
Rev. B | Page 4 of 19
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SOFT START
Soft Start Timer tSS 4 ms SS = open
32 ms SS resistor = 50 kto GND
Hiccup Time tHICCUP 8 × tSS ms
THERMAL SHUTDOWN
Threshold TSHDN 150 °C
Hysteresis THYS 15 °C
ESD CAUTION A m ESD (elenros‘alic discharge) sensi‘ive device. Chavged dewces and ("cum boavds can dlsCharge wmmm detection Although m mam mum paxemed m pvoprielavy pmemon wmmy, damage may occuv on devlces subjeded w hlgh enevgy ESD Therefme, proper ESD precaunon: should be (aken m avoxd pevvmmame degradavon m ‘05: o! mnmonamy
Data Sheet ADP5075
Rev. B | Page 5 of 19
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
PVIN, AVIN 0.3 V to +18 V
SW PVIN40 V to PVIN + 0.3 V
GND 0.3 V to +0.3 V
VREG 0.3 V to lower of AVIN + 0.3 V or +6 V
EN, FB, SYNC/FREQ 0.3 V to +6 V
COMP, SLEW, SS, VREF 0.3 V to VREG + 0.3 V
Operating Junction
Temperature Range
40°C to +125°C
Storage Temperature
Range
65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is based on a 4-layer printed circuit board (PCB) (two
signals and two power planes) as recommended in the Layout
Considerations section. θJC is measured at the top of the
package and is independent of the PCB.
Table 4. Thermal Resistance
Package Type θJA θJC Unit
12-Ball WLCSP
68.3
1.2
°C/W
ESD CAUTION
ADP5075 Data Sheet
Rev. B | Page 6 of 19
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
12819-002
1
AVIN PVIN SW
VREG SLEW SS
GND SYNC/FREQ EN
VREF FB COMP
A
B
C
D
23
BALL A1
INDICATOR
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No. Mnemonic Description
A1 AVIN System Power Supply for the ADP5075.
A2 PVIN Power Input for the Inverting Regulator.
A3 SW Switching Node for the Inverting Regulator.
B1 VREG Internal Regulator Output. Connect a 1.0 μF ceramic filter capacitor between the VREG pin and GND.
B2 SLEW Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the FET driving the SW pin. For the fastest slew
rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For the slowest
slew rate (best noise performance), connect the SLEW pin to ground.
B3 SS Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start
time, connect a resistor between the SS pin and GND.
C1 GND Ground.
C2 SYNC/FREQ
Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high. To
set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency,
connect the SYNC/FREQ pin to an external clock.
C3 EN Inverting Regulator Precision Enable. The EN pin is compared to an internal precision reference to enable the
inverting regulator output.
D1 VREF Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and ground.
D2 FB Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting
regulator output capacitor and VREF to program the output voltage.
D3 COMP Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and GND.
«no BEBE“ .6565“ .3565“ m is 59.55 5.59 2:23: 3.5 5928 2:59 2:232 .3565“
Data Sheet ADP5075
Rev. B | Page 7 of 19
TYPICAL PERFORMANCE CHARACTERISTICS
Typical performance characteristics are generated using the standard bill of materials for each input/output combination listed in Table 9.
0
50
100
150
200
250
300
350
400
450
500
–40 –35 –30 –25 –20 –15 –10 –5 0
MAXIMUM OUTPUT CURRENT (mA)
V
OUT
(V)
V
IN
= 3.3V, L = 6.H, DIODE = DFLS240L
V
IN
= 3.3V, L = 10µH, DIODE = DFLS240
V
IN
= 5.0V, L = 10µH,DIODE = DFLS240
V
IN
= 5.0V, L = 15µH, DIODE = DFLS240
V
IN
= 12.0V, L = 15µH, DIODE = DFLS240L
V
IN
= 12.0V, L = 22µH, DIODE =DFLS240
V
IN
= 15.0V, L = 22µH, DIODE = DFLS240L
V
IN
= 15.0V, L = 22µH,DIODE = DFLS240
12819-003
Figure 3. Maximum Output Current, fSW = 1.2 MHz, TA = 25°C, Based on
Target of 70% ILIM
0
50
100
150
200
250
300
350
400
450
500
–40 –35 –30 –25 –20 –15 –10 –5 0
MAXIMUM OUTPUT CURRENT (mA)
VOUT (V)
12819-004
VIN = 3.3V, L = 3.H, DIODE = DFLS240L
VIN = 3.3V, L = 5.6µH, DIODE = DFLS240
VIN = 5.0V, L = 4.7µH, DIODE = DFLS240L
VIN = 5.0V, L = 6.8µH, DIODE = DFLS240
VIN = 12.0V, L = 8.2µH, DIODE = DFLS240L
VIN = 12.0V, L = 15.0µH, DIODE = DFLS240
VIN = 15.0V, L = 10.0µH, DIODE = DFLS240L
VIN = 15.0V, L = 15.0µH, DIODE = DFLS240
Figure 4. Maximum Output Current, fSW = 2.4 MHz, TA = 25°C, Based on
Target of 70% ILIM
0
10
20
30
40
50
60
70
80
90
0.001 0.01 0.1 1
EFFICIENCY (%)
CURRENT LOAD (A)
1.2MHz
2.4MHz
12819-005
Figure 5. Efficiency vs. Current Load, VIN = 3.3 V, VNEG = −3.3 V, TA = 25°C
0
10
20
30
40
50
60
70
80
90
0.001 0.01 0.1 1
EFFICIENCY (%)
CURRENT LOAD (A)
12819-006
VIN = 3.3V, 1.2MHz
VIN = 3.3V, 2.4MHz
VIN = 12.0V, 1.2MHz
VIN = 12.3V, 2.4MHz
Figure 6. Efficiency vs. Current Load, VNEG = −5 V, TA = 25°C
0
10
20
30
40
50
60
70
80
100
90
0.001 0.01 0.1 1
EFFICIENCY (%)
CURRENT LOAD (A)
12819-007
1.2MHz
2.4MHz
Figure 7. Efficiency vs. Current Load, VIN = 12 V, VNEG = −15 V, TA = 25°C
0
10
20
30
40
50
60
70
80
0.001 0.01 0.1
EFFICIENCY (%)
CURRENT LOAD (A)
12819-008
1.2MHz
2.4M
Hz
Figure 8. Efficiency vs. Current Load, VIN = 5 V, VNEG = −30 V, TA = 25°C
>1 >_ “352 58: 222.5; 656E“ «.93 E :5: .5559 553:2. Banach 2.55 3.5. 55:55 55353 om >1 3 35b? 59: 20:55;
ADP5075 Data Sheet
Rev. B | Page 8 of 19
12819-009
0
10
20
30
40
50
60
70
90
80
0.001 0.01 0.1
EFFICIENCY (%)
CURRENT LOAD (A)
1.2MHz
2.4MHz
Figure 9. Efficiency vs. Current Load, VIN = 5 V, VNEG = −34 V, TA = 25°C
0
10
20
30
40
50
60
70
80
90
0.001 0.01 0.1 1
EFFICIENCY (%)
CURRENT LOAD (A)
–40°C
+25°C
+125°C
12819-010
Figure 10. Efficiency vs. Current Load for Various Temperatures, VIN = 5 V,
VNEG = −15 V, fSW = 1.2 MHz
–0.50
–0.30
–0.10
0.10
0.30
0.50
0246810 12 14 16
VARIATION FROM AVERAGE (V
REF
– V
FB
) (%)
V
IN
(V)
12819-011
Figure 11. Line Regulation, VNEG = −5 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C
–0.50
–0.30
–0.10
0.10
0.30
0.50
VARIATION FROM AVERAGE (V
REF
– V
FB
) (%)
OUTPUT CURRENT (A)
12819-012
00.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Figure 12. Load Regulation, VIN = 12 V, VNEG = −5 V, fSW = 1.2 MHz, TA = 25°C
0.80
0.82
0.84
0.86
0.88
0.90
0.92
0.94
0.96
0 2 4 6 8 10 12 1614
INDUCTOR CURRENT LIMIT (A)
V
IN
(V)
–40°C
+25°C
+125°C
12819-013
Figure 13. Inductor Current Limit (ILIMIT) vs. Input Voltage (VIN) for Various
Temperatures
04812 162 6 10 14
OSCILLATOR FREQUENCY (MHz)
V
IN
(V)
T
A
= –40°C
T
A
= +25°C
T
A
= +125°C
12819-014
2.24
2.29
2.34
2.39
2.44
2.49
2.54
Figure 14. Oscillator Frequency vs. Input Voltage (VIN) for Various
Temperatures, SYNC/FREQ Pin = High
1.27 3.... 55:85 x3553 cm I // / 14 .42 Eummzu 53350 23856 is Euxxau CHZJ'
Data Sheet ADP5075
Rev. B | Page 9 of 19
04812 162 6 10 14
OSCILLATOR FREQUENCY (MHz)
V
IN
(V)
T
A
= –40°C
T
A
= +25°C
T
A
= +125°C
1.13
1.27
1.25
1.23
1.21
1.19
1.17
1.15
12819-015
Figure 15. Oscillator Frequency vs. Input Voltage (VIN) for Various
Temperatures, SYNC/FREQ Pin = Low
04812 162 6 10 14
SHUTDOWN QUIESCENT CURRENT (µA)
V
IN
(V)
T
A
= –40°C
T
A
= +25°C
T
A
= +125°C
0
2
4
6
8
10
12
14
12819-016
Figure 16. Shutdown Quiescent Current vs. Input Voltage (VIN) for Various
Temperatures, EN Pin Below Shutdown Threshold
0
0.5
1.0
1.5
2.0
2.5
0 2 4 6 8 10 12 14 16
CURRENT (mA)
V
IN
(V)
–40°C
+25°C
+125°C
12819-017
Figure 17. Operating Quiescent Current vs. Input Voltage (VIN) for Various
Temperatures, EN Pin On
CH1 1.00V
BW
CH1 1.00V
BW
V
OUT
CH2 10.0mV
BW
CH3 100mV
BW
4.00ms CH1 5.06V
1
3
2
T 12.4800ms
12819-018
V
IN
V
FB
Figure 18. Line Transient Showing VIN, VOUT, and VFB, VIN = 4.5 V to 5.5 V Step,
VNEG = −12 V, RLOAD = 300 , fSW = 1.2 MHz, TA = 25°C
CH2 10.0mV
BW
CH3 50.0mV
BW
CH4 10.0mA
BW
4.00ms CH4 41.2mA
4
3
2
T 11.9600ms
12819-019
V
OUT
I
LOAD
V
FB
Figure 19. Load Transient Showing ILOAD, VOUT, and VFB, VIN = 5 V, VNEG = −12 V,
ILOAD = 35 mA to 45 mA Step, fSW = 1.2 MHz, TA = 25°C
CH2 5.00V
BW
CH3 20.0mV
BW
CH4 50.0mA
BW
4.00µs CH2 3.10V
4
3
2
T 401.600µs
12819-020
SW
I
INDUCTOR
V
NEG
Figure 20. Skip Mode Operation Showing Inductor Current (IINDUCTOR), Switch
Node Voltage, and Output Ripple, VIN = 5 V, VNEG = −5 V, ILOAD = 0.5 mA,
fSW = 1.2 MHz, TA = 25°C
m cm] x cm]
ADP5075 Data Sheet
Rev. B | Page 10 of 19
CH2 5.00V
BW
CH3 20.0mV
BW
CH4 50.0mA
BW
200ns CH2 3.10V
4
3
2
T 0.00000s
12819-021
SW
I
INDUCTOR
V
NEG
Figure 21. Discontinuous Conduction Mode Operation Showing Inductor
Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V,
VNEG = −5 V, ILOAD = 10 mA, fSW = 1.2 MHz, TA = 25°C
CH2 5.00V
BW
CH3 20.0mV
BW
CH4 50.0mA
BW
200ns CH2 2.10V
4
3
2
T 0.00000s
12819-022
SW
I
INDUCTOR
V
NEG
Figure 22. Continuous Conduction Mode Operation Showing Inductor
Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V,
VNEG = 5 V, ILOAD = 50 mA, fSW = 1.2 MHz, TA = 25°C
Table 6‘ SYNC/FREQ Pin Options
Data Sheet ADP5075
Rev. B | Page 11 of 19
THEORY OF OPERATION
VIN
C
IN
HV
BAND GAP SW
FB
INVERTER
PWM CONTROL
PVIN
ERROR AMP
HV
REGULATOR
EN
AVIN VREG
C
VREG
COMP
SLEW
SYNC/FREQ
SS GND
CURRENT
SENSE
START-UP
TIMERS
PLL
4µA
REF
CONTROL
OSCILLATOR
SLEW
INVERTER_ENABLE
EN
R
FB
R
FT
L1
D1
C
OUT
R
SS
(OPTIONAL)
THERMAL
SHUTDOWN
UVLO
OVP
VREF
VREG
FB
REFERENCE
GENERATOR REF_1.6V
REF_1.6V
REF
C
VREF
R
C
C
C
12819-023
Figure 23. Functional Block Diagram
PWM MODE
The inverting regulator in the ADP5075 operates at a fixed fre-
quency set by an internal oscillator. At the start of each oscillator
cycle, the MOSFET switch turns on, applying a positive voltage
across the inductor. The inductor current (IINDUCTOR) increases
until the current sense signal crosses the peak inductor current
threshold that turns off the MOSFET switch; this threshold is set
by the error amplifier output. During the MOSFET off time, the
inductor current declines through the external diode until the next
oscillator clock pulse starts a new cycle. The ADP5075 regulates the
output voltage by adjusting the peak inductor current threshold.
PSM MODE
During light load operation, the regulators can skip pulses to
maintain output voltage regulation. Skipping pulses increases
the device efficiency.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout circuitry monitors the AVIN pin voltage
level. If the input voltage drops below the VUVLO_FALLING threshold,
the regulator turns off. After the AVIN pin voltage rises above
the VUVLO_RISING threshold, the soft start period initiates, and the
regulator is enabled.
OSCILLATOR AND SYNCHRONIZATION
A phase-locked loop (PLL)-based oscillator generates the internal
clock and offers a choice of two internally generated frequency
options or external clock synchronization. The switching frequency
is configured using the SYNC/FREQ pin options shown in Table 6.
For external synchronization, connect the SYNC/FREQ pin to a
suitable clock source. The PLL locks to an input clock within
the range specified by fSYNC.
Table 6. SYNC/FREQ Pin Options
SYNC/FREQ Pin Switching Frequency
High 2.4 MHz
Low 1.2 MHz
External Clock 1× clock frequency
INTERNAL REGULATORS
The internal VREG regulator in the ADP5075 provides a stable
power supply for the internal circuitry. The VREG supply provides
a high signal for device configuration pins but must not be used
to supply external circuitry.
The VREF regulator provides a reference voltage for the inverting
regulator feedback network to ensure a positive feedback voltage
on the FB pin.
A current-limit circuit is included for both internal regulators to
protect the circuit from accidental loading.
PRECISION ENABLING
The ADP5075 has an enable pin that features a precision enable
circuit with an accurate reference voltage. This reference allows the
ADP5075 to be sequenced easily from other supplies. It can also
be used as a programmable UVLO input by using a resistor divider.
The enable pin has an internal pull-down resistor that defaults
to off when the pin is floating.
When the voltage at the enable pin is greater than the VTH_H
reference level, the regulator is enabled.
ADP5075 Data Sheet
Rev. B | Page 12 of 19
SOFT START
The regulator in the ADP5075 includes soft start circuitry that
ramps the output voltage in a controlled manner during startup,
thereby limiting the inrush current. The soft start time is internally
set to the fastest rate when the SS pin is open.
Connecting a resistor between SS and ground allows the
adjustment of the soft start delay.
SLEW RATE CONTROL
The ADP5075 uses programmable output driver slew rate control
circuitry. This circuitry reduces the slew rate of the switching
node as shown in Figure 24, resulting in reduced ringing and
lower EMI. To program the slew rate, connect the SLEW pin to
the VREG pin for normal mode, to the GND pin for slow mode,
or leave it open for fast mode. This configuration allows the use of
an open-drain output from a noise sensitive device to switch the
slew rate from fast to slow, for example, during ADC sampling.
Note that slew rate control causes a trade-off between efficiency
and low EMI.
FASTEST
SLOWEST
12819-024
Figure 24. Switching Node at Various Slew Rate Settings
CURRENT-LIMIT PROTECTION
The inverting regulator in the ADP5075 includes current-limit
protection circuitry to limit the amount of forward current
through the MOSFET switch.
When the peak inductor current exceeds the overcurrent limit
threshold for a number of clock cycles during an overload or
short-circuit condition, the regulator enters hiccup mode. The
regulator stops switching and then restarts with a new soft start
cycle after tHICCUP and repeats until the overcurrent condition is
removed.
OVERVOLTAGE PROTECTION
An overvoltage protection mechanism is present on the FB pin
for the inverting regulator.
When the voltage on the FB pin drops below the VOV threshold,
the switching stops until the voltage rises above the threshold.
This functionality is enabled after the soft start period has elapsed.
THERMAL SHUTDOWN
In the event that the ADP5075 junction temperature rises above
TSHDN, the thermal shutdown circuit turns off the IC. Extreme
junction temperatures can be the result of prolonged high current
operation, poor circuit board design, and/or high ambient
temperature. Hysteresis is included so that when thermal shutdown
occurs, the ADP5075 does not return to operation until the on-
chip temperature drops below TSHDN minus THYS. When resuming
from thermal shutdown, a soft start is performed.
Table 7‘ Recommended Feedback Resistor Values
Data Sheet ADP5075
Rev. B | Page 13 of 19
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
The ADP5075 is supported by the ADIsimPowerdesign tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized to a specific design goal. These tools
allow the user to generate a full schematic, bill of materials, and
calculate performance in minutes. ADIsimPower can optimize
designs for cost, area, efficiency, and device count while taking
into consideration the operating conditions and limitations of
the IC and all real external components. The ADIsimPower tool
can be found at www.analog.com/adisimpower, and the user
can request an unpopulated board through the tool.
COMPONENT SELECTION
Feedback Resistors
The ADP5075 provides an adjustable output voltage. An external
resistor divider sets the output voltage, where the divider output
must equal the feedback reference voltage, VFB. To limit the output
voltage accuracy degradation due to feedback bias current, ensure
that the current through the divider is at least 10 × IFB.
Set the negative output for the inverting regulator by
( )
FBREF
FB
FT
FB
NEG
VV
R
R
VV =
where:
VNEG is the negative output voltage.
VFB is the FB reference voltage.
RFT is the feedback resistor from VNEG to FB.
RFB is the feedback resistor from FB to VREF.
VREF is the VREF pin reference voltage.
Table 7 shows recommended values for common output
voltages using standard resistor values.
Table 7. Recommended Feedback Resistor Values
Desired Output
Voltage (V) RFT (MΩ) RFB (kΩ)
Actual Output
Voltage (V)
1.8 0.332 102 −1.804
−3 0.475 100 −3.000
3.3 0.523 102 −3.302
4.2 0.715 115 −4.174
−5 1.15 158 −5.023
−9 1.62 133 −8.944
12 1.15 71.5 −12.067
13
2.8
162
−13.027
15 2.32 118 −14.929
18 2.67 113 −18.103
20 2.94 113 −20.014
24 3.16 102 −23.984
30 4.12 107 −30.004
35 5.11 115 −34.748
Output Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
the output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage rating
of 25 V or 50 V (depending on output) are recommended for
best performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
Calculate the worst case capacitance accounting for capacitor
variation over temperature, component tolerance, and voltage
using the following equation:
CEFFECTIVE = CNOMINAL × (1 TEMPCO) × (1 DCBIASCO) ×
(1 Tolerance)
where:
CEFFECTIVE is the effective capacitance at the operating voltage.
CNOMINAL is the nominal data sheet capacitance.
TEMPCO is the worst case capacitor temperature coefficient.
DCBIASCO is the dc bias derating at the output voltage.
Tolerance is the worst case component tolerance.
To guarantee the performance of the device, it is imperative that
the effects of dc bias, temperature, and tolerances on the behavior
of the capacitors be evaluated for each application.
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
Note that the use of large output capacitors may require a
slower soft start to prevent current limit during startup. A 10 µF
capacitor is suggested as a good balance between performance
and size.
Input Capacitor
Higher value input capacitors help reduce the input voltage
ripple and improve transient response.
To minimize supply noise, place the input capacitor as close as
possible to the AVIN and PVIN pins. A low ESR capacitor is
recommended.
The effective capacitance needed for stability is a minimum
of 10 µ F. If the power pins are individually decoupled, it is
recommended to use an effective minimum of a 5.6 µF capacitor
on the PVIN pin and a 3.3 µF capacitor on the AVIN pin. The
minimum values specified exclude dc bias, temperature, and
tolerance effects that are application dependent and must be taken
into consideration.
Duty son SYARr J n V X! L] v xr x(erut)/)
ADP5075 Data Sheet
Rev. B | Page 14 of 19
VREG Capacitor
A 1.0 µF ceramic capacitor (CVREG) is required between the
VREG pin and GND.
VREF Capacitor
A 1.0 µF ceramic capacitor (CVREF) is required between the
VREF pin and GND.
Soft Start Resistor
A resistor can be connected between the SS pin and the GND pin
to increase the soft start time. The soft start time can be set
using this resistor between 4 ms (268 kΩ) and 32 ms (50 k).
Leaving the SS pin open selects the fastest time of 4 ms. Figure 25
shows the behavior of this operation. Calculate the soft start time
using the following formula:
tSS = 38.4 × 10−31.28 × 10−7 × RSS ()
where 50 kΩ ≤ RSS ≤ 268 kΩ.
SS PIN OPEN
SOFT START
TIMER
SOFT START
RESISTOR
R1R2
32ms
4ms
12819-025
Figure 25. Soft Start Behavior
Diodes
A Schottky diode with low junction capacitance is recommended
for D1. At higher output voltages and especially at higher switching
frequencies, the junction capacitance is a significant contributor to
efficiency. Higher capacitance diodes also generate more switching
noise. As a guide, a diode with less than 40 pF junction capacitance
is preferred when the output voltage is greater than 5 V.
Inductor Selection
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 µH to 22 µH are recommended. In
general, lower inductance values have higher saturation current
and lower series resistance for a given physical size. However,
lower inductance results in a higher peak current that can lead
to reduced efficiency and greater input and/or output ripple and
noise. A peak-to-peak inductor ripple current close to 30% of
the maximum dc current in the inductor typically yields an
optimal compromise.
For the smallest solution size, inductors with a saturation
current below ILIM may be used when the output current in the
application is such that the inductor current stays below the
saturated region.
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VNEG) voltages
determine the switch duty cycle (Duty) by the following equation:
++
+
=
DIODENEG
IN
DIODENEG
VVV
VV
Duty ||
||
where VDIODE is the forward voltage drop of the Schottky diode
(D1).
The dc current in the inductor in CCM (IL1) can be determined
using the following equation:
)
1( Duty
I
I
OUT
L1
=
Using the duty cycle (Duty) and switching frequency (fSW),
determine the on time (tON) using the following equation:
SW
ON
f
Duty
t=
The inductor ripple current (IL1) in steady state is calculated by
L1
tV
I
ON
IN
L1
×
=
Solve for the inductance value (L1) using the following equation:
L1
ON
IN
I
tV
L1
×
=
Assuming an inductor ripple current of 30% of the maximum
dc current in the inductor results in
OUT
ON
IN
I
DutytV
L1 ×
××
=3.0
)1(
Ensure that the peak inductor current (the maximum input
current plus half the inductor ripple current) is below the rated
saturation current of the inductor. Likewise, ensure that the
maximum rated rms current of the inductor is greater than the
maximum dc input current to the regulator.
When the ADP5075 inverting regulator is operated in CCM at
duty cycles greater than 50%, slope compensation is required to
stabilize the current mode loop. For stable current mode operation,
ensure that the selected inductance is equal to or greater than
the minimum calculated inductance, LMIN, for the application
parameters in the following equation:
×=> 33.0
)1(
27.0
Duty
VLL1
INMIN
(µH)
Table 9 suggests a series of inductors to use with the ADP5075
inverting regulator.
ESR x C
Data Sheet ADP5075
Rev. B | Page 15 of 19
Loop Compensation
The ADP5075 uses external components to compensate the
regulator loop, allowing the optimization of the loop dynamics
for a given application. It is recommended to use the ADIsimPower
tool to calculate compensation components.
The inverting converter, produces an undesirable right half
plane zero in the regulation feedback loop. This feedback loop
requires compensating the regulator such that the crossover
frequency occurs well below the frequency of the right half plane
zero. The right half plane zero frequency is determined by the
following equation:
DutyL1π
Duty)(R
(RHP)f
2
LOAD
Z
××
=2
1
where:
fZ(RHP) is the right half plane zero frequency.
RLOAD is the equivalent load resistance or the output voltage
divided by the load current.
+
+
+
=
DIODENEG
IN
DIODENEG
V|
|VV
V||V
Duty
where VDIODE is the forward voltage drop of the Schottky diode
(D1).
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
The regulator loop gain is
OUT
CSCOMP
OUT
M
NEG
IN
IN
NEG
FB
VL
ZGZ||R
G
VV
V
||V
V
A
××
××
×+
×= |)|2(
where:
AVL is the regulator loop gain.
VFB is the feedback regulation voltage.
VNEG is the regulated negative output voltage.
VIN is the input voltage.
GM is the error amplifier transconductance gain.
ROUT is the output impedance of the error amplifier and is 33 MΩ.
ZCOMP is the impedance of the series RC network from COMP
to GND.
GCS is the current sense transconductance gain (the inductor
current divided by the voltage at COMP), which is internally
set by the ADP5075 and is 6.25 A/V.
ZOUT is the impedance of the load in parallel with the output
capacitor.
To determine the crossover frequency, it is important to note
that, at that frequency, the compensation impedance (ZCOMP) is
dominated by a resistor, RC, and the output impedance (ZOUT) is
dominated by the impedance of the output capacitor (COUT).
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
1
2
1
|)|2(
=
××
××
××
×+
×=
OUT
C
CSC
M
NEG
IN
IN
NEG
FB
VL
Cfπ
GR
G
VV
V
||V
V
A
where fC is the crossover frequency.
To solve for RC, use the following equation:
CS
MINFB
NEG
IN
NEG
OUT
C
C
GGVV
V(V||VCfπ
R×××
×+××××
=|)|2(2
where GCS = 6.25 A/V.
Using typical values for VFB and GM results in
IN
NEG
IN
NEG
OUT
C
C
V
VVVCf
R|)|2((||4188 ×+××××
=
For better accuracy, it is recommended to use the value of
output capacitance (COUT) that takes into account the capacitance
reduction from dc bias in the calculation for RC.
After the compensation resistor is known, set the zero formed
by CC and RC to one-fourth of the crossover frequency, or
CC
C
Rfπ
C×
×
=2
where CC is the compensation capacitor.
ERROR
AMPLIFIER
REF
g
M
FB
COMP
R
C
C
B
C
C
12819-026
Figure 26. Compensation Components
The optional capacitor, CB, is chosen to cancel the zero
introduced by the ESR of the output capacitor. For low ESR
capacitors such as ceramic chip capacitors, CB can be omitted
from the design.
Solve for CB as follows:
C
OUT
B
R
CESR
C×
=
For optimal transient performance, RC and CC may need to be
adjusted by observing the load transient response of the ADP5075.
For most applications, RC is within the range of 1 kΩ to 200 kΩ,
and CC is within the range of 1 nF to 68 nF.
Table 8‘ Recommended Common Component Selections
ADP5075 Data Sheet
Rev. B | Page 16 of 19
COMMON APPLICATIONS
Table 8 and Table 9 list a number of common component
selections for typical VIN and VNEG conditions. These have been
bench tested and provide an off the shelf solution. To optimize
components for an application, use the ADIsimPower tool set.
Figure 27 shows the schematic referenced by Table 8 and Table 9
with example component values for a +5 V input to a −15 V
output. Table 8 shows the components common to all VIN and
VNEG conditions.
Table 8. Recommended Common Component Selections
Reference Value Part Number Manufacturer
CIN 10 µF TMK316B7106KL-TD Taiyo Yuden
CVREG 1 µF GRM188R71A105KA61D Murata
C
VREF
1 µF
GRM188R71A105KA61D
Murata
ADP5075
COMP
SS
R
C
15kΩ
C
C
68nF
EN
GND
AVIN
PVIN
C
IN
10µF
ON
OFF
V
IN
+5V
L1
15µH
SW
SYNC/FREQ
FB
VREF
D1
DFLS240
R
FB
118kΩ
C
VREF
1µF
C
OUT
10µF
C
VREG
1µF
R
FT
2.32MΩ
12918-027
VREG
Figure 27. Typical +5 V Input to −15 V Output, 1.2 MHz Application
Data Sheet ADP5075
Rev. B | Page 17 of 19
Table 9. Recommended Inverting Regulator Components
VIN
(V)
VNEG
(V)
Freq.
(MHz)
L1
(μH)
L1, Manufacturer Part Number
COUT
(μF) COUT2, Murata Part
D1,
Diodes,
Inc. Part
RFT
(MΩ)
RFB
(kΩ)
CC
(nF)
RC
(kΩ)
Coilcraft®
Wurth
Electronik
3.3 −5 1.2 6.8 XAL4030-682ME_ 7443857068 10 GRM32ER71H106KA12L DFLS240L 1.15 158 47 4.7
3.3 −5 2.4 4.7 XAL4030-472ME_ 7443857047 10 GRM32ER71H106KA12L DFLS240L 1.15 158 47 6.8
3.3 −9 1.2 10 XAL4040-103ME_ N/A 10 GRM32ER71H106KA12L DFLS240 1.62 133 47 8.2
3.3 −9 2.4 4.7 XAL4030-472ME_ 74438357047 10 GRM32ER71H106KA12L DFLS240 1.62 133 47 8.2
3.3 −15 1.2 10 XAL4040-103ME_ N/A 10 GRM32ER71H106KA12L DFLS240 2.32 118 47 12
3.3 −15 2.4 4.7 XAL4030-472ME_ 74438357047 10 GRM32ER71H106KA12L DFLS240 2.32 118 47 18
3.3 −24 1.2 10 XAL4040-103ME_ N/A 10 GRM32ER71H106KA12L DFLS240 3.16 102 47 22
3.3 −24 2.4 6.8 XAL4030-682ME_ 74438357068 10 GRM32ER71H106KA12L DFLS240 3.16 102 47 33
3.3 −34 1.2 10 XAL4040-103ME_ N/A 10 GRM32ER71H106KA12L DFLS240 4.99 115 47 47
3.3 −34 2.4 10 XAL4040-103ME_ N/A 10 GRM32ER71H106KA12L DFLS240 4.99 115 47 47
5 −9 1.2 10 XAL4040-103ME_ N/A 10 GRM32ER71H106KA12L DFLS240 1.62 133 47 8.2
5 −9 2.4 6.8 XAL4030-682ME_ 7448357068 10 GRM32ER71H106KA12L DFLS240 1.62 133 47 8.2
5 −15 1.2 15 XAL4040-153ME_ N/A 10 GRM32ER71H106KA12L DFLS240 2.32 118 68 15
5 −15 2.4 6.8 XAL4030-682ME_ 7448357068 10 GRM32ER71H106KA12L DFLS240 2.32 118 47 22
5 −24 1.2 15 XAL4040-153ME_ N/A 10 GRM32ER71H106KA12L DFLS240 3.16 102 47 22
5 −24 2.4 6.8 XAL4030-682ME_ 74438357068 10 GRM32ER71H106KA12L DFLS240 3.16 102 47 22
5 −34 1.2 15 XAL4040-153ME_ N/A 10 GRM32ER71H106KA12L DFLS240 4.99 115 47 39
5 −34 2.4 10 XAL4040-103ME_ N/A 10 GRM32ER71H106KA12L DFLS240 4.99 115 47 39
1224 1.2 22 XAL5050-223ME_ N/A 10 GRM32ER71H106KA12L DFLS240 3.16 102 47 10
1224 2.4 15 XAL4040-153ME_ N/A 10 GRM32ER71H106KA12L DFLS240 3.16 102 47 10
ADP5075 Data Sheet
Rev. B | Page 18 of 19
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is particularly
important for regulators with high switching frequencies. To
achieve high efficiency, good regulation, good stability, and low
noise, a well designed PCB layout is required. Follow these
guidelines when designing PCBs:
Keep the input bypass capacitor, CIN, close to the PVIN pin
and the AVIN pin. Route each of these pins individually to
the pad of this capacitor to minimize noise coupling
between the power inputs, rather than connecting the three
pins at the device. A separate capacitor can be used on the
AVIN pin for the best noise performance.
Keep the high current paths as short as possible. These
paths include the connections between CIN, L1, D1,
COUT, and GND and their connections to the ADP5075.
Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and EMI.
Avoid routing high impedance traces near any node con-
nected to the SW pin or near inductor L1 to prevent
radiated switching noise injection.
Place the feedback resistors as close to the FB pin as possible
to prevent high frequency switching noise injection.
Route a trace to RFT directly from the COUT pad for
optimum output voltage sensing.
Place the compensation components as close as possible to
COMP. Do not share vias to the ground plane with the
feedback resistors to avoid coupling high frequency noise into
the sensitive COMP pin.
Place the CVREF and CVREG capacitors as close to the
VREG and VREF pins as possible. Ensure that short traces
are used between VREF and RFB.
L1
D1
RC
RFT
RFB
CVREG
COUT1
CIN
CVREF
CC
12819-028
Figure 28. Suggested Layout for 5 mm × 6 mm, +3.3 V Input to −5 V Output Application
(Dashed Line Is Connected on the Internal Layer of the PCB; Other Vias Connected to the Ground Plane;
SS, EN, SLEW, and SYNC/FREQ Connections Not Shown for Clarity and Are Typically Connected on an Internal Layer)
@ ng. W O W W @606 f 0000 3‘ OOOO f mommy mm; um um. All .igms "my-.d mamm “a ANALOG DEVICES www.3nalun.com
Data Sheet ADP5075
Rev. B | Page 19 of 19
OUTLINE DIMENSIONS
BOTTOM VIEW
(BALL SIDE UP)
A
B
C
D
0.660
0.600
0.540
1.65
1.61
1.57
2.22
2.18
2.14
1
2
3
0.360
0.320
0.280
0.50
BSC
BALLA1
IDENTIFIER
05-21-2014-A
SEATING
PLANE 0.270
0.240
0.210
0.390
0.360
0.330
COPLANARITY
0.04
TOP VIEW
(BALL SIDE DOWN)
END VIEW
PKG-003876
0.325
0.305
0.285
0.360
0.340
0.320
Figure 29. 12-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-12-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADP5075ACBZ-R7 −40°Cto+125°C 12-Ball Wafer Level Chip Scale Package [WLCSP] CB-12-11
ADP5075CB-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©20152017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12819-0-9/17(B)

Products related to this Datasheet

IC REG BCK BST INV 800MA 12WLCSP
EVAL BOARD FOR ADP5075
IC REG BCK BST INV 800MA 12WLCSP
IC REG BCK BST INV 800MA 12WLCSP