DS28E22 Abridged Datasheet by Maxim Integrated

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_maxim Integrated“,
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
General Description
DeepCoverM embedded security solutions cloak sensitive
data under multiple layers of advanced physical security
to provide the most secure key storage possible.
The DeepCover Secure Authenticator (DS28E22) com-
bines crypto-strong, bidirectional, secure challenge-
and-response authentication functionality with an imple-
mentation based on the FIPS 180-3-specified Secure
Hash Algorithm (SHA-256). A 2Kb user-programmable
EEPROM array provides nonvolatile storage of applica-
tion data and additional protected memory holds a read-
protected secret for SHA-256 operations and settings
for user memory control. Each device has its own guar-
anteed unique 64-bit ROM identification number (ROM
ID) that is factory programmed into the chip. This unique
ROM ID is used as a fundamental input parameter for
cryptographic operations and also serves as an elec-
tronic serial number within the application. A bidirectional
security model enables two-way authentication between
a host system and slave-embedded DS28E22. Slave-to-
host authentication is used by a host system to securely
validate that an attached or embedded DS28E22 is
authentic. Host-to-slave authentication is used to protect
DS28E22 user memory from being modified by a non-
authentic host. The SHA-256 message authentication
code (MAC), which the DS28E22 generates, is computed
from data in the user memory, an on-chip secret, a host
random challenge, and the 64-bit ROM ID. The DS28E22
communicates over the single-contact 1-WireM bus at
overdrive speed. The communication follows the 1-Wire
protocol with the ROM ID acting as node address in the
case of a multiple-device 1-Wire network.
Applications
Authentication of Network-Attached Appliances
Printer Cartridge ID/Authentication
Reference Design License Management
System Intellectual Property Protection
Sensor/Accessory Authentication and Calibration
Secure Feature Setting for Configurable Systems
Key Generation and Exchange for Cryptographic
Systems
Features
S Symmetric Key-Based Bidirectional Secure
Authentication Model Based on SHA-256
S Dedicated Hardware-Accelerated SHA Engine for
Generating SHA-256 MACs
S Strong Authentication with a High Bit Count, User-
Programmable Secret, and Input Challenge
S 2048 Bits of User EEPROM Partitioned Into 8
Pages of 256 Bits
S User-Programmable and Irreversible EEPROM
Protection Modes Including Authentication, Write
and Read Protect, and OTP/EPROM Emulation
S Unique, Factory-Programmed 64-Bit Identification
Number
S Single-Contact 1-Wire Interface Communicates
with Host at Up to 76.9kbps
S Operating Range: 3.3V ±10%, -40NC to +85NC
S Low-Power 5µA (typ) Standby
S ±8kV Human Body Model ESD Protection (typ)
S 6-Pin TDFN, 6-Lead TSOC Packages
Typical Application Circuit
219-0020; Rev 2; 12/12
Ordering Information appears at end of data sheet.
DeepCover and 1-Wire are registered trademark of Maxim Integrated Products, Inc.
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/DS28E22.related
EVALUATION KIT AVAILABLE
SDA
VCC
SCL
SLPZ IO
RP
RP = 1.1k
MAXIMUM I2C BUS CAPACITANCE 320pF
3.3V
1-Wire LINE
µC
(I2C PORT)
DS2465
DS28E22
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
2Maxim Integrated
IO Voltage Range to GND ...................................... -0.5V to 4.0V
IO Sink Current ...................................................................20mA
Operating Temperature Range ......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage VPUP (Note 2) 2.97 3.63 V
1-Wire Pullup Resistance RPUP VPUP = 3.3V Q 10% (Note 3) 300 1500 I
Input Capacitance CIO (Notes 4, 5) 1500 pF
Input Load Current ILIO pin at VPUP 5 19.5 FA
High-to-Low Switching Threshold VTL (Notes 6, 7) 0.65 x VPUP V
Input Low Voltage VIL (Notes 2, 8) 0.3 V
Low-to-High Switching Threshold VTH (Notes 6, 9) 0.75 x VPUP V
Switching Hysteresis VHY (Notes 6, 10) 0.3 V
Output Low Voltage VOL IOL = 4mA (Note 11) 0.4 V
Recovery Time tREC RPUP = 1500I (Notes 2, 12) 5Fs
Time-Slot Duration tSLOT (Notes 2, 13) 13 Fs
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time tRSTL (Note 2) 48 80 Fs
Reset High Time tRSTH (Note 14) 48 Fs
Presence-Detect Sample Time tMSP (Notes 2, 15) 8 10 Fs
IO PIN: 1-Wire WRITE
Write-Zero Low Time tW0L (Notes 2, 16) 8 16 Fs
Write-One Low Time tW1L (Notes 2, 16) 1 2 Fs
IO PIN: 1-Wire READ
Read Low Time tRL (Notes 2, 17) 1 2 - dFs
Read Sample Time tMSR (Notes 2, 17) tRL + d2Fs
EEPROM
Programming Current IPROG VPUP = 3.63V (Notes 5, 18) 1 mA
Programming Time for a 32-Bit
Segment or Page Protection tPRD Refer to the full data sheet. ms
Programming Time for the Secret tPRS ms
Write/Erase Cycling Endurance NCY TA = +85NC (Notes 21, 22) 100k —
Data Retention tDR TA = +85NC (Notes 23, 24, 25) 10 Years
ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
3Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 4: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 5: Guaranteed by design and/or characterization only; not production tested.
Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values
of VTL, VTH, and VHY.
Note 7: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 8: The voltage on IO must be less than or equal to VILMAX at all times when the master is driving IO to a logic-zero level.
Note 9: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E22 present. The power-up pres-
ence detect pulse could be outside this interval, but will be complete within 2ms after power-up.
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 17: d in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during
the programming interval or SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V.
Note 19: Refer to the full data sheet.
Note 20: Refer to the full data sheet.
Note 21: Write-cycle endurance is tested in compliance with JESD47G.
Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 23: Data retention is tested in compliance with JESD47G.
Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 25: EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended.
Note 26: Refer to the full data sheet.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SHA-256 ENGINE
Computation Current ICSHA Refer to the full data sheet. mA
Computation Time tCSHA ms
ABRIDGED DATA SHEET
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
4Maxim Integrated
Pin Configuration
Pin Description
PIN NAME FUNCTION
TSOC TDFN-EP
1 3 GND Ground Reference
2 2 IO 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
3, 4, 5, 6 1, 4, 5, 6 N.C. Not Connected
— EP
Exposed Pad (TDFN only). Solder evenly to the board’s ground plane for proper
operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for
additional information.
TOP VIEW
N.C.
IO
GND
N.C.
N.C.
N.C.
TSOC
+
5
4
6
2
3
1
DS28E22 16N.C. N.C.
25IO N.C.
34GND N.C.
TDFN
(3mm × 3mm)
TOP VIEW
DS28E22
28E22
ymrrF
+
EP
ABRIDGED DATA SHEET
maxim Integrated
DS28E22
DeepCover Secure Authenticator with
1-Wire SHA-256 and 2Kb User EEPROM
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 42
© 2012 Maxim Integrated Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Ordering Information Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Note to readers: This document is an abridged version of the full data sheet. Additional device information is available
only in the full version of the data sheet. To request the full data sheet, go to www.maximintegrated.com/DS28E22
and click on Request Full Data Sheet.
PART TEMP RANGE PIN-PACKAGE
DS28E22P+ -40°C to +85°C6 TSOC
DS28E22P+T -40°C to +85°C6 TSOC (4k pcs)
DS28E22Q+T -40°C to +85°C6 TDFN-EP* (2.5k pcs)
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
6 TSOC D6+1 21-0382 90-0321
6 TDFN-EP T633+2 21-0137 90-0058
ABRIDGED DATA SHEET

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