BD9D321EFJ Datasheet by Rohm Semiconductor

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I Constant On-time Control I SLLMTM (Simple Light Load Mode) Control Over Current Protection I Short Circuit Protection I I Thermal Shutdown Protection Under Voltage Lockout Protection Adjustable Sofl Stan I HTSOP»JB Package (Backside Heat Dissipation) Applications I Step»down Power Supply lor DSPs. FPGAs. Microprocessors, etc. Set-top Box LCD TVs DVD I Blu-ray Player I Recorder Entertainment Devices Typical Application Circuit 50333215“ 6 vm BOOT EN Caoor 0.luF sw ‘ (va ‘ vour 2.2uH GND W Rig VREG FB 22“,: x2 35 Fe 0mm i 035 I Figure 1. Typical Application Circ OProduct structure. Silicon monolithic integrated lecull OThis product has no designed www.mhmcon © 2013 ROHM 0d. Ltd. All rights reserved, 1/25 Tszzzm -14- cm
Product structure: Silicon monolithic integrated circuit This product has no designed protection against radioactive rays.
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Datashee
t
4.5V to 18V Input, 3.0A Integrated MOSFET
1ch Synchronous Buck DC/DC Converter
BD9D321EFJ
General Description
BD9D321EFJ is a synchronous buck switching regulator
with built-in low on-resistance power MOSFETs. It is
capable of providing current of up to 3 A. The SLLMTM
control provides excellent efficiency characteristics in
light-load conditions which make the product appropriate
for equipment and devices that demand minimal standby
power consumption. External phase compensation circuit
is not necessary for it is a constant on-time control DC/DC
converter with high speed response.
Features
Synchronous Single DC/DC Converter
Constant On-time Control
SLLMTM (Simple Light Load Mode) Control
Over Current Protection
Short Circuit Protection
Thermal Shutdown Protection
Under Voltage Lockout Protection
Adjustable Soft Start
HTSOP-J8 Package (Backside Heat Dissipation)
Applications
Step-down Power Supply for DSPs, FPGAs,
Microprocessors, etc.
Set-top Box
LCD TVs
DVD / Blu-ray Player / Recorder
Entertainment Devices
Key Specifications
Input Voltage Range: 4.5V to 18.0 V
Output Voltage Setting Range: 0.765V to 7V
(VIN×0.07)V to (VIN×0.65)V
Output Current: 3 A (Max)
Switching Frequency: 700 kHz (Typ)
High Side MOSFET On-Resistance:100 m (Typ)
Low Side MOSFET On-Resistance: 70 m (Typ)
Standby Current: 2 μA (Typ)
Package W (Typ) x D (Typ) x H (Max)
HTSOP-J8 4.90mm x 6.00mm x 1.00mm
Typical Application Circuit
Figure 1. Typical Application Circuit
HTSOP-J8
Datasheet
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Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
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TSZ2211115001
Pin Configuration
Pin Descriptions
Terminal
No. Symbol Function
1 EN
Turning this terminal signal low level (0.3 V or lower) forces the device to enter the shutdown
mode. Turning this terminal signal high level (2.2 V or higher) enables the device. This
terminal must be terminated.
2 FB
An inverting input terminal of comparator which compares with reference voltage (VREF).
Refer to page.17 for how to calculate the resistance of the output voltage setting.
3 VREG
Power supply voltage terminal inside IC.
Voltage of 5.25V (Typ) is outputted with more than 2.2V is impressed to EN terminal.
Connect 1µF ceramic capacitor to ground.
4 SS Terminal for setting the soft start time. The rise time of the output voltage can be specified by
connecting a capacitor to this terminal. Refer to page.17 for how to calculate the capacitance.
5 GND Ground terminal for the output stage of the switching regulator and the control circuit
6 SW
Switch node. This terminal is connected to the source of the high-side MOSFET and drain of
the low-side MOSFET. Connect a bootstrap capacitor of 0.1µF between this terminal and
BOOT terminal. In addition, connect an inductor considering the direct current
superimposition characteristic.
7 BOOT
Connect a bootstrap capacitor of 0.1µF between this terminal and SW terminal.
The voltage of this capacitor is the gate drive voltage of the high-side MOSFET.
8 VIN
Power supply terminal for the switching regulator.
Connecting a 20µF(10µF×2) and 0.1µF ceramic capacitor to ground is recommended.
- FIN
A backside heat dissipation pad. Connecting to the internal PCB ground plane by using
multiple via provides excellent heat dissipation characteristics.
Figure 2. Pin Assignment
VIN
GND
FB
EN
SS
SW
7
8
6
5
3
4
2
1
(TOP VIEW)
VREG
BOOT
“Hm—IKL/w—o YEW
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BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
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29.Jan.2015 Rev.002
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Block Diagram
Figure 3. Block Diagram
Thermal
Protection
EN
UVLO
TSD Soft
Start
REF
SS
UVLO
OCP
TSD
On Time
Controller
Block
R
S
Q
BG
5V REG
VIN
VREG
EN
Driver
Circuit
OCP
SW
UVLO
5
GND
SW
VOUT
VIN
7BOOT
VIN
3
VREG
4
SS
FB
2
VOUT
BG
EN Logic
EN
1
8
6
TSD
VREG
3
ZERO
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BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
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TSZ2211115001
Absolute Maximum Ratings (Ta = 25C)
Parameter Symbol Rating Unit
Input Voltage (Note 1) VIN 20 V
BOOT Voltage (Note 1) VBOOT 27 V
BOOT-SW Voltage (Note 1) VBOOT-VSW 7 V
Output Feedback Voltage VFB VREG V
SW Voltage (Note 1) VSW 20 V
VREG Voltage (Note 1) VREG 7 V
SS Voltage (Note 1) VSS 7 V
Logic Input Voltage (Note 1) VEN 20 V
Power dissipation (Note 2) Pd 3.75 W
Operating Temperature Range Topr -40 to +85 °C
Storage Temperature Range Tstg -55 to +150 °C
Junction Temperature Tjmax +150 °C
(Note 1) No need to exceed Pd.
(Note 2) Derating in done 30.08 mW/°C for operating above Ta 25°C (Mount on 4-layer 70.0mm×70.0mm×1.6mm board)
Caution1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Caution2: The operating temperature range is intended to guarantee functional operation and does not guarantee the life of the LSI within this range. The life of
the LSI is subject to derating depending on usage environment such as the voltage applied, ambient temperature and humidity. Consider derating in the design
of equipment and devices.
Recommended Operating Conditions
Parameter Symbol
Limit
Unit
Min Typ Max
Input voltage VIN 4.5 12 18 V
BOOT voltage VBOOT 4.5 - 24 V
SW Voltage VSW -0.7 - +18 V
BOOT-SW voltage VBOOT-VSW 4.5 - 5.5 V
Logic Input Voltage VEN 0 - 18 V
Output Current IOUT - - 3 A
Output Voltage Range VRANGE 0.765 (Note 3) - 7 (Note 4) V
(Note 3) Please use under the condition of VOUT VIN×0.07 [V].
(Note 4) Please use under the condition of VOUT VIN×0.65 [V].
(Refer to the page 17 for how to calculate the output voltage setting.)
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BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
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29.Jan.2015 Rev.002
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Electrical Characteristics
(Ta = 25°C, VIN = 12V, VEN = 3V unless otherwise specified)
Parameter Symbol
Limit
Unit Conditions
Min Typ Max
<VIN Pin Block >
Standby Circuit Current ISTB - 2 15 µA VEN=GND
Operating Circuit Current IVIN - 0.7 2 mA
VEN=3V, IOUT=0mA
when no switching
<Enable Block >
EN Low Voltage VENL - - 0.3 V
EN High Voltage VENH 2.2 - VIN V
EN Bias Current IEN - 1.5 5 µA VEN=3V
<5V Linear Regulator Block >
VREG Standby Voltage VVREG_STB - - 0.1 V VEN=GND
VREG Output Voltage VVREG 5 5.25 5.5 V
Maximum Current IREG - 10 - mA
< Under-Voltage Lock-Out Block >
UVLO Threshold Voltage VVREG_UVLO 3.4 3.8 4.2 V VREG: Sweep up
UVLO Hysteresis Voltage dVVREG_UVLO 200 300 400 mV VREG: Sweep down
< Reference Voltage Block >
FB Threshold Voltage1 VREF1 0.753 0.765 0.777 V
VIN=12V, VOUT=1.8V
PWM Mode Operation
FB Threshold Voltage2 VREF2 0.741 0.757 0.773 V
VIN=12V, VOUT=5.0V
PWM Mode Operation
FB Input Current IFB - - 1 µA
SS Charge Current ISSC 1.4 2.0 2.6 µA
SS Discharge Current ISSD 0.1 0.2 - mA
VREG=5.25V,
VSS=0.5V
< On Time Control Block >
On Time Ton - 215 - nsec VIN=12V,
VOUT=1.8V
Minimum Off Time Toffmin 100 200 - nsec
<SW Block >
High Side FET ON Resistance RONH - 100 200 m
Low Side FET ON Resistance RONL - 70 140 m
< Over Current Protection Block >
Over Current Protection Current Limit Iocp - 5 - A (Note 5)
(Note 5) No tested on outgoing inspection.
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BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
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TSZ2211115001
Typical Performance Curves
1.50
1.60
1.70
1.80
1.90
2.00
00.511.522.53
IOUT [A]
VOUT [V]
0
5
10
15
20
25
30
35
40
45
50
0 5 10 15 20
EN [V]
EN Input Current [µA]
Figure 4. VIN Current vs Junction Temperature Figure 5. VIN Shutdown Current vs Junction Temperature
Figure 6. EN Current vs EN Voltage
Figure 7. Output Voltage vs Output Current
0
1
2
3
4
5
6
7
8
9
10
-50 0 50 100
Tj [°C]
VIN Supply Current [µA]
0
200
400
600
800
1000
1200
-50 0 50 100
Tj [°C]
VIN Supply Current [µA]
VIN=12V
VIN=12V
VIN=12V
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BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
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TSZ2211115001
Typical Performance Curves (Continued)
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
IOUT [A]
Efficiency [%]
1.70
1.72
1.74
1.76
1.78
1.80
1.82
1.84
1.86
1.88
1.90
0 5 10 15 20
VIN[V]
VOUT [V]
IOUT=10mA
Figure 8. Output Voltage vs Input Voltage
Figure 10. Start-up WaveformEN=0V5V
(VIN=12V, VOUT=1.8V, IOUT=3A, Css=3300pF)
500µsec/div
VOUT 1V/div
SW 10V/div
VREG 5V/div
EN 5V/div
Figure 11. Start-up WaveformVIN=EN
(VIN=12V, VOUT=1.8V, IOUT=3A, Css=3300pF)
500µsec/div
VOUT 1V/div
SW 10V/div
VREG 5V/div
VIN 10V/div
IOUT=1A
Figure 9. Efficiency vs Output Current
VOUT =1.05V
VOUT =1.8V
VOUT =3.3V
VIN=12V
VOUT =5.0V
VOUT =7.0V
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TSZ2211115001
Typical Performance Curves (Continued)
Figure 12. Shutdown WaveformEN=5V0V
(VIN=12V, VOUT=1.8V, IOUT=3A, Css=3300pF)
Figure 13. Shutdown WaveformVIN=EN
(VIN=12V, VOUT=1.8V, IOUT=3A, Css=3300pF)
500µsec/div
VOUT 1V/div
SW 10V/div
VREG 5V/div
VIN 10V/div
500µsec/div
VOUT 1V/div
SW 10V/div
VREG 5V/div
EN 5V/div
VOUT
50mV/div
IOUT
2.0A/div
Figure 15. Load Transient Response
(VIN=12V, VOUT=1.8V, IOUT=1A to 3A)
100µsec/div
VOUT
50mV/div
IOUT
2.0A/div
Figure 14. Load Transient Response
(VIN=12V, VOUT=1.8V, IOUT=50mA to 3A)
100µsec/div
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TSZ2211115001
Typical Performance Curves (Continued)
0
100
200
300
400
500
600
700
800
900
00.511.522.53
IOUT [A]
Switching Frequency [kHz]
VOUT=1.8V
400
450
500
550
600
650
700
750
800
850
900
0 5 10 15 20
VIN[V]
Switching Frequency [kHz]
IOUT=1A
VOUT=1.8V
VIN
100mV/div
SW
5V/div
Figure 18. Voltage Ripple at Input
(VIN=12V, VOUT=1.8V, IOUT=3A, L=2.2µH, CIN=10µF x 2)
Figure 17. Switching Frequency vs Output Current Figure 16. Switching Frequency vs Input Voltage
1µsec/div
VIN=12V
MEL—Ll; JIJJJJL
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Typical Performance Curves (Continued)
VOUT
20mV/div
SW
5V/div
Figure 19. Voltage Ripple at Output
(VIN=12V, VOUT=1.8V, IOUT=30mA, L=2.2µH, COUT=22µF x 2)
10µsec/div
VOUT
20mV/div
SW
5V/div
Figure 20. Voltage Ripple at Output
(VIN=12V, VOUT=1.8V, IOUT=3A, L=2.2µH, COUT=22µF x 2)
1µsec/div
0.745
0.75
0.755
0.76
0.765
0.77
0.775
0.78
0 20406080
ON Duty[%]
VREF [V]
Figure 21. Reference Voltage vs ON Duty
(PWM operation)
BD9D321EFJ Function Explanations 1 Basic Operation 1-1 Consmnt On Time Contr BD9D321EFJ is a single 5 it controls the on-iime by u Therefore ii runs wiih ihe 1-2 SLLMm Control BD9D321EFJ utilizes swi SLLM (Simple Light Load Datasheet
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TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
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TSZ2211115001
Function Explanations
1 Basic Operation
1-1 Constant On Time Control
BD9D321EFJ is a single synchronous buck switching regulator employing a constant on-time control system.
It controls the on-time by using the duty ratio of VOUT /VIN inside IC so that a switching frequency becomes 700 kHz.
Therefore it runs with the frequency of 700 kHz under the constant on-time decided with VOUT / VIN.
1-2 SLLMTM Control
BD9D321EFJ utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes
SLLM (Simple Light Load Mode) control for lighter load to improve efficiency.
Figure 23. SW Waveform (SLLMTM control)
(VIN = 12V, VOUT = 1.8V, IOUT = 30mA)
Figure 24. SW Waveform (PWM control)
(VIN = 12V, VOUT = 1.8V, IOUT = 3A)
SLLMTM Control
PWM Control
Figure 22. Efficiency (SLLM
TM
Control and PWM Control)
PWM Control
Efficiency η[%]
Output Current IOUT[A]
SLLMTM Control
VOUT
20mV/div
SW
5V/div
10µsec/div
VOUT
20mV/div
SW
5V/div
1µsec/div
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BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
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TSZ2211115001
EN
VOUT
FB
0.765V
SS
VTH
Td Tss
VEN
0
VOUT
0
Soft start time
VENH
VENL
EN terminal
Output setting voltage
t
t
1-3 Enable Control
The IC shutdown can be controlled by the voltage applied to the EN terminal. When VEN reaches 2.2 V (Typ), the
internal circuit is activated and the IC starts up.
Figure 25. Start-up with EN pin
1-4 Soft Start Function
By turning EN terminal to High, the soft start function operates and it gradually starts output voltage by controlling the
current at start-up. Also soft start function prevents sudden current and over shoot of output voltage. Rising time can
be set by connecting capacitor to SS terminal. For setting the rising time, please refer to page.17.
Figure 26. Soft Start Timing chart
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TSZ02201-0J3J0AC00490-1-2
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2 Protective Functions
The protective circuits are intended for prevention of damage caused by unexpected accidents. Do not use them
for continuous protective operation.
2-1 Over Current Protection (OCP)
Over current protection function is effective by controlling current which flows in low side MOSFET by 1 cycle each of
switching period. With inductor current exceeding the current restriction setting value IOCP when LG is ON, the HG
pulse cannot be hit even with FB voltage under REF voltage and LG continues to be ON until it is below IOCP. It hits
HG when it goes below IOCP. As a result both frequency and duty fluctuates and output voltage may decrease.
In a case where output is decreased because of OCP, output may rise after OCP is released due to the action at high
speed load response. This is non-latch protection and after over current situation is released the output voltage will
recover.
Figure 27. Over current protection timing chart
VOUT
FB
High side
MOSFET gate
(HG)
Low side
MOSFET gate
(LG)
Inductor current
OCP signal
inside IC
Output load
current Normal Over
Current Normal
OCP threshold (Iocp)
VREG Vow FB «evmml Hm suds MOSFET gale Low sue MOSFET gale uvm OFF ,3 uvm 0N Datasheet Normal operatxon UVLO Normal operatxon
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2-2 Under Voltage Lockout Protection (UVLO)
The Under Voltage Lockout Protection circuit monitors the VREG terminal voltage.
The operation enters standby when the VREG terminal voltage is 3.5 V (Typ) or lower.
The operation starts when the VREG terminal voltage is 3.8 V (Typ) or higher.
Figure 28. UVLO Timing Chart
Load at Startup
Ensure that the respective output has light load at startup of this IC. Also, restrain the power supply line noise at startup and
voltage drop generated by operating current within the hysteresis width of UVLO. Noise exceeding the hysteresis noise width
may cause the IC to malfunction.
2-3 Thermal Shutdown Function
When the chip temperature exceeds Tj = 175°C, the DC/DC converter is stopped. The thermal shutdown circuit is
intended for shutting down the IC from thermal runaway in an abnormal state with the temperature exceeding Tjmax =
150°C. Do not use this function for application protection design. This is non-latch protection.
Datasheet VIN GIN WW2 0|”; EDQDSZIEFJ L L L VIN BOOT CBOOT l l l E" 1W VOLIT VREG SW L RI cvwgo SS Co“ I“; 22uFX2 055 FB 1 I
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Application Example
Table 1. Recommended Component values
VIN [V] VOUT [V] R1 [k] R2 [k] C1 [pF] L H] (Note 7)
12 1.0 6.8 22 -
(Note 6) 1.5
12 1.05 8.2 22 -
(Note 6) 1.5
12 1.2 12+0.51 22 -
(Note 6) 1.5
12 1.8 30 22 -
(Note 6) 2.2
12 3.3 68+5.6 22 -
(Note 6) 2.2
12 5.0 120+3.3 22 -
(Note 6) 3.3
12 7.0 180+3.3 22 -
(Note 6) 3.3
(Note 6) C1 is a feed forward capacitor.
Additional phase boost can be achieved by adding the 5pF to 100pF capacitor (C1) in parallel with R1.
(Note 7) Recommended InductorALPS GLMC series
TDK SPM6530 series
Selection of Components Externally Connected
(1) Output LC Filter Constant
The DC/DC converter requires an LC filter for smoothing the output voltage in order to supply a continuous current to the
load. Selecting an inductor with a large inductance causes the ripple current IL that flows into the inductor to be small.
However, decreasing the ripple voltage generated in the output is not advantageous in terms of the load transient
response characteristic. An inductor with a small inductance improves the transient response characteristic but causes the
inductor ripple current to be large which increases the ripple voltage in the output voltage, showing a trade-off relationship.
The recommended inductor values are shown in Table 1.
Figure 29. Application Circuit
Datasheet Driver vm
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The inductor peak to peak ripple current IL is calculated using the following equation.
[A]
LFV
)V(VVΔI
OSCIN
OUTINOUTL
1
For example, with VIN = 12 V, VOUT = 1.8 V, L = 2.2µH and the switching frequency FOSC = 700 kHz, the calculated peak
current IL is 1.0A.
Then, the inductor saturation current must be larger than the sum of the maximum output current (IOUTMAX) and 1/2 of the
inductor ripple current (IL / 2).
The output capacitor COUT affects the output ripple voltage characteristics. The output capacitor COUT must satisfy the
required ripple voltage characteristics.
The output ripple voltage can be represented by the following equation.
[V])
FC
(RΔIΔV
OSCOUT
ESRLRPL
8
1
RESR is the Equivalent Series Resistance (ESR) of the output capacitor.
The capacitor rating must allow a sufficient margin with respect to the output voltage.
The output ripple voltage can be decreased with a smaller ESR.
A ceramic capacitor of about 22 µF to 100 µF is recommended.
Pay attention to total capacitance value, when additional capacitor CLOAD is connected in addition to output capacitor
COUT. Then, please determine CLOAD and soft start time Tss (Refer to (3) Soft Start Setting) as satisfying the following
equation.
[μF]
OUT
SSOUTOCP
LOADOUT V
T)I(I
CC
IOCP is Over Current Protection Current limit value.
IL
t
Inductor saturation current > IOUTMAX +IL /2
Average inductor current
(Output CurrentIOUT)
IL
Figure 30. Waveform of current through inductor Figure 31. Output LC filter circuit
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(2) Output Voltage Setting
The output voltage value can be set by the feedback resistance ratio.
Figure 32. Feedback Resistor Circuit
V
REFOUT V
R
RR
V
2
21
The VREF can be represented by the following equation defining VOUT_T as the target output voltage.
[V]
[V]
,
case In
case In
7105.02.022.0,65.05.0
765.002.05.007.0
_
2
__
__
IN
TOUT
IN
TOUT
REF
IN
TOUT
IN
TOUT
REF
IN
TOUT
V
V
V
V
V
V
V
V
V
V
V
V 
BD9D321EFJ can operate under the condition which satisfies the following equation.
650070 .
V
V
.
IN
OUT
3) Soft Start Setting
Turning the EN terminal signal High activates the soft start function. This causes the output voltage to rise gradually while
the current at startup is placed under control. This allows the prevention of output voltage overshoot and inrush current.
The rise time depends on the value of the capacitor connected to the SS terminal.
[msec]
[V][pF]
[msec]
[[V][pF]
3300pF, with
Typ)A 0Current(2. Source Terminal Start Soft is
Typ)7V voltage(0. threshold MOS Internal is
Typ).765V Voltage(0Terminal FB is
Terminal Time Start Soft to connected Capacitor is
Time Start Soft is
TimeDelay Start Soft is
where
1.45
2.01.150.7653300
1.16
2.00.73300
1.15
=
/ ) ( =
=
/ ) ( =
A][
A]
μ
μ
μ
SS
d
SS
SS
TH
FB
SS
SS
d
SSFBSSSS
S
S
THS
S
d
T
T
C
V
V
C
T
T
V
C
T
V
C
T
I
 
VOUT
R1
R2
FB Voltage
Reference
BD9 D321 EFJ Datasheet PCB Layout Design In the step-down DC/DC converter, 3 large flows when the high side FET is turned ON and output capacitor Cour and back to grcu flows when the low side FET is turned on. T capacitor Cour and back to ground cl the lo possible to allow noise to be reduced lcr im directly to the ground plane. The PCB layo generation, noise and efficiency characteris ‘l—MOS FET Figure Accordingly, design the PCB layout cons - Connect an input capacitor as close a - lfthere is any unused area on the PC the IC and the surrounding componen - Switching nodes such as SW are sus thick and as short as possible. - Provide lines connected to F3 and SS - Place the output capacitor away from TOP Layer Figure 34. Exam www.mhm.oo.]p © 2013 ROHM 00.. Ltd. All rights reserved. 18 T5222111-15m1
18/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
PCB Layout Design
In the step-down DC/DC converter, a large pulse current flows into two loops. The first loop is the one into which the current
flows when the high side FET is turned ON. The flow starts from the input capacitor CIN, runs through the FET, inductor L
and output capacitor COUT and back to ground of CIN via ground of COUT. The second loop is the one into which the current
flows when the low side FET is turned on. The flow starts from the low side FET, runs through the inductor L and output
capacitor COUT and back to ground of the low side FET via ground of COUT. Route these two loops as thick and as short as
possible to allow noise to be reduced for improved efficiency. It is recommended to connect the input and output capacitors
directly to the ground plane. The PCB layout has a great influence on the DC/DC converter in terms of all of the heat
generation, noise and efficiency characteristics.
Accordingly, design the PCB layout considering the following points.
Connect an input capacitor as close as possible to the IC VIN terminal on the same plane as the IC.
If there is any unused area on the PCB, provide a copper foil plane for the ground node to assist heat dissipation from
the IC and the surrounding components.
Switching nodes such as SW are susceptible to noise due to AC coupling with other nodes. Route the coil pattern as
thick and as short as possible.
Provide lines connected to FB and SS far from the SW nodes.
Place the output capacitor away from the input capacitor in order to avoid the effect of harmonic noise from the input.
Figure 34. Example of PCB layout
EN GND_S GND VIN VIN_S
VOUT_S
VOUT
GND
GND_S
EN GND_S GND VIN VIN_S
VOUT_S
VOUT
GND
GND_S
Figure 33. Current Loop of Buck Converter
CIN
MOS FET
COUT
VOUT
L
VIN
TOP Layer Bottom Layer
VOUT_S
VOUT
GND
GND_S
EN GND_S GND VIN VIN_S
R2
R1
C1
C
VREG
C
SS
C
IN
C
BOOT
L
C
OUT
VOUT_S
VOUT
GND
GND_S
EN GND_S GND VIN VIN_S
R2
R1
C1
C
VREG
C
SS
C
IN
C
BOOT
L
C
OUT
VOUT_S
VOUT
GND
GND_S
EN GND_S GND VIN VIN_S
R2
R1
C1
C
VREG
C
SS
C
IN
C
BOOT
L
C
OUT
Power d issi p alion[W] ‘3 V‘ .'\’ .0" o m A UV m m w m b 50 100 Ambienl ‘emperaturercl Datasheet
19/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
Power Dissipation
When designing the PCB layout and peripheral circuitry, sufficient consideration must be given to ensure that the power
dissipation is within the allowable dissipation curve.
HTSOP-J8 Package
70 70 1.6 mm assembled glass epoxide board
(1) 4-layer board (Copper foil area 70 mm 70 mm)
(2) 2-layer board (Copper foil area 70 mm 70 mm)
(3) 2-layer board (Copper foil area 15 mm 15 mm)
(4) 1-layer board (Copper foil area 0 mm 0 mm)
Figure 35. Power dissipation (HTSOP-J8)
20/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
EN
333kΩ
666kΩ
1MΩ
VREG
VIN
BOOT
VREG
SW
VIN
SW
VIN
BOOT
I/O Equivalent Circuit
1. EN 2. FB
3. VREG 4. SS
6. SW 7. BOOT
Figure 36. I/O equivalence circuit
SS
VREG
2.3kΩ
Datasheet
21/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
terminals.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on 4 - layer 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum
rating, increase the board size and copper area to prevent exceeding the Pd rating.
6. Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
7. Rush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
8. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
Datasheet H P l 4:- N N t Parasmc LElements P Subsnale ; 1: (3ND Parasmc Elements TranslsmrmPN) B l PlnB \l" ]:GND GND: Parasmc Elements P Subsnale N Raglan closlrby
22/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
Operational Notes – continued
11. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Figure 37. Example of monolithic IC structure
12. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be
within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below the
TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
14. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
Datasheet Pan Number Package Pan Number Markmg A/ LOT Number 0\ 1P|N MARK www.rohm,cu.]p © 2013 ROHM Co” Ltd. An rights reserved, 23/25 T5202201-0J3J0AC00490-1-2 13222111 15001 29.Jan.2015 Rev.002
23/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
Ordering Information
B D 9 D 3 2 1 E F J - E 2
Part Numbe
r
Package
EFJ: HTSOP-J8
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
HTSOP-J8 (TOP VIEW)
D9D321
Part Number Marking
LOT Numbe
r
1PIN MARK
Datasheet 4 9:0. 1 1Max5. 25 include. BURR) (.1 2) s 1 s 5 (2V 4) 4 u. 545 _1PIN MARK 7 ¥ 0.17% n ”w m—ui 3 [fl 3 \ \ [j I ~ m w \ \ a o ‘ . . \ ,mos A a fi \ 27 va-OW m as \ on a . . V (UNTT:mm} o c PKG:1|TSOP-JB Drawing Nn,l-ZX169*5002*2
24/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
Physical Dimension, Tape and Reel Information
Package Name HTSOP-J8
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
Direction of feed
Reel 1pin
Datasheet
25/25
Datasheet
Datasheet
BD9D321EFJ
TSZ02201-0J3J0AC00490-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
29.Jan.2015 Rev.002
www.rohm.co.jp
TSZ2211115001
Revision History
Date Revision Changes
07.Aug.2013 001 Created
29.Jan.2015 002 Revised the Electrical Characteristics and Table1. Added Figure 21.
Datasheet
Datasheet
Datasheet
Notice-GE Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
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serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN USA EU CHINA
CLASS CLASS CLASSb CLASS
CLASS CLASS
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
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a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
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[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
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4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
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Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
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2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
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please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Datasheet
Datasheet
Datasheet
Notice-GE Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
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2. You agree that application notes, reference designs, and associated data and information contained in this document
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Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
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isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
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3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
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DatasheetDatasheet
Notice – WE Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
General Precaution
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