PowerSSO-36
exposed pad up
Features
• 160-W + 160-W output power at THD = 10% with RL = 4 Ω and VCC = 36 V
• 1 x 220 W output power mono parallel BTL at THD = 10% with RL = 3 Ω and
VCC = 36 V
• Wide-range single-supply operation (14 - 36 V)
• High efficiency (η = 85%)
• Parallel BTL function using the MODE pin
• Four selectable, fixed gain settings of nominally 23.8 dB, 29.8 dB, 33.3 dB and
35.8 dB
• Differential inputs minimize common-mode noise
• Standby and mute features
• Smart protection
• Thermal overload protection
• Small offset less than 20 mV
Description
The TDA7498E is a dual BTL class-D audio amplifier with a single power supply
designed for home systems and active speaker applications.
It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate
mounting a separate heatsink.
Maturity status link
TDA7498E
Device summary
Order code TDA7498ETR
Operating
temperature range 0 to 70 °C
Package PowerSSO36
(EPU)
Packing Tape and reel
160-watt + 160-watt dual BTL class-D audio amplifier
TDA7498E
Datasheet
DS8807 - Rev 3 - December 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
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1Device block diagram
The figure below shows the block diagram of one of the two identical channels of the TDA7498E.
Figure 1. Internal block diagram (showing one channel only)
TDA7498E
Device block diagram
DS8807 - Rev 3 page 2/17
:jjjjjjjjjjjjjjjjj
::::::::::::::::::
2Pin description
2.1 Pinout
Figure 2. Pin connections (top view, PCB view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
28
29
30
31
32
33
34
35
36
19
20
21
22
23
24
25
26
27
VSS SUB_GND
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB
OUTNA
OUTNA
PVCCA
PVCCA
PGNDA
PGNDA
OUTPA
OUTPA
PGND
VDDPW
STBY
MUTE
INPA
INNA
ROSC
SYNCLK
VDDS
SGND
DIAG
SVR
GAIN
MODE
INPB
INNB
VREF
SVCC
EP, exposed pad
Connect to ground
TDA7498E
Pin description
DS8807 - Rev 3 page 3/17
2.2 Pin list
Table 1. Pin description list
Number Name Type Description
1 SUB_GND PWR Connect to the frame
2,3 OUTPB O Positive PWM for right channel
4,5 PGNDB PWR Power stage ground for right channel
6,7 PVCCB PWR Power supply for right channel
8,9 OUTNB O Negative PWM output for right channel
10,11 OUTNA O Negative PWM output for left channel
12,13 PVCCA PWR Power supply for left channel
14,15 PGNDA PWR Power stage ground for left channel
16,17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 GAIN I Gain setting input
31 MODE I Enables stereo or mono BTL mode of operation
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply
36 VSS O 3.3-V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to ground
TDA7498E
Pin list
DS8807 - Rev 3 page 4/17
3Electrical specifications
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage for pins PVCCA, PVCCB, SVCC 45 V
VI Voltage limits for input pins STBY, MUTE, INNA,
INPA, INNB, INPB, GAIN, MODE -0.3 to 4.0 V
TjOperating junction temperature 0 to 150 °C
Top Operating ambient temperature 0 to 70 °C
Tstg Storage temperature -40 to 150 °C
3.2 Thermal data
Table 3. Thermal data
Symbol Parameter Min. Typ. Max. Unit
Rth j-case Thermal resistance, junction to case - 3.0 °C/W
3.3 Recommended operating conditions
Table 4. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
VCC Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 39 V
Tamb Ambient operating temperature 0 - 70 °C
3.4 Electrical specifications
Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 36 V, RL = 4 Ω,
ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 23.6 dB Tamb = 25 °C.
Table 5. Electrical specifications
Symbol Parameter Condition Min. Typ. Max. Unit
IqTotal quiescent current No LC filter, no load - 60 mA
IqSTBY Quiescent current in standby - - 1 µA
VOS Output offset voltage Vi = 0, Av = 23.6 dB, no load -20 - 20 mV
IOCP Overcurrent protection threshold RL = 0 Ω 10 11 14 A
TjJunction temperature at thermal
shutdown - 140 150 160 °C
RiInput resistance Differential input 69 - kΩ
VUVP Undervoltage protection threshold - - - 8 V
TDA7498E
Electrical specifications
DS8807 - Rev 3 page 5/17
Symbol Parameter Condition Min. Typ. Max. Unit
RdsON Power transistor on-resistance
High side - 0.15 -
Ω
Low side - 0.15 -
PoOutput power
THD = 10% - 160 -
W
THD = 1% - 125 -
Po
Parallel BTL (mono) output power,
RL = 3 ohm, Vcc = 36 V
THD = 10% - 220 -
W
THD = 1% - 170 -
η Efficiency - 85 - %
THD Total harmonic distortion Po = 1 W - 0.05 - %
GVClosed-loop gain
GAIN < 0.25*VDD 23.8
dB
0.25*VDD < GAIN < 0.5*VDD 29.8
0.5*VDD < GAIN < 0.75*VDD 33.3
GAIN > 0.75*VDD 35.8
ΔGVGain matching - -1 - 1 dB
CTCrosstalk f = 1 kHz, Po = 1 W 50 60 - dB
Vn Total output noise
Inputs shorted and to ground,
A Curve 231
µV
Inputs shorted and to ground,
f = 20 Hz to 20 kHz 400
SVRR Supply voltage rejection ratio
fr = 100 Hz, Vr = 0.5 Vpp,
CSVR = 10 µF - 55 - dB
Tr, TfRise and fall times - - 35 - ns
fSW Switching frequency Internal oscillator 240 310 400 kHz
fSWR Output switching frequency range With internal oscillator by changing
ROSC (1) 240 - kHz
VinH Digital input high (H)
-
2.0 - -
V
VinL Digital input low (L) - - 0.8
Function
mode Standby & mute & play
STBY < 0.5 V; MUTE = X Standby
STBY > 2.5 V; MUTE < L Mute
STBY > 2.5 V; MUTE > H Play
AMUTE Mute attenuation VMUTE < L, VSTBY = H - 75 - dB
1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 3. Test circuit stereo application and
mono BTL mode).
TDA7498E
Electrical specifications
DS8807 - Rev 3 page 6/17
3.5 Test circuit
Figure 3. Test circuit stereo application and mono BTL mode
GAIN SETTING
GAIN JUMPER
23.6dB
29.6dB
33.1dB
35.6dB
J9
J10
J11
J12
Optional components or circuitry
L+
R+
R-
VCC
GND
L+
L-
R+
R-
TDA7498E
MUTE
STBY
3V3 POWER SUPPLY
Single-Ended
Input
CLASS-D AMPLIFIER
For Single-Ended
Input and
Load=4 ohm
For
LOUTPUT
INPUT
L-
MONO
OUT
FREQUENCY SHIFT
Load=4 ohm
R-OUTPUT
MONO
OUT
(PSSO36)
MONO Config
MONO
Config
MONO
INPUT
L+, L- Only
MODE SETTING
STEREO
MONO
MODE JUMPER
J5
J6,J3,J8
C5
100nF
L4
C1
1uF
C2
1uF
C11
1uF
C12
1uF
C25
100nF
C19
100nF
C27
330pF
R6
22R C40
220nF
C41
220nF
C21
330pF
R5
22R
C42
220nF
C43
220nF
C3
1nF
C4
1nF
C13
1nF
C14
1nF
32 INPB
36 VSS
9
OUTNB
5
PGNDB
7
PVCCB
3
OUTPB
10
OUTNA
12
PVCCA
14
PGNDA
16
OUTPA
33 INNB
8
OUTNB
4
PGNDB
21 MUTE
6
PVCCB
2
OUTPB
29
SVR
11
OUTNA
1SUB_GND
22 INPA
23 INNA
27 SGND
26 VDDS
28 DIAG
19 VDDPW
18 PGND
20 STBY
24 ROSC
31 MODE
35 SVCC
30 GAIN
25 SYNCLK
17
OUTPA
15
PGNDA
34
VREF
13
PVCCA
IC1
TDA7498E
R1
47k
R7
22R
C6
100nF
R4
120k
R2
33k
R8
6.8k
C26
1uF
C10
100nF
C20
1uF
J6
J9
2
1
3
S1
2
1
3
S2
C9
100nF
C29
2.2uF 2GND
1
OUT
3
IN
IC2
L4931CZ33
+C15
2.2uF
16V
1
2
J2
J8
J7
+C7
2.2uF
16V
+
C23
2200uF
50V
L3
L1
L2
C17
10uF
10V
C16
10uF
10V
D1
18V
J4
C30
1uF
C31
1uF
R15
8R
C28
220nF
R16
8R
C24
220nF
R17
8R
C18
220nF
R18
8R
C22
220nF
SYNC
2
4
1
3
J1
R10
100k
R11
100k
R12
100k
J11
J12
J5
J10
J3
R3
39K
C8
100nF
R9
180K
1
2
3
Q1
KTC3875(S)
R13
47k
R14
100k
D2
D3
D4
D8
D6
D5
D7
D9
+
C32
2200uF
50V
1
2
J14
1
2
J13
WL+
WR+
WL-
WR-
L1S
L2S
L3S
L4S
R19
33k
DIAG
VDDS
VDDS
VDDS
VCC
VCC
VCC
VCC
VCC
VDDS
3V3 PS
PS
TDA7498E
Test circuit
DS8807 - Rev 3 page 7/17
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4Characterization curves
Unless otherwise stated the measurements were made under the following conditions:
VCC = 36 V, f = 1 kHz, GV = 23.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C
4.1 For RL = 4 Ω, stereo configuration
Figure 4. Output power vs. supply voltage Figure 5. THD vs. output power
Figure 6. THD vs. frequency Figure 7. FFT performance
Figure 8. Crosstalk vs. frequency
TDA7498E
Characterization curves
DS8807 - Rev 3 page 8/17
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4.2 For RL = 3 Ω, mono BTL configuration
Figure 9. Output power vs. supply voltage Figure 10. THD vs. output power
Figure 11. THD vs. frequency
TDA7498E
For RL = 3 Ω, mono BTL configuration
DS8807 - Rev 3 page 9/17
5Application information
5.1 Stereo and mono BTL operation selection using the MODE pin
The TDA7498E can be used in stereo applications or mono BTL applications. Connecting the MODE pin to the
VDDS pin configures the device in mono BTL. The output of the two channels can be paralleled. When the MODE
pin is connected to ground or floating (pulled down internally) the device works as a stereo amplifier.
5.2 Gain setting
The gain of the TDA7498E is set by GAIN (pin 30).
Table 6. Gain settings
GAIN Total gain Application recommendation
VGAIN < 0.25*VDDS 23.6 dB GAIN pin connected to SGND
0.25*VDDS < VGAIN < 0.5*VDDS 29.6 dB Rc10 = Rc11 = Rc12 = 100 K max
0.5*VDDS < VGAIN < 0.75*VDDS 33.1 dB Rc10 = Rc11 = Rc12 = 100 K max
VGAIN > 0.75VDDS 35.6 dB GAIN pin connected to VDDS
5.3 Smart protection
The TDA7498E embeds an overcurrent protection circuitry to protect the device from unwanted current peaks. If
the overcurrent protection threshold (Table 5. Electrical specifications) is exceeded, the power stage will be shut
down immediately. The device will recover automatically once the fault is removed.
TDA7498E
Application information
DS8807 - Rev 3 page 10/17
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6Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
6.1 PowerSSO-36 EPU package information
The device comes in a 36-pin PowerSSO package with exposed pad up (EPU).
Figure 12. PowerSSO-36 EPU package outline shows the package outline and Table 7. PowerSSO-36 EPU
package mechanical data gives the dimensions.
Figure 12. PowerSSO-36 EPU package outline
h x 45°
TDA7498E
Package information
DS8807 - Rev 3 page 11/17
Table 7. PowerSSO-36 EPU package mechanical data
Symbol
Dimensions in mm Dimensions in inches
Min. Typ. Max. Min. Typ. Max.
A 2.15 - 2.45 0.085 - 0.096
A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G - - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h - - 0.40 - - 0.016
k 0 - 8 degrees 0 - 8 degrees
L 0.55 - 0.85 0.022 - 0.033
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 4.90 - 7.10 0.193 - 0.280
TDA7498E
PowerSSO-36 EPU package information
DS8807 - Rev 3 page 12/17
Revision history
Table 8. Document revision history
Date Revision Changes
12-Dec-2011 1 Initial release.
16-Jun-2015 2
Updated VCC in Table 3: "Absolute maximum ratings" , updated Section 6.3:
"Smart protection", and updated dimension L in Table 8: "PowerSSO-36 EPU
package mechanical data".
10-Dec-2018 3 Updated device summary on the cover page.
TDA7498E
DS8807 - Rev 3 page 13/17
Contents
1Device block diagram..............................................................2
2Pin description ....................................................................3
2.1 Pinout ........................................................................3
2.2 Pin list ........................................................................4
3Electrical specifications ...........................................................5
3.1 Absolute maximum ratings.......................................................5
3.2 Thermal data ..................................................................5
3.3 Recommended operating conditions ..............................................5
3.4 Electrical specifications .........................................................5
3.5 Test circuit ....................................................................6
4Characterization curves............................................................8
4.1 For RL = 4 Ω, stereo configuration ................................................8
4.2 For RL = 3 Ω, mono BTL configuration .............................................8
5Application information...........................................................10
5.1 Stereo and mono BTL operation selection using the MODE pin .......................10
5.2 Gain setting ..................................................................10
5.3 Smart protection ..............................................................10
6Package information..............................................................11
6.1 PowerSSO-36 EPU package information..........................................11
Revision history .......................................................................13
Contents ..............................................................................14
List of tables ..........................................................................15
List of figures..........................................................................16
TDA7498E
Contents
DS8807 - Rev 3 page 14/17
List of tables
Table 1. Pin description list ...................................................................4
Table 2. Absolute maximum ratings .............................................................5
Table 3. Thermal data.......................................................................5
Table 4. Recommended operating conditions.......................................................5
Table 5. Electrical specifications................................................................5
Table 6. Gain settings ...................................................................... 10
Table 7. PowerSSO-36 EPU package mechanical data ............................................... 12
Table 8. Document revision history ............................................................. 13
TDA7498E
List of tables
DS8807 - Rev 3 page 15/17
List of figures
Figure 1. Internal block diagram (showing one channel only) ...........................................2
Figure 2. Pin connections (top view, PCB view) ...................................................3
Figure 3. Test circuit stereo application and mono BTL mode ...........................................7
Figure 4. Output power vs. supply voltage ........................................................8
Figure 5. THD vs. output power ...............................................................8
Figure 6. THD vs. frequency .................................................................8
Figure 7. FFT performance ..................................................................8
Figure 8. Crosstalk vs. frequency ..............................................................8
Figure 9. Output power vs. supply voltage ........................................................9
Figure 10. THD vs. output power ...............................................................9
Figure 11. THD vs. frequency .................................................................9
Figure 12. PowerSSO-36 EPU package outline .................................................... 11
TDA7498E
List of figures
DS8807 - Rev 3 page 16/17
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© 2018 STMicroelectronics – All rights reserved
TDA7498E
DS8807 - Rev 3 page 17/17
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