DV75D Datasheet by Connor-Winfield

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m w fwous a| R0 H S COMPLIANT
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851- 4722
Fax: 630- 851- 5040
www.conwin.com
5x7mm
Precision TCXO
Model DV75D
Description:
The Connor-Winfield’s DV75D is a 5x7mm
Surface Mount Temperature Compensated
Crystal Controlled Oscillator (TCXO) with
LVCMOS output. Through the use of Analog
Temperature Compensation, the DV75D
is capable of holding sub 1-ppm stabilities
over the -40 to 85°C temperature range.
Operating Specifications
Parameter Minimum Nominal Maximum Units Notes
Nominal Frequency (Fo) - 10.0, 12.8 or 20.0 - MHz
Frequency Calibration @ 25 °C -1.0 - 1.0 ppm 1
Frequency Stability vs. Temperature -1.0 - 1.0 ppm 2
Frequency vs. Load Stability -0.05 - 0.05 ppm ±5%
Frequency vs. Voltage Stability -0.05 - 0.05 ppm ±5%
Static Temperature Hysteresis - - 0.4 ppm 3
Aging -1.0 - 1.0 ppm/year
Operating Temperature Range: -40 - 85 °C
Supply Voltage (Vcc) 3.135 3.3 3.465 Vdc ±5%
Supply Current (Icc) - 2.1 6 mA
Period Jitter - 3 5 ps rms
Integrated Phase Jitter - 0.3 1.0 ps rms 4
Typical Phase Noise Fo = 20.0 MHz
SSB Phase Noise at 10Hz offset - -90 - dBc/Hz
SSB Phase Noise at 100Hz offset - -120 - dBc/Hz
SSB Phase Noise at 1KHz offset - -140 - dBc/Hz
SSB Phase Noise at 10KHz offset - -150 - dBc/Hz
SSB Phase Noise at 100KHz offset - -150 - dBc/Hz
Start-up Time - - 10 ms
Absolute Maximum Ratings
Parameter Minimum Nominal Maximum Units Notes
Storage Temperature -55 - 85 °C
Supply Voltage (Vcc) -0.5 - 6.0 Vdc
Input Voltage -0.5 - Vcc+0.5 Vdc
Features:
TCXO
3.3 Vdc Operation
LVCMOS Output
Frequency Stability: ± 1.0 ppm
Temperature Range: -40 to 85°C
Low Jitter <1ps RMS
5x7mm Surface Mount Package
Tape and Reel Packaging
RoHS Compliant / Pb Free
LVCMOS Output Characteristics
Parameter Minimum Nominal Maximum Units Notes
Load - 15 - pF 5
Voltage (High) (Voh) 90%Vcc - - Vdc
(Low) (Vol) - - 10%Vcc Vdc
Duty Cycle at 50% of Vcc 45 50 55 %
Rise / Fall Time 10% to 90% - 4 8 ns
Package Characteristics
Package Hermetically sealed crystal mounted on a ceramic package
Notes:
1. Initial calibration @ 25°C. Specifications at time of shipment after 48 hours of operation.
2. Frequency stability vs. change in temperature. [±(Fmax - Fmin)/(2*Fo)].
3. Frequency change after reciprocal temperature ramped over the operating range. Frequency measured before and after at 25°C.
4. BW = 12 KHz to Fo/2 MHz.
5. For best performance it is recommended that the circuit connected to this output should have an equivalent input capacitance of 15pF.
Environmental Characteristics
Vibration Vibration per Mil Std 883E Method 2007.3 Test Condition A
Shock Mechanical Shock per Mil Std 883E Method 2002.4 Test Condition B.
Soldering Process RoHS compliant lead free. See soldering profile on page 2.
Ordering Information
DV75D-010.0M, DV75D-012.8M or DV75D-020.0M
DV75D 1202
20.0 MHZ
Bulletin Tx356
Page 1 of 2
Revision 04
Date 11 June 2019
Applications:
GR-253-CORE (SMC)
ITU-T-G.813 Option 1 and 2 (SEC)
Available at Digi-Key
www.digikey.com
CONNOR WINFIELD ,2 LIT. i W 1. . ”a q Q
Specifications subject to change without notification. See Connor-Winfield's website for latest revision.
© Copyright 2019 The Connor-Winfield Corporation Not intended for life support applications.
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851- 4722
Fax: 630- 851- 5040
www.conwin.com
Suggested Pad Layout
Design Recommendations
Output Waveform
Tape and Reel Dimensions
Pad Connections
Solder Profile
120°C
150°C
180°C
260°C
0
220°C
Up to 120 s
Typical
10 s
60 to 90 s
Typical
Temperature 260°C
Meets IPC/JEDEC J-STD-020C
Package Layout
1V/Div
4
12
3
N/C
Output
15 pF
Vcc
Supply
Voltage
0.1 uF
Bypass
10 nF
Bypass
OSC
TOP LAYER
GROUND LAYER
BOTTOM LAYER
Output
Buffer
50 Ohm Trace
Without
Vias
.......
Buffer
Ground
50 Ohm trace
<1”by design
Vcc
Ground
Top View
0.010”(0.254mm)
Recommended
clearance
inductance
for internal
copper flood.
4
5
9
10
4
12
3
Vcc, should have
a large copper
area for reduced
inductance.
Connect a 0.01uF
bypass capacitor
<0.1”(2.54mm)
from the pad.
Ground,
should have
a large copper
area for reduced
inductance.
Top View
Test Circuit
Attention: To achieve optimal frequency stability, and in some cases to meet the specification stated on this data
sheet, it is required that the circuit connected to this TCXO output must have the equivalent input capacitance
that is specified by the nominal load capacitance. Deviations from the nominal load capacitance will have a
graduated effect on the stability of approximately 20 ppb per pF load difference.
Bulletin Tx356
Page 2 of 2
Revision 04
Date 11 June 2019
1: N/C
2: Ground
3: Output (Fo)
4: Supply Voltage (Vcc)
Dimensional Tolerance:
±.005 (.127mm)
±.02 (.508mm)
0.276 0.006
(7.0mm)
±
0.197
0.006
(5.0mm)
±
0.095 Max.
(2.4mm)
0.03
(0. mm)
4
90
(4 Places)
0.0
( mm)
55
1.40
(4 Places)
Pad 1
12
3
4
(Bottom View)
(Top View)
DV75D 1923
12.8 MHZ
(Top View)
12
3
4
0.165
(4.2mm)
0.224
(5.7mm)
0.047
(1.2mm)
4 Places
0.071
(1.8mm)
4 Places
Keep
Out *
Area
* Do not route any traces in the keep out area. It is
recommended the next layer under the keep out area
is to be ground plane.
Revision History
Revision Date Note
00 01/11/12 New issue
01 11/26/12 Removed tri-state information from features and description.
02 04/15/13 Added "Applications.
03 12/03/13 Removed TR from Ordering Information.
04 06/11/19 Updated stability, supply current, phase noise and height specifications.

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