USBLC6-4 Datasheet by STMicroelectronics

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‘ ’I 111e.augmemed 11%:
This is information on a product in full production.
November 2015 DocID11068 Rev 7 1/13
USBLC6-4
Very low capacitance ESD protection
Datasheet
-
production data
Figure 1. Functional diagram
Features
4 data-line protection
Protects V
BUS
Very low capacitance: 3 pF typ.
Peak pulse power (8/20 µs): 130 W typ.
SOT23-6L package
RoHS compliant
Benefits
Very low capacitance between lines to GND for
optimized data integrity and speed
Low PCB space consumption, 9 mm²
maximum foot print
Enhanced ESD protection: IEC 61000-4-2
level 4 compliance guaranteed at device level,
hence greater immunity at system level
ESD protection of V
BUS
: allows ESD current
flowing to ground when ESD event occurs on
data line
High reliability offered by monolithic integration
Low leakage current for longer operation of
battery powered devices
Fast response time
Consistent D+ / D- signal balance:
Best capacitance matching tolerance
I/O to GND = 0.015 pF
Compliant with USB 2.0 requirements
< 1 pF
Complies with the following standards
IEC 61000-4-2 level 4:
15 kV (air discharge)
8 kV (contact discharge)
Applications
USB 2.0 ports up to 480 Mb/s (high speed)
Backwards compatible with USB 1.1 low and
full speed
Ethernet port: 10/100 Mb/s
SIM card protection
Video line protection
Portable electronics
Description
The USBLC6-4 is a monolithic application specific
device dedicated to ESD protection of high speed
interfaces, such as USB 2.0, Ethernet links and
video lines.
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
SOT23-6L
116
25
34
I/O1 I/O4
GND VBUS
I/O2 I/O3
www.st.com
Characteristics USBLC6-4
2/13 DocID11068 Rev 7
1 Characteristics
Table 1. Absolute ratings
Symbol Parameter Value Unit
V
PP
Peak pulse voltage
IEC 61000-4-2 air discharge
IEC 61000-4-2 contact discharge
MIL STD883C-Method 3015-6
15
15
25
kV
T
stg
Storage temperature range -55 to +150 °C
T
j
Operating junction temperature range -40 to +125 °C
T
L
Lead solder temperature (10 seconds duration) 260 °C
Table 2. Electrical characteristics (T
amb
= 25 °C)
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
I
RM
Leakage current V
RM
= 5.25 V 10 150 nA
V
BR
Breakdown voltage
between V
BUS
and GND I
R
= 1 mA 6 10 V
V
F
Forward voltage I
F
= 10 mA 0.86 V
V
CL
Clamping voltage
I
PP
= 1 A, 8/20 µs
Any I/O pin to GND 12 V
I
PP
= 5 A, 8/20 µs
Any I/O pin to GND 17 V
C
i/o-GND
Capacitance between I/O
and GND V
R
= 1.65 V 3 4 pF
ΔC
i/o-GND
0.015
C
i/o-i/o
Capacitance between I/O V
R
= 1.65 V 1.85 2.7 pF
ΔC
i/o-i/o
0.04
DocID11068 Rev 7 3/13
USBLC6-4 Characteristics
13
Figure 2. Capacitance versus voltage
(typical values) Figure 3. Line capacitance versus frequency
(typical values)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C(pF)
F=1MHz
V =30mV
T=25°C
OSC RMS
j
C=I/O-I/O
j
C =I/O-GND
O
Data line voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1 10 100 1000
C(pF)
V =30mV
T=25°C
OSC RMS
j
V =1.65V
CC
F(MHz)
V =0V
CC
Figure 4. Relative variation of leakage current
versus junction temperature (typical values) Figure 5. Frequency response
1
10
100
25 50 75 100 125
T (°C)
j
V =5V
BUS
I[T
RM j] / I [T
RM j=25°C]
100.0k 1.0M 10.0M 100.0M 1.0G
-20.00
-15.00
-10.00
-5.00
0.00 S21(dB)
F(Hz)
Technical information USBLC6-4
4/13 DocID11068 Rev 7
2 Technical information
2.1 Surge protection
The USBLC6-4SC6 is particularly optimized to provide surge protection based on the rail to
rail topology.
The clamping voltage V
CL
can be calculated as follows:
V
CL
+ = V
TRANSIL
+ V
F
for positive surges
V
CL
- = - V
F
for negative surges
with: V
F
= V
T
+ R
d
.I
p
(V
F
forward drop voltage, V
T
forward drop threshold voltage
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
R
d
= 0.5 Ω and V
T
= 1.1 V.
For an IEC 61000-4-2 surge level 4 (Contact Discharge: V
g
= 8 kV, R
g
= 330 Ω),
V
BUS
= +5 V, and if in a first approximation, we assume that:
I
p
= V
g
/ R
g
= 24 A.
So, we find:
V
CL
+ = +31.2 V
V
CL
- = -13.1 V
Note: The calculations do not take into account phenomena due to parasitic inductances.
2.2 Surge protection application example
If we consider that the connections from the pin V
BUS
to V
CC
, from I/O to data line and from
GND to PCB GND plane are implemented as racks 10 mm long and 0.5 mm large, we can
assume that the parasitic inductances L
VBUS
L
I/0
and L
GND
of these tracks are about 6 nH.
So, when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (t
r
= 1 ns), the
voltage V
CL
has an extra value equal to L
I/0
·dI/dt, + L
GND
·dI/dt
The dI/dt is calculated as:
dI/dt = I
p
/t
r
= 24 A/ns
The overvoltage due to the parasitic inductances is:
L
I/0
·dI/dt, = L
GND
·dI/dt = 6 x 24 = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
V
CL
+ = +31.2 + 144 + 144 = 319.2 V
V
CL
- = -13.1 - 144 -144 = -301.1 V
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see 2.3: How to ensure good ESD
protection).
DocID11068 Rev 7 5/13
USBLC6-4 Technical information
13
Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends
on the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
CC
to the V
BUS
pin and from GND plane to GND pin must be as short
as possible to avoid overvoltages due to parasitic phenomena (see Figure 7 and Figure 8
for layout considerations)
V
BUS
LI/O LVBUS
LGND
LI/O
LGND
Vpin
CC
VCL
VF
I/O pin
VTRANSIL V+V
TRANSIL F
-V
F
VCL-
t = 1 ns
r
t
t
t = 1 ns
r
VCL+
GND pin
Data line
Positive
Surge
Negative
Surge
ESD sur ge on data line
di
dt LI/O + LGND
di
dt
di
dt
-LI/O - LGND
di
dt
di
dt
V+=V +V + L + L sur ge > 0
CL TRANSIL F I/O GND
V = -V - L - L sur ge > 0
CL- F I/O GND
di
dt
di
dt
di
dt
di
dt
di
dt
Rd.IpVV BR
TRANSIL +=
Figure 7. ESD behavior: optimized layout and
addition of a capacitance of 100 nF Figure 8. ESD behavior: measurement
conditions (with coupling capacitance)
Unsuitable layout
Optimized layout
TEST BOARD
Vbus
ESD SURGE
OUT
IN
USBLC6-4SC6
Technical information USBLC6-4
6/13 DocID11068 Rev 7
Note: The measurements have been done with the USBLC6-4SC6 in open circuit.
Important:
A good precaution to take is to put the protection device as close as possible to the
disturbance source (generally the connector).
2.4 Crosstalk behavior
2.4.1 Crosstalk phenomenon
Figure 11. Crosstalk phenomenon
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12
or β21) increases when the gap across lines decreases, particularly in silicon dice. In the
above example the expected signal on load R
L2
is α
2
V
G2
, in fact the real voltage at this
point has got an extra value β
21
V
G1
. This part of the V
G1
signal represents the effect of the
crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into
account when the drivers impose fast digital data or high frequency analog signals in the
disturbing line. The perturbed line will be more affected if it works with low voltage signal or
high load impedance (few kΩ).
Figure 9. Remaining voltage after the USBLC6-
4SC6 during positive ESD surge Figure 10. Remaining voltage after the USBLC6-
4SC6 during negative ESD surge
i. LI”L| /HnH
DocID11068 Rev 7 7/13
USBLC6-4 Technical information
13
Figure 12. Analog crosstalk measurements
Figure 12. shows the measurement circuit for the analog application. In usual frequency
range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see
Figure 13.).
Figure 13. Analog crosstalk results
As the USBLC6-4SC6 is designed to protect high speed data lines, it must ensure a good
transmission of operating signals. The frequency response (Figure 5.) gives attenuation
information and shows that the USBLC6-4SC6 is well suitable for data line transmission up
to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz)
frequencies, for instance.
NETWORK ANALYSER
PORT 2
NETWORK ANALYSER
PORT 1
TEST BOARD
Vbus
USBLC6-4SC6
100.0k 1.0M 10.0M 100.0M 1.0G
- 120.00
- 90.00
- 60.00
- 30.00
0.00
dB
f/Hz
100.0k 1.0M 10.0M 100.0M 1.0G
- 120.00
- 90.00
- 60.00
- 30.00
0.00
dB
F (Hz)
l fl UT
Technical information USBLC6-4
8/13 DocID11068 Rev 7
2.5 Application examples
Figure 14. USB 2.0 port application diagram using USBLC6-4SC6
Figure 15. T1/E1/Ethernet protection
HUB-
DOWNSTREAM
TRANSCEIVER
+ 5V
RS
RS
RS
RS
RPD
RPD
RPD
RPD
Protecting
Bus Switch
DEVICE-
UPSTREAM
TRANSCEIVER
+ 3.3V
SW1
RPU
VBUS
D+
D-
GND
VBUS VBUS
VBUS
RX LS/FS +RX LS/FS +
RX LS/FS +
RX LS/FS +
RX HS +RX HS +
RX HS +
RX HS +
TX HS +TX HS +
TX HS +
TX HS +
TX LS/FS +TX LS/FS +
TX LS/FS +
TX LS/FS +
RS
RS
USB
connector
TX LS/FS - TX LS/FS -
TX LS/FS -
TX LS/FS -
RX LS/FS - RX LS/FS -
RX LS/FS -
RX LS/FS -
RX HS - RX HS -
RX HS -
RX HS -
TX HS - TX HS -
TX HS -
TX HS -
GND GND
GND
GND
SW2
DEVICE-
UPSTREAM
TRANSCEIVER
USBLC6-4SC6
USBLC6-2P6
USBLC6-2SC6
+ 3.3V
SW1
RPU
VBUS
D+
D-
GND
RS
RS
USB
connector
SW2
OpenClosed then openHigh Speed HS
OpenClosedFull Speed FS
ClosedOpenLow Speed LS
SW
2
SW
1
Mode
USBLC6-4SC6
+VCC
100nF
DATA
TRANSCEIVER
SMP75-8
SMP75-8
Tx
Rx
' 4 BUS _4
DocID11068 Rev 7 9/13
USBLC6-4 Technical information
13
2.6 PSPICE model
Figure 16. shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes
are defined by the PSPICE parameters given in Figure 17.
Figure 16. PSPICE model
Note: This simulation model is available only for an ambient temperature of 27 °C.
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
VBUS
LIO
io1
RIO
LIO
io2
GND
RIO LIO
RIO
io3
MODEL = Dzener LIO
RIO
LIO
io4
RIO
RGNDLGND
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
VBUS
LIO
io1
RIO
LIO
io2
GND
RIO LIO
RIO
io3
MODEL = Dzener LIO
RIO
LIO
io4
RIO
RGNDLGND
Figure 17. PSPICE parameters Figure 18. USBLC6-4SC6 PCB layout
considerations
0.1u0.1u0.1uTT
0.60.60.6VJ
0.420.630.38RS
0.33330.33330.3333M
1.241.131.62N
100p100p100pISR
3.21p2.27f55.2pIS
2.420.0180.038IKF
1m1m1mIBV
20p2.4p2.4pCJ0
7.35050BV
DzenerDhighDlow
0.1u0.1u0.1uTT
0.60.60.6VJ
0.420.630.38RS
0.33330.33330.3333M
1.241.131.62N
100p100p100pISR
3.21p2.27f55.2pIS
2.420.0180.038IKF
1m1m1mIBV
20p2.4p2.4pCJ0
7.35050BV
DzenerDhighDlow
50mRGND
430pLGND
100mRIO
710pLIO
50mRGND
430pLGND
100mRIO
710pLIO
D+1
C = 100nF
BUS
D-1
GND
USBLC6-4SC6
D+2
D-2
VBUS
1
Product Deslgna Ion Low capacitance Breakdown Volta 2 Number or lines rolecled
Ordering information scheme USBLC6-4
10/13 DocID11068 Rev 7
3 Ordering information scheme
Figure 19. Ordering information scheme
USB LC 6 - 4 SC6
Product Designation
Low capacitance
Breakdown Voltage
Package
6 = 6 Volts
4 = 4 lines
SC6 = SOT23-6L
Number of lines protected
DocID11068 Rev 7 11/13
USBLC6-4 Package information
13
4 Package information
Epoxy meets UL94, V0
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Table 3. SOT23-6L package dimensions
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.45 0.035 0.057
A1 0 0.10 0 0.004
A2 0.90 1.30 0.035 0.051
b 0.35 0.50 0.014 0.02
C 0.09 0.20 0.004 0.008
D 2.80 3.05 0.110 0.120
E 1.50 1.75 0.059 0.069
e 0.95 0.037
H 2.60 3.00 0.102 0.118
L 0.10 0.60 0.004 0.024
θ 10° 0° 10°
Figure 20. SOT23-6L footprint (mm) Figure 21. SOT23-6L marking
A2
A
L
H
c
b
E
D
e
e
A1
q
0.60
0.95
2.30
3.50
1.20
1.10
UL46
Ordering information USBLC6-4
12/13 DocID11068 Rev 7
5 Ordering information
6 Revision history
Table 4. Ordering information
Order code Marking Package Weight Base qty Delivery mode
USBLC6-4SC6 UL46 SOT23-6L 16.7 mg 3000 Tape and reel
Table 5. Document revision history
Date Revision Changes
10-Dec-2004 1 First issue.
28-Feb-2005 2 Minor layout update. No content change.
04-Feb-2008 3 Updated operating junction temperature range in absolute ratings,
page 2. Updated Section 2: Technical information. Updated marking
illustration Figure 21. Reformatted to current standard.
23-Sep-2011 4 Updated leakage current at V
RM
= 5.25 V as specified in USB
standard. Updated marking illustration Figure 21.
13-Oct-2015 5 Updated features in cover page and Table 2.
26-Oct-2015 6 Updated features in cover page.
03-Nov-2015 7 Minor text changes.
DocID11068 Rev 7 13/13
USBLC6-4
13
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