DS28E83 Datasheet by Analog Devices Inc./Maxim Integrated

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D828E83 DeepCover Radiation Resistant _maxim Integrated,"
General Description
The DS28E83 is a radiation-resistant secure authentica-
tor that provides a core set of cryptographic tools derived
from integrated asymmetric (ECC-P256) and symmetric
(SHA-256) secu rity functions. In addition to the security
services provided by the hardware implemented crypto
engines, the device integrates a FIPS-compatible true
random number genera tor (TRNG), 10Kb of secured
OTP, one configurable GPIO, and a unique 64-bit ROM
identification number (ROM ID).
The ECC public/private key capabilities operate from the
NIST defined P-256 curve and include FIPS 186-compliant
ECDSA signature generation and verification to support
a bidirectional asymmetric key authentication model. The
SHA-256 secret key capabilities are compli ant with FIPS
180 and are flexibly used either in conjunc tion with ECDSA
operations or independently for multiple HMAC functions.
The GPIO pin can be operated under command control and
include configurability supporting authenticated and nonau-
thenticated operation, including an ECDSA-based crypto-
robust mode to support secure boot of a host processor.
DeepCover® embedded security solutions cloak sensitive
data under multiple layers of advanced security to provide
the most secure key storage possible. To protect against
device-level security attacks, invasive and noninvasive
countermeasures are implemented including active die
shield, encrypted storage of keys, and algorithmic methods.
Applications
Medical Consumables Secure Authentication
Medical Tools/Accessories Identification and
Calibration
Accessory and Peripheral Secure Authentication
Secure Storage of Cryptographic Keys for Host
Controllers
Secure Boot or Download of Firmware and/or System
Parameters
Ordering Information appears at end of data sheet.DeepCover® is a registered trademark of Maxim Integrated
Products, Inc.
19-100287; Rev 0; 3/18
Benefits and Features
High Radiation Resistance Allows User-
Programmable Manufacturing or Calibration Data
Before Medical Sterilization
Resistant Up to 75kGy (kiloGray) of Radiation
One Time Programmable (OTP) 10kb of User
Data, Keys, and Certificates
ECC-P256 Compute Engine
FIPS 186 ECDSA P256 Signature and Verification
ECDH Key Exchange for Session Key Establishment
ECDSA Authenticated R/W of Configurable Memory
SHA-256 Compute Engine
FIPS 180 MAC for Secure Download/Boot
FIPS 198 HMAC for Bidirectional Authentication
and Optional GPIO Control
SHA-256 OTP (One-Time Pad) Encrypted R/W of
Configurable Memory Through ECDH Established Key
One GPIO Pin with Optional Authentication Control
Open-Drain, 4mA/0.4V
Optional SHA-256 or ECDSA Authenticated On/Off
and State Read
Optional ECDSA Certificate to Set On/Off After
Multiblock Hash for Secure Download
TRNG with NIST SP 800-90B Compliant Entropy
Source with Function to Read Out
Optional Chip Generated Pr/Pu Key Pairs for ECC
Operations or Secrets for SHA256 Functions
Unique and Unalterable Factory Programmed 64-Bit
Identification Number (ROM ID)
Optional Input Data Component to Crypto and Key
Operations
Advanced 1-Wire Protocol Minimizes Interface to
Just Single Contact
Operating Range: 3.3V ±10%, 0°C to +50°C
±8kV HBM ESD Protection of 1-Wire IO Pin
6-Pin, 3mm x 3mm TDFN
Request Security User Guide and Developer Software ›
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
EVALUATION KIT AVAILABLE
Simplified Block Diagram
1-WIRE FUNCTION
CONTROL
AND
COMMAND
64-BIT ROM ID
BUFFER
RNG
10Kb OTP ARRAY
ECC-P256
SHA-256
COMPUTE
CONTROL
IO
DS28E83
C
X
C
EXT
PARASITE
POWER
USER MEMORY
KEYS & CERTIFICATES
AUTHENTICATED
GPIO
PIO
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
6 TDFN
Voltage Range on Any Pin Relative to GND ..........-0.5V to 4.0V
Maximum Current into Any Pin......................... -20mA to +20mA
Operating Temperature Range ................................. 0°C to 50°C
Lead Temperature (soldering, 10s) .................................+300°C
6 TDFN
Package Code T633+2
Outline Number 21-0137
Land Pattern Number 90-0058
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) 55ºC/W
Junction to Case (θJC) 9ºC/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 42ºC/W
Junction to Case (θJC) 9ºC/W
(Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage VPUP (Note 1) 2.97 3.3 3.63 V
1-Wire Pullup Resistance RPUP (Notes 1, 2) 1000 Ω
Input Capacitance CIO (Note 3) 0.1 + CXnF
Capacitor External CX(Note 1) 399.5 470 540.5 nF
Input Load Current ILIO pin at VPUP
Pre-radiation 40 360 μA
Post-radiation 120
High-to-Low Switching Threshold VTL (Notes 4, 5, 6) 0.65 x
VPUP
V
Input Low Voltage VIL (Notes 4, 7) 0.10 x
VPUP
V
Low-to-High Switching Threshold VTH (Notes 4, 5, 8) 0.75 x
VPUP
V
Switching Hysteresis VHY (Notes 4, 5, 9) 0.3 V
Output Low Voltage VOL IOL = 4mA (Note 10) 0.4 V
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package Information
Electrical Characteristics
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
(Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: 1-Wire Interface
Recovery Time
(Notes 1, 11, 12) tREC
Standard speed, Pre-
radiation, RPUP = 1000Ω
25
μs
Directly prior to
reset pulse 100
Standard speed, Post-
radiation, RPUP = 1000Ω
(Note 22)
50
Directly prior to
reset pulse 1500
Overdrive speed, RPUP
= 1000Ω
10
Directly prior to
reset pulse 100
Rising-Edge Hold-off
(Notes 4, 13) tREH Applies to standard speed only 1 μs
Time Slot Duration
(Notes 1, 14) tSLOT
Standard speed
Pre-radiation 85
μs
Post-radiation
(Note 22) 110
Overdrive speed 16
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time
(Note 1) tRSTL
Standard speed 480 640 μs
Overdrive speed 48 80
Reset High Time
(Note 1) tRSTH
Standard speed 480 μs
Overdrive speed 48
Presence Detect High Time tPDH
Standard speed 15 60 μs
Overdrive speed 2 6
Presence Detect Low Time tPDL
Standard speed 60 240 μs
Overdrive speed 8 24
Presence Detect Fall Time
(Notes 4, 15) tFPD
Standard speed 1.25 μs
Overdrive speed 0.15
Presence-Detect Sample Time
(Notes 1, 16) tMSP
Standard speed 65 75 μs
Overdrive speed 7 10
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 1, 17) tW0L
Standard speed 60 120 μs
Overdrive speed 6 15.5
Write-One Low Time
(Notes 1, 17) tW1L
Standard speed 0.25 15 μs
Overdrive speed 0.25 2
IO PIN: 1-Wire READ
Read Low Time
(Notes 1, 18) tRL
Standard speed 0.25 15 - δ μs
Overdrive speed 0.25 2 - δ
Read Sample Time
(Note 1, 18) tMSR
Standard speed tRL + δ 15 μs
Overdrive speed tRL+ δ 2
Electrical Characteristics (continued)
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
(Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
Note 1: System requirement.
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 3: Value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it does
not affect normal communication. Typically, during normal communication, the internal parasite capacitance is effectively ~100pF.
Note 4: Guaranteed by design and/or characterization only. Not production tested.
Note 5: VTL, VTH, and VHY are functions of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive
loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY.
Note 6: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 7: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic-zero level.
Note 8: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 9: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero.
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: Applies to a single device attached to a 1-Wire line.
Note 12: tREC min covers operation at worst-case temperature VPUP, RPUP, CX, tRSTL, tWOL, and tRL. tRECMIN can be significantly
reduced under less extreme conditions. Contact the factory for more information.
Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 14: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GPIO PIN
GPIO Output Low PIOVOL PIOIOL = 4mA (Note 10) 0.4 V
GPIO Input Low PIOVIL -0.3 0.15 x VPUP V
GPIO Master Sample PIOVIH 0.70 x VPUP VPUP + 0.3 V
GPIO Switching Hysteresis PIOVHY 0.3 V
GPIO Leakage Current PIOIL-10 +10 μA
STRONG PULLUP OPERATION
Strong Pullup Current ISPU (Note 19) 11 15 mA
Strong Pullup Voltage VSPU (Note 19) 2.8 V
Read Memory tRM 2 ms
Write Memory tWM 100 ms
Write State tWS 15 ms
Computation Time (HMAC) tCMP 4 ms
Generate ECC Key Pair tGKP 350 ms
Generate ECDSA Signature tGES 80 ms
Verify ECDSA Signature or
Compute ECDH Time tVES 160 ms
TRNG Generation tRNG 40 ms
TRNG On-Demand Check tODC 65 ms
OTP
OTP Write Temperature TOPTW 50 ºC
Data Retention tDR TA = +85°C (Note 21) 10 Years
POWER
Power-Up Time tOSCWUP (Notes 1, 20) 2 ms
Electrical Characteristics (continued)
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
(Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
Note 15: Time from V(IO) = 80% of VPUP and V(IO) = 20% of VPUP at the negative edge on IO at the beginning of the presence detect pulse.
Note 16: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E83 present.
Note 17: ε in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH.
Note 18: δ in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high thresh-
old of the bus master.
Note 19: ISPU is the current drawn from IO during a strong pullup (SPU) operation. The pullup circuit on IO during the SPU operation
should be such that the voltage at IO is greater than or equal to VSPUMIN. A low-impedance bypass of RPUP activated during
the SPU operation is the recommended way to meet this requirement.
Note 20: 1-Wire communication should not take place for at least tOSCWUP after VPUP reaches VPUP min.
Note 21: Data retention is tested in compliance with JESD47G. No elevated gamma radiation level.
Note 22: Post radiation increases leakage current and requires long recovery times as noted.
PIN NAME FUNCTION
1, 5 DNC Do Not Connect
2 IO 1-Wire IO
3 GND Ground
4 PIO General-Purpose IO
6 CEXT Input for External Capacitor
Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer to
Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
Pin Description
Pin Configuration
DNC 1
IO 2
GND 3
6 CEXT
5 DNC
4 PIO
EP*
+
TDFN-EP
(3mm x 3mm)
TOP VIEW
*EP =
EXPOSED
PAD
Electrical Characteristics (continued)
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
Detailed Description
The DS28E83 is the first secure authenticator to integrate
high radiation resistance. It provides a core set of crypto-
graphic tools derived from integrated asymmetric (ECC-
P256) and symmetric (SHA-256) security functions. In
addition to the security services provided by the hardware
implemented crypto engines, the device integrates a FIPS
true random number generator (TRNG), 10Kb of secured
OTP, one pin of configurable GPIO, and a unique 64-bit
ROM identification number (ROM ID).
Function Commands
After a 1-Wire reset/presence cycle and ROM function
command sequence is successful, a command start can be
accepted and then followed by a device function command.
In general, these commands follow the state flow diagram
(Figure 1). Within this diagram, the data transfer is verified
when writing and reading by a CRC of 16-bit type (CRC-16).
The CRC-16 is computed as described in Application Note
27: Understanding and Using Cyclic Redundancy Checks
with Maxim 1-Wire and iButton Products.
Figure 1. Device Function Flow Chart
MASTER Tx
COMMAND START
FROM ROM FUNCTIONS
FLOW CHART
66h
COMMAND
START?
MASTER Tx RELEASE BYTE
MASTER Rx CRC-16 (INVERTED
OF COMMAND START, LENGTH,
COMMAND, AND PARAMETERS)
MASTER Tx
PARAMETER BYTE(S)
SLAVE Rx AAh
RELEASE BYTE?
DELAY WITH STRONG PULLUP
MASTER Rx RESULT BYTE
MASTER Rx CRC-16 (INVERTED
OF LENGTH, RESULT, & DATA)
MASTER
Rx 1S
TO ROM FUNCTIONS
FLOW CHART
Y
N
Y
N
N
Y
MASTER Tx INPUT
LENGTH BYTE
MASTER Tx COMMAND BYTE
MASTER Rx FFh DUMMY BYTE
MASTER Rx OUTPUT
LENGTH BYTE
MASTER Rx DATA BYTE(S)
MASTER Tx
RESET?
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
1 «M
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS28E83 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots that are initiated
on the falling edge of sync pulses from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus can drive it at the
appropriate time. To facilitate this, each device attached
to the 1-Wire bus must have open-drain or three-state
outputs. The 1-Wire port of the DS28E83 is open drain
with an internal circuit equivalent.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E83 supports both a standard
and overdrive communication speed of 11.7kbps (max)
and 62.5kbps (max), respectively. The value of the pullup
resistor primarily depends on the network size and load
conditions. The DS28E83 requires a pullup resistor of
1kΩ (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be
left in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than 16μs
(overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS28E83 through the
1-Wire port is as follows:
Initialization
ROM Function command
Device Function command
Transaction/data
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E83 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling and Timing section.
Figure 2. Hardware Configuration
RPUP
VPUP
IL
100Ω
MOSFET
Rx
Tx
Rx
Tx
BIDIRECTIONAL
OPEN-DRAIN PORT
BUS MASTER
DATA
1-WIRE SLAVE PORT
Rx = RECEIVE
Tx = TRANSMIT
Tx
*SEE NOTE
*NOTE: USE A LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY
PIOX
PIOY
CX
CTL
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
1-Wire Signaling and Timing
The DS28E83 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28E83 can communicate at two speeds: standard
and overdrive. If not explicitly set into the overdrive mode,
the DS28E83 communicates at standard speed. While in
overdrive mode, the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from VILMAX
past the threshold VTH. The time it takes for the voltage
to make this rise is seen in Figure 3 as ε, and its dura-
tion depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached. The voltage
VILMAX is relevant for the DS28E83 when determining a
logical level, not triggering any events.
Figure 3 shows the initialization sequence required to
begin any communication with the DS28E83. A reset pulse
followed by a presence pulse indicates that the DS28E83
is ready to receive data, given the correct ROM and device
function command. If the bus master uses slew-rate con-
trol on the falling edge, it must pull down the line for tRSTL
+ tF to compensate for the edge. A tRSTL duration of 480μs
or longer exits the overdrive mode, returning the device to
standard speed. If the DS28E83 is in overdrive mode and
tRSTL is no longer than 80μs, the device remains in over-
drive mode. If the device is in overdrive mode and tRSTL
is between 80μs and 480μs, the device resets, but the
communication speed is undetermined.
After the bus master has released the line, it goes into
receive mode. Now the 1-Wire bus is pulled to VPUP
through the pullup resistor or, in the case of a special
driver chip, through the active circuitry. When the thresh-
old VTH is crossed, the DS28E83 waits for tPDH and then
transmits a presence pulse by pulling the line low for tPDL.
To detect a presence pulse, the master must test the logi-
cal state of the 1-Wire line at tMSP.
The tRSTH window must be at least the sum of tPDH-
MAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
expired, the DS28E83 is ready for data communication. In
a mixed population network, tRSTH should be extended to
minimum 480μs at standard speed and 48μs at overdrive
speed to accommodate other 1-Wire devices.
Figure 3. Initialization Procedure: Reset and Presence Pulse
tRSTL tPDH tPDL tREC
tRSTH
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tMSP
MASTER Tx RESET PULSE MASTER Rx PRESENCE PULSE
RESISTOR (RPUP)MASTER 1-WIRE SLAVE
tF
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
Read/Write Time Slots
Data communication with the DS28E83 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 4 illustrates the
definitions of the write and read time slots.
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the threshold VTL, the DS28E83 starts its internal timing
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line must
have crossed the VTH threshold before the write-one low
time tW1LMAX is expired. For a write-zero time slot, the
voltage on the data line must stay below the VTH thresh-
old until the write-zero low time tW0LMIN is expired. For
the most reliable communication, the voltage on the data
line should not exceed VILMAX during the entire tW0L or
tW1L window. After the VTH threshold has been crossed,
the DS28E83 needs a recovery time tREC before it is
ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot. The
voltage on the data line must remain below VTL until the
read low time tRL is expired. During the tRL window, when
responding with a 0, the DS28E83 starts pulling the data
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E83 does not hold the data
line low at all, and the voltage starts rising as soon as tRL
is over.
The sum of tRL + δ (rise time) on one side and the internal
timing generator of the DS28E83 on the other side define
the master sampling window (tMSRMIN to tMSRMAX), in
which the master must perform a read from the data line.
For the most reliable communication, tRL should be as
short as permissible, and the master should read close
to but no later than tMSRMAX. After reading from the data
line, the master must wait until tSLOT is expired. This
guarantees sufficient recovery time tREC for the DS28E83
to get ready for the next time slot. Note that tREC speci-
fied herein applies only to a single DS28E83 attached to a
1-Wire line. For multidevice configurations, tREC must be
extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the
special 1-Wire line drivers can be used.
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
.74.
Figure 4. Read/Write Timing Diagrams
tW1L
tSLOT
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
RESISTOR (RPUP)MASTER
tF
RESISTOR (RPUP)MASTER 1-WIRE SLAVE
WRITE-ONE TIME SLOT
tW0L
tSLOT
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
RESISTOR (RPUP)MASTER
tF
WRITE-ZERO TIME SLOT
tREC
tSLOT
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
δ
tF
READ-DATA TIME SLOT
tREC
tRL
tMSR
MASTER SAMPLING
WINDOW
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
1-Wire ROM Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS28E83 supports. All ROM function commands are
8 bits long. For operational details, see the flowchart
description in Figure 5 and Figure 6. A descriptive list of
these ROM function commands follows in the subsequent
sections.
Read ROM[33h]
The Read ROM command allows the bus master to read
the DS28E83’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM[55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E83 on a multidrop bus. Only the DS28E83 that
exactly matches the 64-bit ROM sequence responds
to the subsequent device function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Search ROM[F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
Skip ROM [CCh]
This command can save time in a single-drop bus system
by allowing the bus master to access the device functions
without providing the 64-bit ROM ID. If more than one
slave is present on the bus and, for example, a read com-
mand is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
Resume [A5h]
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the device function commands, similar
to a Skip ROM command. The only way to set the RC bit
is through successfully executing the Match ROM, Search
ROM, or Overdrive-Match ROM command. Once the RC
bit is set, the device can repeatedly be accessed through
the Resume command. Accessing another device on the
bus clears the RC bit, preventing two or more devices from
simultaneously responding to the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the device functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS28E83 into the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28E83 on a multi-
drop bus and to simultaneously set it in overdrive mode.
Only the DS28E83 that exactly matches the 64-bit ROM
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12
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
sequence responds to the subsequent device function
command. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or mul-
tiple devices on the bus.
ROM Command Flow
Figure 5. ROM Function Flow (Part 1)
BUS MASTER Tx
ROM FUNCTION COMMAND
OD
RESET PULSE?
BUS MASTER Tx
RESET PULSE
F0h
SEARCH ROM
COMMAND?
SLAVE Tx
SERIAL NUMBER
(6 BYTES)
SLAVE Tx
FAMILY CODE
(1 BYTE)
Y
N
Y
N
Y
OD = 0
SLAVE Tx
PRESENCE PULSE
33h
READ ROM
COMMAND?
55h
MATCH ROM
COMMAND?
NCCh
SKIP ROM
COMMAND?
N N
RC = 0 RC = 0 RC = 0 RC = 0
MASTER Tx BIT 0 SLAVE Tx BIT 0
SLAVE Tx BIT 0
MASTER Tx BIT 0
SLAVE Tx BIT 1
SLAVE Tx BIT 1
MASTER Tx BIT 0
MASTER Tx BIT 1
Y Y Y Y
Y
SLAVE Tx BIT 63
SLAVE Tx BIT 63
MASTER Tx BIT 63
RC = 1
BIT 63 MATCH?
BIT 1 MATCH?
BIT 0 MATCH?
BIT 0 MATCH?
FROM DEVICE FUNCTIONS
FLOW CHART
BIT 1 MATCH?
MASTER Tx BIT 63
RC = 1
BIT 63 MATCH?
Y Y
N
N
N
N
N
N
SLAVE Tx
CRC BYTE
TO ROM FUNCTION
FLOW PART 2
TO ROM FUNCTION
FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
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13
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
RC MASYER n RESET? MAST RES Wm H 63 MAYCH” WWW C
Figure 6. ROM Function (Part 2)
69h
OVERDRIVE-
MATCH ROM?
TO DEVICE FUNCTIONS
FLOW CHART
N
Y
A5h
RESUME
COMMAND?
3Ch
OVERDRIVE-
SKIP ROM?
NN
RC = 0; OD = 1
MASTER Tx BIT 0
MASTER Tx BIT 1
Y Y Y
N
SLAVE Tx BIT 63
RC = 1
BIT 63 MATCH?
BIT 1 MATCH?
BIT 0 MATCH?
MASTER Tx
RESET?
RC = 1?
MASTER Tx
RESET?
Y
N
Y
N
RC = 0; OD = 1
OD = 0
N
OD = 0
N
OD = 0
N
Y
TO ROM FUNCTION FLOW PART 1
FROM ROM
FUNCTION
FLOW PART 1
FROM ROM FUNCTION
FLOW PART 1
TO ROM FUNCTION FLOW PART 1
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14
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
Improved Network Behavior (Switch-Point
Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-spe-
cific function command to abort. For better performance
in network applications, the DS28E83 uses a 1-Wire front-
end that is less sensitive to noise.
The DS28E83’s 1-Wire front end has the following features:
The falling edge of the presence pulse has a con-
trolled slew rate to reduce ringing. The slew rate con-
trol is specified by tFPD.
There is a hysteresis at the low-to-high switching
threshold VTH. If a negative glitch crosses VTH, but
does not go below VTH - VHY, it is not recognized
(Figure 7, Case A). The hysteresis is effective at any
1-Wire speed.
There is a time window specified by the rising edge
hold-off time tREH during which glitches are ignored,
even if they extend below the VTH - VHY threshold
(Figure 7, Case B, tGL < tREH). Deep voltage drops
or glitches that appear late after crossing the VTH
threshold and extend beyond the tREH window can-
not be filtered out and are taken as the beginning of
a new time slot (Figure 7, Case C, tGL tREH).
Figure 7. Noise Suppression Scheme
VPUP
VTH
VHY
tREH
tGL
tREH
tGL
0V
CASE A CASE B CASE C
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15
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
PART TEMP RANGE PIN-PACKAGE
DS28E83Q+T 0°C to +50°C 6 TDFN-EP (2.5k pcs reel)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
µC
PIOX
PIOY
100kΩ
DS28E83
RPUP
VCC
Q1
IO
*NOTE: USE A Q1 LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY
BIDIRECTIONAL
GND
VCC
GND
OPEN-DRAIN PORT
1kΩ
*PMV65XP
CEXT CX
DS2476
VCC
I2C
PORT
SDA
SCL
VCC
PIOA
PIOB
IO
IO
Rp
PIO IO
Typical Application Circuit
Ordering Information
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16
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 3/18 Initial release
0.1 Added Security User Guide button 1
Revision History
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc.
17
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

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