STM32L4S5xx, 4S7xx, 4S9xx Datasheet by STMicroelectronics

This is information on a product in full production.
April 2018 DS12024 Rev 3 1/277
STM32L4S5xx STM32L4S7xx
STM32L4S9xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 150DMIPS,
up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, AES+HASH
Datasheet- production data
Features
Ultra-low-power with FlexPowerControl
1.71 V to 3.6 V power supply
-40 °C to 85/125 °C temperature range
Batch acquisition mode (BAM)
305 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
33 nA Shutdown mode (5 wakeup pins)
125 nA Standby mode (5 wakeup pins)
420 nA Standby mode with RTC
–2.8 A Stop 2 with RTC
110 A/MHz Run mode
5 µs wakeup from Stop mode
Brownout reset (BOR) in all modes except
shutdown
Interconnect matrix
Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 120 MHz,
MPU, 150 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
Performance benckmark
1.25 DMIPS/MHz (Drystone 2.1)
409.20 Coremark® (3.41 Coremark/MHz
@120 MHz)
Energy benckmark
233 ULPMark™CP score
56.5 ULPMark™PP score
Clock sources
4 to 48 MHz crystal oscillator
32 kHz crystal oscillator for RTC (LSE)
Internal 16 MHz factory-trimmed RC (±1%)
Internal low-power 32 kHz RC (±5%)
Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
Internal 48 MHz with clock recovery
3 PLLs for system clock, USB, audio, ADC
RTC with HW calendar, alarms and calibration
Up to 24 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
Advanced graphics features
Chrom-ART Accelerator™ (DMA2D) for
enhanced graphic content creation
Chrom-GRC™ (GFXMMU) allowing up to
20% of graphic resources optimization
–MIPI
® DSI Host controller with two DSI
lanes running at up to 500 Mbits/s each
LCD-TFT controller
16x timers: 2 x 16-bit advanced motor-control,
2 x 32-bit and 5 x 16-bit general purpose, 2x
16-bit basic, 2x low-power 16-bit timers
(available in Stop mode), 2x watchdogs,
SysTick timer
Up to 136 fast I/Os, most 5 V-tolerant, up to 14
I/Os with independent supply down to 1.08 V
Memories
2-Mbyte Flash, 2 banks read-while-write,
proprietary code readout protection
640 Kbytes of SRAM including 64 Kbytes
with hardware parity check
External memory interface for static
memories supporting SRAM, PSRAM,
NOR, NAND and FRAM memories
2 x OctoSPI memory interface
4x digital filters for sigma delta modulator
Rich analog peripherals (independent supply)
12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
2x 12-bit DAC, low-power sample and hold
2x operational amplifiers with built-in PGA
UFBGA132 (7 × 7)
LQFP144 (20 × 20) UFBGA169 (7 x 7)
LQFP100 (14 x 14) UFBGA144 (10 x 10) WLCSP144
www.st.com
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
2/277 DS12024 Rev 3
2x ultra-low-power comparators
20x communication interfaces
USB OTG 2.0 full-speed, LPM and BCD
2x SAIs (serial audio interface)
–4x I2C FM+(1 Mbit/s), SMBus/PMBus
6x USARTs (ISO 7816, LIN, IrDA, modem)
3x SPIs (5x SPIs with the dual OctoSPI)
CAN (2.0B Active) and SDMMC
14-channel DMA controller
True random number generator
CRC calculation unit, 96-bit unique ID
8- to 14-bit camera interface up to 32 MHz
(black and white) or 10 MHz (color)
Encryption hardware accelerator: AES
(128/256-bit key), HASH (SHA-256)
Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell
(ETM)
Table 1. Device summary
Reference Part numbers
STM32L4S5xx STM32L4S5VI, STM32L4S5QI, STM32L4S5ZI, STM32L4S5AI
STM32L4S7xx STM32L4S7VI, STM32L4S7ZI, STM32L4S7AI
STM32L4S9xx STM32L4S9VI, STM32L4S9ZI, STM32L4S9AI
DS12024 Rev 3 3/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Contents
6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21
3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.11 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.15 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.16 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.17 Chrom-GRC™ (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.18 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.18.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 42
3.18.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 42
3.19 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Contents STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
4/277 DS12024 Rev 3
3.19.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.19.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.19.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.20 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.21 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.22 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.23 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.24 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.25 LCD-TFT controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.26 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.27 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 49
3.28 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.29 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.30 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 51
3.31 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.32 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.32.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.32.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.32.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.32.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 53
3.32.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.32.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.32.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.33 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 55
3.34 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.35 Universal synchronous/asynchronous receiver transmitter (USART) . . . 57
3.36 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 58
3.37 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.38 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.39 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.40 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 60
3.41 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 61
3.42 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DS12024 Rev 3 5/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Contents
6
3.43 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 61
3.44 OctoSPI interface (OctoSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.45 OctoSPI IO manager (OctoSPIIOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.46 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.46.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.46.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 124
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 124
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.10 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.11 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.3.12 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Contents STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
6/277 DS12024 Rev 3
6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.19 Extended interrupt and event controller input (EXTI) characteristics . . 185
6.3.20 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.3.21 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 186
6.3.22 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 199
6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 204
6.3.24 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.3.25 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.3.26 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.3.27 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.3.28 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.3.29 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.3.30 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 215
6.3.31 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.3.32 OctoSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.3.33 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 248
6.3.34 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 249
6.3.35 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 250
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.1 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.2 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
7.4 WLCSP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
7.5 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
7.6 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 272
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
DS12024 Rev 3 7/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx List of tables
9
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18
Table 4. STM32L4S5xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 6. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 10. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 12. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 13. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 14. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 15. STM32L4Sxxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 16. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 17. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 18. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx memory map and
peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 23. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 25. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 26. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . 129
Table 27. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) . . . 130
Table 28. Current consumption in Run and Low-power run modes,
code with data processing running from Flash in single bank, ART disable. . . . . . . . . . . 131
Table 29. Current consumption in Run and Low-power run modes,
code with data processing running from Flash in dual bank, ART disable . . . . . . . . . . . . 132
Table 30. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 134
Table 32. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 33. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 34. Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 138
Table 35. Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 139
Table 36. Current consumption in Stop 2 mode, SRAM3 disabled . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 37. Current consumption in Stop 2 mode, SRAM3 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 141
List of tables STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
8/277 DS12024 Rev 3
Table 38. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 39. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 40. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 41. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 42. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 43. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 44. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 45. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 46. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 47. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 48. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 49. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 50. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 51. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 52. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Table 53. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 54. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 55. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 56. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 57. MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 171
Table 58. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 59. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 60. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 61. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 62. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 63. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 64. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 65. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 66. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 67. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 68. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 69. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 70. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 71. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 72. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 73. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 74. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 75. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 76. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 77. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 78. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 79. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 80. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 81. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 82. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 83. OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 84. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 85. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 86. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 87. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 88. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 89. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
DS12024 Rev 3 9/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx List of tables
9
Table 90. WWDG min/max timeout value at 120 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 91. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 92. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 93. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 94. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 95. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 96. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 97. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 226
Table 98. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 226
Table 99. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 227
Table 100. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 228
Table 101. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 102. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 229
Table 103. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 104. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 231
Table 105. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 106. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 107. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 108. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 109. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 110. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 111. OctoSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 112. OctoSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 113. OctoSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . . . 243
Table 114. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 115. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 116. Dynamics characteristics:
SD / eMMC characteristics at VDD = 2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 117. Dynamics characteristics:
eMMC characteristics at VDD = 1.71 V to 1.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 118. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 119. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 254
Table 120. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 121. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 257
Table 122. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 123. WLCSP - 144 bump, 5.24x 5.24 mm, 0.40 mm pitch, wafer level chip scale,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 124. WLCSP - 144 bump, 5.24x 5.24 mm, 0.40 mm pitch, wafer level chip scale,
recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 125. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 126. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 267
Table 127. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 128. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 129. STM32L4Sxxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 130. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
List of figures STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
10/277 DS12024 Rev 3
List of figures
Figure 1. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx block diagram . . . . . . . . . . . . . . . . . . 16
Figure 2. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. STM32L4S5xx and STM32L4S7xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. STM32L4S9xx power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 8. STM32L4S5xx and STM32L4S7xx UFBGA169 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 9. STM32L4S9xx UFBGA169 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 10. STM32L4S5xx
and STM32L4S7xx LQFP144 pinout(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11. STM32L4S9xx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 12. STM32L4S9xx UFBGA144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 13. STM32L4S9xx WLCSP144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 14. STM32L4S5xx WLCSP144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 15. STM32L4S5xx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 16. STM32L4S5xx and STM32L4S7xx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 17. STM32L4S9xx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 18. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx memory map . . . . . . . . . . . . . . . . . . 113
Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 22. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 23. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 24. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 25. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 26. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 27. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 28. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 29. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 30. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 31. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 32. MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 33. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 34. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 35. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 36. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 37. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 38. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 39. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 40. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 41. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 42. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 43. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 44. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 223
Figure 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 225
Figure 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 227
Figure 47. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 228
DS12024 Rev 3 11/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx List of figures
11
Figure 48. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 49. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 50. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 51. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 52. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 53. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 54. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 55. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 239
Figure 56. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 240
Figure 57. OctoSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 58. OctoSPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 59. OctoSPI Hyperbus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 60. OctoSPI Hyperbus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 61. OctoSPI Hyperbus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 62. OctoSPI Hyperbus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 63. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 64. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 65. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 66. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 67. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 68. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 69. UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 70. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 71. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 72. UFBGA144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 73. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 259
Figure 74. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 75. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 76. WLCSP - 144 bump, 5.24x 5.24 mm, 0.40 mm pitch, wafer level chip scale,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 77. WLCSP - 144 bump, 5.24x 5.24 mm, 0.40 mm pitch, wafer level chip scale,
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 78. WLCSP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 79. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 80. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 81. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 82. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 269
Figure 83. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 84. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
arm
Introduction STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
12/277 DS12024 Rev 3
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L4Sxxx microcontrollers.
This document should be read in conjunction with the STM32L4Sxxx reference manual
(RM0432). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12024 Rev 3 13/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Description
64
2 Description
The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices are an ultra-low-power
microcontrollers family (STM32L4+ Series) based on the high-performance
Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 120 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all
the Arm® single-precision data-processing instructions and all the data types. The Cortex-
M4 core also implements a full set of DSP (digital signal processing) instructions and a
memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (2 Mbytes of Flash memory and 640 Kbytes of
SRAM), a flexible external memory controller (FSMC) for static memories (for devices with
packages of 100 pins and more), two OctoSPI Flash memories interface (available on all
packages) and an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L4Sxxx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and a firewall.
These devices offer a fast 12-bit ADC (5 Msps), two comparators, two operational
amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two
general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven
general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four
digital filters for external sigma delta modulators (DFSDM). In addition, up to 24 capacitive
sensing channels are available.
They also feature standard and advanced communication interfaces such as:
Four I2Cs
Three SPIs
Three USARTs, two UARTs and one low-power UART
Two SAIs
One SDMMC
One CAN
One USB OTG full-speed
Camera interface
DMA2D controller
The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices embed an AES and a
HASH hardware accelerator.
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to
14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows to
backup the RTC and backup the registers.
The STM32L4Sxxx family offers six packages from 100-pin to 169-pin.
Description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
14/277 DS12024 Rev 3
Table 2. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
features and peripheral counts
Peripheral S5VI S7VI S9VI S5QI S5ZI S7ZI S9ZI S5AI S7AI S9AI
Flash memory 2 Mbytes
SRAM
System 640 (192 + 64 + 384) Kbytes
Backup 128 bytes
External memory
controller for static
memories (FSMC)
Yes(1) Yes
OctoSPI 2
Timers
Advanced
control 2 (16-bit)
General
purpose
5 (16-bit)
2 (32-bit)
Basic 2 (16-bit)
Low-power 2 (16-bit)
SysTick timer 1
Watchdog
timers
(independent
, window)
2
Comm.
interface
s
SPI 3
I2C4
USART/UAR
T
UART
LPUART
3
2
1
SAI 2
CAN 1
USB OTG
FS Yes
SDMMC Yes
Digital filters for sigma-
delta modulators Yes (4 filters)
Number of channels 8
RTC Yes
Tamper pins 3
Camera interface Yes
Chrom-ART
AcceleratorYes
Chrom-GRCNo Yes No Yes No Yes
DS12024 Rev 3 15/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Description
64
LCD - TFT No Yes No Yes No Yes
MIPI DSI Host(2) No Yes No Yes No Yes
Random number
generator Yes
AES + HASH Yes
GPIOs
Wakeup pins
Nb of I/Os down to
1.08 V
83
5
0
77
4
0
110
5
14
115
5
14
112
5
11
140
5
14
131
4
13
Capacitive sensing
Number of channels 21 18 24
12-bit ADCs
Number of channels
1
16 14 16 14
12-bit DAC
Number of channels
2
2
Internal voltage
reference buffer Yes
Analog comparator 2
Operational amplifiers 2
Max. CPU frequency 120 MHz
Operating voltage 1.71 to 3.6 V
Operating temperature Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Packages LQFP100 UFBGA
132
LQFP
144
WLCS
P144
LQFP
144
LQFP
144,
UFBGA
144
WLCSP
144
UFBGA169
Bootloader USART
1
USART
2
USART
3SPI1 SPI2 I2C1 I2C2 I2C3 CAN1
USB
through
DFU
1. For the LQFP100 package, only FMC bank1 and NAND bank are available. Bank1 can only support a multiplexed
NOR/PSRAM memory using the NE1 chip select.
2. The DSI Host interface is only available on the STM32L4S9xx sales types.
Table 2. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
features and peripheral counts (continued)
Peripheral S5VI S7VI S9VI S5QI S5ZI S7ZI S9ZI S5AI S7AI S9AI
m: THI—
Description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
16/277 DS12024 Rev 3
Figure 1. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx block diagram
Note: AF: alternate function on I/O pins.
MSv38487V3
USB
OTG
Flash
up to
2 MB
Flexible static memory controller (FSMC):
SRAM, PSRAM, NOR Flash, NAND Flash
GPIO PORT A
AHB/APB2
EXT IT. WKUP
114 AF
PA[15:0]
TIM1 / PWM
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
USART1
RX, TX, CK,CTS,
RTS as AF
SPI1
MOSI, MISO,
SCK, NSS as AF
APB260 M Hz
APB1 30MHz
MOSI, MISO, SCK, NSS as AF
DAC1_OUT
ITF
WWDG
RTC_TS
OSC32_IN
OSC32_OUT
VDDA, VSSA
VDD, VSS, NRST
smcard
irDA
16b
SDIO / MMC
D[7:0]
CMD, CK as AF
VBAT = 1.55 to 3.6 V
SCL, SDA, SMBA as AF
JTAG & SW
ARM Cortex-M4
120 MHz
FPU
NVIC
ETM
MPU
TRACECLK
TRACED[3:0]
DMA2
ART
ACCEL/
CACHE
CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE, INT as AF, FRAM
RNG
DP
DM
ID, VBUS, SOF
FIFO
@ VDDA
BOR
Supply
supervision
PVD, PVM
Int
reset
XTAL 32 kHz
MAN AGT
RTC
FCLK
Standby
interface
IWDG
@VBAT
@ VDD
@VDD
AWU
Reset & clock
control
PCLKx
VDD = 1.71 to 3.6 V
VSS
Voltage
regulator
3.3 to 1.2 V
VDD Power management
@ VDD
RTC_TAMPx
Backup register
AHB bus-matrix
TIM15
2 channels,
1 compl. channel, BKIN as AF
DAC1
DAC2
TIM6
TIM7
TIM2
TIM3
TIM4
TIM5
USART2
USART3
I2C1/SMBUS
D-BUS
APB1 120 MHz (max)
SRAM 192 KB
SRAM 64 KB
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
I-BUS
S-BUS
DMA1
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[15:0]
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
TIM8 / PWM 16b
16b
TIM16 16b
TIM17 16b
3 compl. Channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
1 channel,
1 compl. channel, BKIN as AF
1 channel,
1 compl. channel, BKIN as AF
DAC2_OUT
16b
16b
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
MOSI, MISO, SCK, NSS as AF
RX, TX, CTS, RTS as AF
RX, TX, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
smcard
irDA
smcard
irDA
32b
16b
16b
32b
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
AHB/APB1
OSC_IN
OSC_OUT
HCLKx
XTAL OSC
4- 16MHz
8 analog inputs common to the ADC
VREF+
USAR T 2MBps
Temperature sensor
SAI1
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
SAI2
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
DFSDM
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
Touch sensing controller
8 Groups of 4 channels max as AF
OUT, INN, INP
LPUART1
LPTIM1
LPTIM2
RX, TX, CTS, RTS as AF
IN1, IN2, OUT, ETR as AF
IN1, OUT, ETR as AF
RC HSI
RC LSI
PLL 1&2&3
MSI
Octo SPI1 memory interface IO[7:0],
CLK, NCS. DQS
@ VDDUSB
COMP1
INP, INN, OUT
COMP2
INP, INN, OUT
@ VDDA
RTC_OUT
VDDIO, VDDUSB
FIFO
PHY
AHB1 120 MHz
CRC
OUT, INN, INP
I2C2/SMBUS
I2C3/SMBUS
OpAmp1
SPI3
SPI2
UART5
UART4
APB2 120MHz
AHB2 120 MHz
OpAmp2
@VDDA
AES
Firewall
VREF Buffer
@ VDDA
@ VDD
HASH
Camera Interface
FIFO
HSYNC, VSYNC,
PIXCLK, D[13:0]
CHROM-ART
DMA2D
FIFO
PI[11:0] GPIO PORT I
FIFO
TX, RX as AF
bxCAN1
SCL, SDA, SMBA as AF
I2C4/SMBUS
Octo SPI2 memory interface
FIFO
LCD - TFT
SRAM 384 KB
ITF
ADC1
@ VDDA
DSI Host
DSI
PHI
DSIHOST_D0 P/N
DSIHOST_D1 P/N
DSIHOST_CK P/N
VDD12DSI, VDDSI, VSSDSI
VCAPDSI
DSIHOST_TE
LCD_R[7:0], LCD_G[7:0], LCD_B[7:0],
LCD_HSYNC, LCD_VSYNC, LCD_DE,
LCD_CLK
CHROM-GRC
(GFXMMU)
FIFO
DS12024 Rev 3 17/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional code-
efficiency, delivering the expected high-performance from an Arm® core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions which allows an efficient signal processing
and a complex algorithm execution. Its single precision FPU speeds up the software
development by using metalanguage development tools to avoid saturation.
With its embedded Arm® core, the STM32L4Sxxx family is compatible with all Arm® tools
and software.
Figure 1 shows the general block diagram of the STM32L4Sxxx family devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator that is optimized for the STM32 industry-
standard Arm®Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 150 DMIPS performance at 120 MHz, the accelerator
implements an instruction prefetch queue and a branch cache, which increases the
program’s execution speed from the Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from the Flash memory at a CPU frequency of up to 120 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to eight protected areas, which can
be divided in up into eight subareas each. The protection area sizes range between 32
bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
18/277 DS12024 Rev 3
3.4 Embedded Flash memory
The STM32L4Sxxx devices feature 2 Mbytes of embedded Flash memory which is available
for storing programs and data.
The Flash interface features:
Single or dual bank operating modes
Read-while-write (RWW) in dual bank mode
This feature allows to perform a read operation from one bank while an erase or program
operation is performed to the other bank. The dual bank boot is also supported. Each bank
contains 256 pages of 4 or 8 Kbytes (depending on the read access width).
Flexible protections can be configured thanks to the option bytes:
Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
Level 0: no readout protection
Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Write protection (WRP): the protected area is protected against erasing and
programming:
In single bank mode, four areas can be selected with 8-Kbyte granularity.
In dual bank mode, two areas per bank can be selected with 4-Kbyte granularity.
Table 3. Access status versus readout protection level and execution modes
Area Protection
level
User execution Debug, boot from RAM or boot
from system memory (loader)
Read Write Erase Read Write Erase
Main
memory
1 Yes Yes Yes No No No
2 Yes Yes Yes N/A N/A N/A
System
memory
1 Yes No No Yes No No
2 Yes No No N/A N/A N/A
Option
bytes
1 Yes Yes Yes Yes Yes Yes
2 Yes No No N/A N/A N/A
Backup
registers
1YesYesN/A
(1)
1. Erased when RDP change from Level 1 to Level 0.
No No N/A(1)
2 Yes Yes N/A N/A N/A N/A
SRAM2
1 Yes Yes Yes(1) No No No(1)
2 Yes Yes Yes N/A N/A N/A
DS12024 Rev 3 19/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited:
In single bank mode, two areas can be selected with 128-bit granularity.
In dual bank mode, one area per bank can be selected with 64-bit granularity.
An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or
not when the RDP protection is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
Single error detection and correction
Double error detection
The address of the ECC fail can be read in the ECC register.
3.5 Embedded SRAM
The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices feature 640 Kbytes of
embedded SRAM. This SRAM is split into three blocks:
192 Kbytes mapped at address 0x2000 0000 (SRAM1).
64 Kbytes located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2003 0000 offering a contiguous address
space with the SRAM1.
This block is accessed through the ICode/DCode buses for maximum performance.
These 64 Kbytes SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
384 Kbytes mapped at address 0x2004 0000 - (SRAM3).
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
CORTExl-MA DMM DMAZ DMAZD LCD-TFT SDMMm GFXMMU wnh FPU a bus S‘bus GF pen pen ‘TTTTTTTTF. 0“ BusMamx-S
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
20/277 DS12024 Rev 3
3.6 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, DMA2D,
SDMMC1, LCD-TFT and GFXMMU) and the slaves (Flash memory, RAM, FMC, OctoSPI,
AHB and APB peripherals). It also ensures a seamless and efficient operation even when
several high-speed peripherals work simultaneously.
Figure 2. Multi-AHB bus matrix
3.7 Firewall
These devices embed a firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
MSv38490V1
CORTEX®-M4
with FPU DMA1 DMA2
FSMC
AHB2
peripherals
AHB1
peripherals
SRAM2
SRAM1
FLASH
2 MB
ACCEL
S-bus
D-bus
ICode
DCode
OCTOSPI2
DMA2D
I-bus
BusMatrix-S
LCD-TFT SDMMC1 GFXMMU
SRAM3
GFXMMU
OCTOSPI1
DS12024 Rev 3 21/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
The main features of the firewall are the following:
Three segments can be protected and defined thanks to the firewall registers:
Code segment (located in Flash or SRAM1 if defined as executable protected
area)
Non-volatile data segment (located in Flash)
Volatile data segment (located in SRAM1)
The start address and the length of each segment are configurable:
Code segment: up to 2048 Kbytes with granularity of 256 bytes
Non-volatile data segment: up to 2048 Kbytes with granularity of 256 bytes
Volatile data segment: up to 192 Kbytes of SRAM1 with a granularity of 64 bytes
Specific mechanism implemented to open the firewall to get access to the protected
areas (call gate entry sequence)
Volatile data segment can be shared or not with the non-protected code
Volatile data segment can be executed or not depending on the firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
3.8 Boot modes
At startup, a BOOT0 pin and an nBOOT1 option bit are used to select one of three boot
options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on
the value of a user option bit to free the GPIO pad if needed.
A Flash empty-check mechanism is implemented to force the boot from system Flash if the
first Flash memory location is not programmed and if the boot selection is configured to boot
from main Flash.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, CAN or USB OTG FS in device mode through the DFU (device
firmware upgrade).
3.9 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
22/277 DS12024 Rev 3
3.10 Power supply management
3.10.1 Power supply schemes
The STM32L4x devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several
independent supplies can be provided for specific peripherals:
VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage and should preferably be connected to VDD when
these peripherals are not used.
VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage and should preferably be
connected to VDD when the USB is not used.
VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage
level is independent from the VDD voltage and should preferably be connected to VDD
when PG[15:2] are not used.
VDDDSI is an independent DSI power supply dedicated for is used to supply the DSI
regulator and MIPI D-PHY. This supply must be connected to the global VDD.
VCAPDSI pin is the output of DSI regulator (1.2 V) which must be connected externally
to VDD12DSI.
VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin.
VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V VREF+ must be equal to VDDA.
When VDDA 2 V VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
–V
REF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
–V
REF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disable (refer to datasheet for
DS12024 Rev 3 23/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
packages pinout description).
VREF- must always be equal to VSSA.
An embedded linear voltage-regulator is used to supply the internal digital power VCORE.
VCORE is the power supply for digital peripherals, SRAM1, SRAM2 and SRAM3. The Flash
is supplied by VCORE and VDD.
Figure 3. STM32L4S5xx and STM32L4S7xx power supply overview
MSv38489V1
VDDA domain
Backup domain
Standby circuitry
(Wakeup logic,
IWDG)
Voltage regulator
Low voltage detector
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
I/O ring
VCORE domain
Temp. sensor
Reset block
3 x PLL, HSI, MSI
Flash memory
USB transceivers
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
Core
SRAM1
SRAM2
SRAM3
Digital
peripherals
2 x D/A converters
3 x A/D converters
2 x comparators
2 x operational amplifiers
Voltage reference buffer
]‘¥
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
24/277 DS12024 Rev 3
Figure 4. STM32L4S9xx power supply overview
During power-up and power-down phases, the following power sequence requirements
must be respected:
When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB and VLCD) must
remain below VDD +300 mV.
When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ; this allows external
decoupling capacitors to be discharged with different time constants during the power-
down transient phase.
MSv38488V1
VDDA domain
Backup domain
2 x D/A converters
3 x A/D converters
Standby circuitry
(Wakeup logic,
IWDG)
Voltage regulator
Low voltage detector
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
2 x comparators
2 x operational amplifiers
Voltage reference buffer
I/O ring
VCORE domain
Temp. sensor
Reset block
3 x PLL, HSI, MSI
Flash memory
DSI PHY
VDD12DSI
USB transceivers
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
DSI
voltage regulator
VCAPDSI
VDDDSI
Core
SRAM1
SRAM2
SRAM3
Digital
peripherals
,,,,,,,4, , ,,,,,,,,,,,,,,,,,,,,,,,,,
DS12024 Rev 3 25/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
Figure 5. Power-up/down sequence
1. VDDX refers to any power supply among VDDA, VDDIO2, VDDUSB and VLCD.
3.10.2 Power supply supervisor
The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices have an integrated ultra-
low-power Brownout reset (BOR) active in all modes (except for Shutdown mode). The BOR
ensures proper operation of the devices after power-on and during power-down. The
devices remain in reset mode when the monitored supply voltage VDD is below a specified
threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD
is higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor which compares the
independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure
that the peripheral is in its functional supply range.
3.10.3 Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 64 Kbytes SRAM2 in standby with RAM2 retention.
Both regulators are in power-down while they are in standby and Shutdown modes: the
regulator output is in high impedance, and the kernel circuitry is powered down thus
inducing zero consumption.
MSv47490V1
0.3
1
VBOR0
3.6
Operating modePower-on Power-down time
V
VDDX(1)
VDD
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
26/277 DS12024 Rev 3
The ultra-low-power STM32L4Sxxx devices support dynamic voltage scaling to optimize its
power consumption in Run mode. The voltage from the main regulator that supplies the
logic (VCORE) can be adjusted according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
Range 1 boost mode with the CPU running at up to 120 MHz.
Range 1 normal mode with the CPU running at up to 80 MHz.
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by the HSI16.
Note: The USB and DSIHOST can only be used when the main regulator is in range1 boost mode.
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
DS12024 Rev 3 27/277
3.10.4 Low-power modes
The ultra-low-power STM32L4Sxxx devices support seven low-power modes to achieve the best compromise between low-power
consumption, short startup time, available peripherals and available wake-up sources. Table 4 shows the related STM32L4Sxxx
modes overview.
Table 4. STM32L4S5xx modes overview
Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source
Run
Range 1
Yes ON (3) ON Any
All
N/A
Range2 All except
OTG_FS, RNG, LCD-TFT
LPRun LPR Yes ON(3) ON Any except
PLL
All except
OTG_FS, RNG, LCD-TFT N/A
Sleep
Range 1
No ON(3) ON(4) Any
All
Any interrupt or event
Range 2 All except
OTG_FS, RNG, LCD-TFT
LPSleep LPR No ON(3) ON(4) Any
except PLL All except OTG_FS, RNG, LCD-TFT Any interrupt or event
Stop 0
Range 1
No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DACx (x=1,2)
OPAMPx (x=1,2)
USARTx (x=1...5)(5)
LPUART1(5)
I2Cx (x=1...4)(6)
LPTIMx (x=1,2)
***
All other peripherals are frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(5)
LPUART1(5)
I2Cx (x=1...4)(6)
LPTIMx (x=1,2)
OTG_FS(7)
Range 2
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
28/277 DS12024 Rev 3
Stop 1 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DACx (x=1,2)
OPAMPx (x=1,2)
USARTx (x=1...5)(5)
LPUART1(5)
I2Cx (x=1...4)(6)
LPTIMx (x=1,2)
***
All other peripherals are frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(5)
LPUART1(5)
I2Cx (x=1...4)(6)
LPTIMx (x=1,2)
OTG_FS(7)
Stop 2 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(6)
LPUART1(5)
LPTIM1
***
All other peripherals are frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(6)
LPUART1(5)
LPTIM1
Standby
LPR
Powered
Off Off
SRAM2 ON
LSE
LSI
BOR, RTC, IWDG
***
All other peripherals are powered off
***
I/O configuration can be floating, pull-
up or pull-down
Reset pin
5 I/Os (WKUPx)(8)
BOR, RTC, IWDG
OFF Powered
Off
Shutdown OFF Powered
Off Off Powered
Off LSE
RTC
***
All other peripherals are powered off
***
I/O configuration can be floating, pull-
up or pull-down(9)
Reset pin
5 I/Os (WKUPx)(8)
RTC
Table 4. STM32L4S5xx modes overview (continued)
Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
DS12024 Rev 3 29/277
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
4. The SRAM1, SRAM2 and SRAM3 clocks can be gated on or off independently.
5. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
6. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
7. OTG_FS wakeup by resume from suspend and attach detection protocol event.
8. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
9. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
30/277 DS12024 Rev 3
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
Low-power sleep mode
This mode is entered from the Low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Low-
power run mode.
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode
to detect their wake-up condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL,
the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The Brownout reset (BOR) always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1, SRAM3 and register contents are lost except for
registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be
DS12024 Rev 3 31/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
retained in Standby mode, supplied by the low-power regulator (standby with RAM2
retention mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the
HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
32/277 DS12024 Rev 3
Table 5. Functionalities depending on the working mode(1)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
CPU Y - Y - - --------
Flash memory
(2 Mbytes) O(2) O(2) O(2) O(2) ---------
SRAM1
(192 Kbytes) YY
(3) YY
(3) Y-Y------
SRAM2 (64 Kbytes) Y Y(3) YY
(3) Y-Y-O
(4) ----
SRAM3
(384 Kbytes) YY
(3) YY
(3) Y-Y
(3) ------
FSMC OOOO---------
OctoSPIs O O O O - --------
Backup Registers Y Y Y Y Y -Y-Y-Y-Y
Brownout reset
(BOR) YYYYYYYYYY- --
Programmable
Voltage Detector
(PVD)
OOOOOOOO- ----
Peripheral Voltage
Monitor (PVMx;
x=1,2,3,4)
OOOOO
OOO- ----
DMA OOOO-
--------
DMA2D OOOO-
--------
High speed internal
(HSI16) OOOO
(5) -(5) ------
Oscillator HSI48 O O - - - --------
High speed external
(HSE) OOOO-
--------
Low speed internal
(LSI) OOOOO
-O-O----
Low speed external
(LSE) OOOOO
-O-O-O-O
Multi speed internal
(MSI) OOOO-
--------
Clock security
system (CSS) OOOO-
--------
DS12024 Rev 3 33/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
Clock security
system on LSE OOOOO
OOOOO- --
RTC / Auto wakeup O O O O O OOOOOOOO
Number of RTC
Tamper pins 33333O3O3O3O3
Camera interface O O O O - --------
LCD-TFT O O - - - --------
GFXMMU OOOO-
--------
DSIHOST O O - - - --------
USB OTG FS O(8) O(8) ---O- ------
USARTx
(x=1,2,3,4,5) OOOOO
(6) O(6) -------
Low-power UART
(LPUART) OOOOO
(6) O(6) O(6) O(6) -----
I2Cx (x=1,2,4) O O O O O(7) O(7) -------
I2C3 OOOOO
(7) O(7) O(7) O(7) -----
SPIx (x=1,2,3) O O O O - --------
CAN(x=1,2) O O O O - --------
SDMMC1 OOOO-
--------
SAIx (x=1,2) O O O O - --------
DFSDM1 OOOO-
--------
ADC OOOO-
--------
DACx (x=1,2) O O O O O --------
VREFBUF O O O O O --------
OPAMPx (x=1,2) O O O O O --------
COMPx (x=1,2) OOOOO
OOO- ----
Temperature sensor O O O O - --------
Timers (TIMx) O O O O - --------
Low-power timer 1
(LPTIM1) OOOOO
OOO- ----
Low-power timer 2
(LPTIM2) OOOOO
O- ------
Table 5. Functionalities depending on the working mode(1) (continued)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
34/277 DS12024 Rev 3
Independent
watchdog (IWDG) OOOOO
OOOOO- --
Window watchdog
(WWDG) OOOO-
--------
SysTick timer O O O O - --------
Touch sensing
controller (TSC) OOOO-
--------
Random number
generator (RNG) O(8) O(8) -----------
AES hardware
accelerator OOOO-
--------
HASH hardware
accelerator OOOO-
--------
CRC calculation
unit OOOO-
--------
GPIOs OOOOOOOO(9)
5
pins
(10)
(11)
5
pins
(10)
-
1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off. In Stop 2 mode, the content of SRAM3 is preserved or not depending on the
RRSTP bit in PWR_CR1 register.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
Table 5. Functionalities depending on the working mode(1) (continued)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
DS12024 Rev 3 35/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.10.5 Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.10.6 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when there is no external battery and when an external
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
3.11 Interconnect matrix
Several peripherals have direct connections between them, which allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep, Low-
power run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 6 for more details.
Table 6. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
peripherals interconnect matrix
Interconnect source Interconnect
destination Interconnect action
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
TIMx
TIMx Timers synchronization or chaining Y Y Y Y - -
ADC
DACx
DFSDM1
Conversion triggers Y Y Y Y - -
DMA Memory to memory transfer trigger Y Y Y Y - -
COMPx Comparator output blanking Y Y Y Y - -
COMPx
TIM1, 8
TIM2, 3
Timer input channel, trigger, break from
analog signals comparison YYYY - -
LPTIMERx Low-power timer triggered by analog
signals comparison YYYYYY
(1)
ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - -
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
36/277 DS12024 Rev 3
RTC
TIM16 Timer input channel from RTC events Y Y Y Y - -
LPTIMERx Low-power timer triggered by RTC alarms
or tampers YYYYYY
(1)
All clocks sources (internal
and external)
TIM2
TIM15, 16, 17
Clock source used as input channel for
RC measurement and trimming YYYY - -
USB TIM2 Timer triggered by USB SOF Y Y - - - -
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
TIM1,8
TIM15,16,17 Timer break Y Y Y Y - -
GPIO
TIMx External trigger Y Y Y Y - -
LPTIMERx External trigger Y Y Y Y Y Y
(1)
ADC
DACx
DFSDM1
Conversion external trigger Y Y Y Y - -
1. LPTIM1 only.
Table 6. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
peripherals interconnect matrix (continued)
Interconnect source Interconnect
destination Interconnect action
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
DS12024 Rev 3 37/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.12 Clocks and startup
The clock controller (see Figure 6) distributes the clocks coming from the different
oscillators to the core and to the peripherals. It also manages the clock gating for low-power
modes and ensures the clock robustness. It features:
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: clock sources can be changed safely on the fly in Run mode
through a configuration register.
Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals or memory.
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 120 MHz.
RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can
be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be
output on the MCO.
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.
Three PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the USB/SDMMC/RNG, the two SAIs, LCD-
TFT and DSI-HOST. When using DSI-HOST peripheral, the high-speed external crystal
(HSE) must be available.
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
38/277 DS12024 Rev 3
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
Clock-out capability:
MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application
LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 120 MHz.
svscLK
DS12024 Rev 3 39/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
Figure 6. Clock tree
MSv38434V7
SYSCLK
MCO
LSCO
PLL
SAI2_EXTCLK
48 MHz clock to USB, RNG
to ADC
to IWDG
to RTC
to PWR
HCLK
to AHB bus, core, memory and DMA
FCLK Cortex free running clock
to Cortex system timer
to APB1 peripherals
to APB2 peripherals
PCLK1
PCLK2
to SAI1
to SAI2
LSE
HSI16
SYSCLK to USARTx
X=2..5
to LPUART1
to I2Cx
x=1,2,3,4
to LPTIMx
x=1,2
SAI1_EXTCLK
to TIMx
x=2..7
OSC32_OUT
OSC32_IN
MSI
HSI16
HSE
HSE
MSI
HSI16
MSI
SYSCLK
LSE OSC
32.768 kHz /32
AHB PRESC
/ 1,2,..512
/ 8
APB1 PRESC
/ 1,2,4,8,16
x1 or x2
HSI16
SYSCLK
LSI
LSE
HSI16
APB2 PRESC
/ 1,2,4,8,16
to TIMx
x=1,8,15,16,17
x1 or x2
to
USART1
LSE
HSI16
SYSCLK
/ P
/ Q
/ R
PLLSAI1
/ P
/ Q
/ R
/ M
MSI RC
100 kHz – 48 MHz
HSI RC
16 MHz
HSE OSC
4-48 MHz
Clock
detector
OSC_OUT
OSC_IN
/ 1→16
LSI RC 32 kHz
Clock
source
control
PLLSAI3CLK
PLL48M1CLK
PLLCLK
PLLSAI1CLK
PLL48M2CLK
PLLADC1CLK
PLLSAI2CLK
PLLLCDCLK
HSI16
HSI16
HSI16
PLLSAI2
/ P
/ Q
/ R
HSI16
LSI
LSE
HSE
SYSCLK
PLLCLK
HSI48
MSI
OCTOSPI clock
MSI
MSI
HSI16
DFSDM
audio clock
SDMMC clock
PLLSAI2DIVR LTDC clock
DSI
PLL DSI - PHY
HSE
PLLDSICLK
62.5 MHz
20 MHz
< 62.5 MHz
DSIHOST
byte lane clock
DSIHOST
rxclkesc clock
/ M
/ M
RC 48 MHz
CRS clock
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
40/277 DS12024 Rev 3
3.13 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.14 Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 14 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports:
14 independently configurable channels (requests)
Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data size
Support for circular buffer management
3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
Memory-to-memory transfer
Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
Access to Flash, SRAM, APB and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536
Table 7. DMA implementation
DMA features DMA1 DMA2
Number of regular channels 7 7
DS12024 Rev 3 41/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.15 DMA request router (DMAMux)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
3.16 Chrom-ART Accelerator™ (DMA2D)
Chrom-ART Accelerator™ (DMA2D) is a graphic accelerator that offers an advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4 bpp color mode up to 32 bpp
direct color. It embeds a dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.17 Chrom-GRC™ (GFXMMU)
The Chrom-GRC™ (GFXMMU) is a graphical oriented memory management unit aimed to:
Optimize memory usage according to the display shape
Manage packing/unpacking for 24 bpp frame buffers
The Chrom-GRC™ features:
Fully programmable display shape to physically store only the visible pixel
Up to four virtual buffers
Each virtual buffer have 4096 bytes per line and 1024 lines
Each virtual buffer can be physically mapped to any system memory
24 bpp packing unit to store unpacked 24bpp data in a packed 24 bpp
Packing/un-packing management per buffer
Interrupt in case of buffer overflow (1 per buffer)
Interrupt in case of memory transfer error
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
42/277 DS12024 Rev 3
3.18 Interrupts and events
3.18.1 Nested vectored interrupt controller (NVIC)
The STM32L4S5xx, STM32L4S7xx and STM32L4S9xxdevices embed a nested vectored
interrupt controller which is able to manage 16 priority levels, and to handle up to 95
maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4.
The NVIC benefits are the following:
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.18.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 36 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can
be connected to the 16 external interrupt lines.
DS12024 Rev 3 43/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.19 Analog-to-digital converter (ADC)
The device embeds a successive approximation analog-to-digital converters with the
following features:
12-bit native resolution, with built-in calibration
5.33 Msps maximum conversion rate with full resolution
Down to 18.75 ns sampling time
Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
Up to 16 external channels
5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1 and
DAC2 outputs
One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
Single-ended and differential mode inputs
Low-power design
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
Dual clock domain architecture: ADC speed independent from CPU frequency
Highly versatile digital interface
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
Results stored into a data register or in RAM with DMA controller support
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.19.1 Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channels which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
44/277 DS12024 Rev 3
3.19.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
3.19.3 VBAT battery voltage monitoring
This embedded hardware enables the application to measure the VBAT battery voltage using
the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than the VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third of the VBAT voltage.
3.20 Digital to analog converter (DAC)
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
Up to two DAC output channels
8-bit or 12-bit output mode
Buffer offset calibration (factory and user trimming)
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Table 8. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75A8 - 0x1FFF 75A9
TS_CAL2
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75CA - 0x1FFF 75CB
Table 9. Internal voltage reference calibration values
Calibration value name Description Memory address
VREFINT
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75AA - 0x1FFF 75AB
DS12024 Rev 3 45/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.21 Voltage reference buffer (VREFBUF)
The STM32L4Sxxx devices embed a voltage reference buffer which can be used as voltage
reference for ADC, DACs and also as voltage reference for external components through
the VREF+ pin.
The internal voltage reference buffer supports two voltages:
2.048 V
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 7. Voltage reference buffer
3.22 Comparators (COMP)
The STM32L4Sxxx devices embed two rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) and
with selectable output polarity.
The reference voltage can be one of the following:
External I/O
DAC output channels
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can also be combined into a window comparator.
MSv40197V1
VREFBUF
Low frequency
cut-off capacitor
DAC, ADC
Bandgap +
VDDA
-
100 nF
VREF+
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
46/277 DS12024 Rev 3
3.23 Operational amplifier (OPAMP)
The STM32L4Sxxx devices embed two operational amplifiers with external or internal
follower routing and PGA capability.
The operational amplifier features:
Low input bias current
Low offset voltage
Low-power mode
Rail-to-rail input
3.24 Touch sensing controller (TSC)
The touch sensing controller provides a simple solution to add capacitive sensing
functionality to any application. A capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (glass, plastic
or other). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
Proven and robust surface charge transfer acquisition principle
Supports up to 24 capacitive sensing channels
Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
Spread spectrum feature to improve system robustness in noisy environments
Full hardware management of the charge transfer acquisition sequence
Programmable charge transfer frequency
Programmable sampling capacitor I/O pin
Programmable channel I/O pin
Programmable max count value to avoid long acquisition when a channel is faulty
Dedicated end of acquisition and max count error flags with interrupt capability
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
DS12024 Rev 3 47/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.25 LCD-TFT controller (LTDC)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (red, green, blue) and
delivers all signals to interface directly to a broad range of LCD and TFT panels with the
following features:
Two displays layers with dedicated FIFO (64 x 32-bit)
Color look-up table (CLUT) up to 256 colors (256 x 24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to four programmable interrupt events
3.26 DSI Host (DSIHOST)
The DSI Host is a dedicated IP that interfaces with the MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
The interfaces are as follows:
LTDC interface:
Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI)
Used to transmit information in full bandwidth in the Adapted Command Mode
(DBI) through a custom mode
APB slave interface:
Allows the transmission of generic information in Command mode, and follows a
proprietary register interface
Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode
Video mode pattern generator:
Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
48/277 DS12024 Rev 3
The DSI Host main features are:
Compliant with MIPI® Alliance standards
Interface with MIPI® D-PHY
Supports all commands defined in the MIPI® Alliance specification for DCS:
Transmission of all Command mode packets through the APB interface
Transmission of commands in low-power and high-speed during Video Mode
Supports up to two D-PHY data lanes
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for end of transmission packet (EoTp)
Fault recovery schemes
Configurable selection of system interfaces:
AMBA APB for control and optional support for generic and DCS commands
Video Mode interface through LTDC
Adapted command mode interface through LTDC
Independently programmable virtual channel ID in
Video mode
Adapted command mode
APB Slave
Video Mode interfaces features:
LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2 and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
Programmable polarity of all LTDC interface signals
Maximum resolution is limited by available DSI physical link bandwidth:
Number of lanes: 2
Maximum speed per lane: 500 Mbps
Adapted interface features:
Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2 and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
Video mode pattern generator:
Vertical and horizontal color bar generation without LTDC stimuli
BER pattern without LTDC stimuli
DS12024 Rev 3 49/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.27 Digital filter for sigma-delta modulators (DFSDM)
The STM32L4Sxxx devices embed one DFSDM with four digital filters modules and eight
external input serial channels (transceivers) or alternately eight internal parallel inputs
support.
The DFSDM peripheral is dedicated to interface the external  modulators to the
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on  modulators inputs).
The DFSDM can also interface the PDM (pulse density modulation) microphones and
perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional
parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into
DFSDM).
The DFSDM transceivers support several serial interface formats (to support various 
modulators) and the DFSDM digital filter modules perform digital processing according to
the user’s selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
8 multiplexed input digital serial channels:
Configurable SPI interface to connect various SD modulator(s)
Configurable Manchester coded 1 wire interface support
PDM (pulse density modulation) microphone input support
Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
Clock output for SD modulator(s): 0..20 MHz
Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):
Internal sources: device memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–Sinc
x filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
Integrator: oversampling ratio (1..256)
Up to 24-bit output data resolution, signed output data format
Automatic data offset correction (offset stored in register by user)
Continuous or single conversion
Start-of-conversion triggered by:
Software trigger
Internal timers
External events
Start-of-conversion synchronously with first digital filter module (DFSDM0)
Analog watchdog feature:
Low value and high-value data threshold registers
Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
Input from final output data or from selected input digital serial channels
Continuous monitoring independently from standard conversion
Short circuit detector to detect saturated analog input values (bottom and top range):
Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
Monitoring continuously each input serial channel
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
50/277 DS12024 Rev 3
Break signal generation on analog watchdog event or on short circuit detector event
Extremes detector:
Storage of minimum and maximum values of final conversion data
Refreshed by software
DMA capability to read the final conversion data
Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
“Regular” or “injected” conversions:
“Regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
“Injected” conversions for precise timing and with high conversion priority
3.28 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.29 Digital camera interface (DCMI)
The STM32L4Sxxx devices embed a camera interface that can connect with any camera
modules and CMOS sensors through an 8-bit to 14-bit parallel interface in order to receive
video data.
The camera interface can sustain a data transfer rate up to 54 Mbytes/s at 54 MHz. It
features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication of 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image.
DS12024 Rev 3 51/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.30 Advanced encryption standard hardware accelerator (AES)
The STM32L4Sxxx devices embed an AES hardware accelerator that can be used both to
encipher and to decipher data using an AES algorithm.
The AES peripheral supports:
Encryption/decryption using AES Rijndael block cipher algorithm
NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x
32-bit registers)
Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois
Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher
Message Authentication Code mode (CMAC) supported
Key scheduler
Key derivation for decryption
128-bit data block processing
128-bit, 256-bit key length
1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer
Register access supporting 32-bit data width only
One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected, GCM mode or
CMAC mode
Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data
Suspend a message if another message with a higher priority needs to be processed.
3.31 HASH hardware accelerator (HASH)
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-
1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the
HMAC (keyed-hash message authentication code) algorithm suitable for a variety of
applications.
It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256
algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for
messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating
messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,
SHA-224, SHA-256 or MD5 hash function twice.
3.32 Timers and watchdogs
The STM32L4Sxxx devices include two advanced control timers, up to nine general-
purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick
timer.
The Table 10 below compares the features of the advanced control, general-purpose and
basic timers.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
52/277 DS12024 Rev 3
3.32.1 Advanced-control timer (TIM1, TIM8)
The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.32.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
Table 10. Timer feature comparison
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Advanced
control TIM1, TIM8 16-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 3
General-
purpose TIM2, TIM5 32-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 No
General-
purpose TIM3, TIM4 16-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 No
General-
purpose TIM15 16-bit Up
Any integer
between 1
and 65536
Yes 2 1
General-
purpose TIM16, TIM17 16-bit Up
Any integer
between 1
and 65536
Yes 1 1
Basic TIM6, TIM7 16-bit Up
Any integer
between 1
and 65536
Yes 0 No
DS12024 Rev 3 53/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.32.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32L4Sxxx devices (see Table 10 for differences).
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time
base.
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
TIM15 has two channels and one complementary channel
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.32.3 Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
3.32.4 Low-power timer (LPTIM1 and LPTIM2)
The STM32L4Sxxx devices embed two low-power timers. These timers have an
independent clock and are running in Stop mode if they are clocked by LSE, LSI or an
external clock. They are able to wakeup the system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
54/277 DS12024 Rev 3
This low-power timer supports the following features:
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
Internal clock sources: LSE, LSI, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
Programmable digital glitch filter
Encoder mode (LPTIM1 only).
3.32.5 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.32.6 System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.32.7 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
DS12024 Rev 3 55/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.33 Real-time clock (RTC) and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
Two programmable alarms
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
Three anti-tamper detection pins with programmable filter
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from standby or Shutdown mode.
The RTC clock sources can be:
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
3.34 Inter-integrated circuit interface (I2C)
The device embeds four I2C. Refer to Table 11: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
56/277 DS12024 Rev 3
The I2C peripheral supports:
I2C-bus specification and user manual rev. 5 compatibility:
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
System management bus (SMBus) specification rev 2.0 compatibility:
Hardware PEC (packet error checking) generation and verification with ACK
control
Address resolution protocol (ARP) support
SMBus alert
Power system management protocol (PMBusTM) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 6: Clock tree
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 11. I2C implementation
I2C features(1)
1. X: supported
I2C1 I2C2 I2C3 I2C4
Standard-mode (up to 100 kbit/s) X X X X
Fast-mode (up to 400 kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
Wakeup from Stop 0, Stop 1 mode on address match X X X X
Wakeup from Stop 2 mode on address match - - X -
DS12024 Rev 3 57/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.35 Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32L4Sxxx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable. They are able to communicate at speeds of up to
10 Mbit/s.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The
wake up events from Stop mode are programmable and can be:
Start bit detection
Any received data frame
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 12. USART/UART/LPUART features
USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1
Hardware flow control for modem XXXXX X
Continuous communication using DMA XXXXX X
Multiprocessor communication XXXXX X
Synchronous mode X X X - - -
Smartcard mode X X X - - -
Single-wire half-duplex communication XXXXX X
IrDA SIR ENDEC block XXXXX -
LIN mode XXXXX -
Dual clock domain XXXXX X
Wakeup from Stop 0 / Stop 1 modes XXXXX X
Wakeup from Stop 2 mode ----- X
Receiver timeout interrupt XXXXX -
Modbus communication XXXXX -
Auto baud rate detection X (4 modes) -
Driver enable XXXXX X
LPUART/USART data length 7, 8 and 9 bits
1. X = supported.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
58/277 DS12024 Rev 3
3.36 Low-power universal asynchronous receiver transmitter
(LPUART)
The STM32L4Sxxx devices embed one low-power UART. The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half-
duplex single-wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
Start bit detection
Any received data frame
A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.37 Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and
simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size
is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode
and hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.38 Serial audio interfaces (SAI)
The STM32L4Sxxx devices embed two SAI. Refer to Table 13: SAI implementation for the
features implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
8-word integrated FIFOs for each audio sub-block.
Synchronous or asynchronous mode between the audio sub-blocks.
Master or slave configuration independent for both audio sub-blocks.
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
DS12024 Rev 3 59/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
Number of bits by frame may be configurable.
Frame synchronization active level configurable (offset, bit length, level).
First active bit position in the slot is configurable.
LSB first or MSB first for data transfer.
Mute mode.
Stereo/Mono audio frame capability.
Communication clock strobing edge configurable (SCK).
Error flags with associated interrupts if enabled respectively.
Overrun and underrun detection.
Anticipated frame synchronization signal detection in slave mode.
Late frame synchronization signal detection in slave mode.
Codec not ready for the AC’97 mode in reception.
Interruption sources when enabled:
–Errors.
FIFO requests.
DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
3.39 Controller area network (CAN)
The CAN is compliant with the 2.0A and B (active) specifications with a bit rate of up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive
FIFOS with three stages and 28 shared scalable filter banks (all of them can be used even if
one CAN is used). 256 bytes of SRAM are allocated.
Table 13. SAI implementation
SAI features(1)
1. X: supported
SAI1 SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X
Mute mode X X
Stereo/Mono audio frame capability. X X
16 slots X X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X
FIFO size X (8 Word) X (8 Word)
SPDIF X X
PDM X -
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
60/277 DS12024 Rev 3
The CAN peripheral supports:
CAN protocol version 2.0 A, B Active
Bit rates of up to 1 Mbit/s
Transmission
Three transmit mailboxes
Configurable transmit priority
Reception
Two receive FIFOs with three stages
Scalable filter banks: 28 filter banks
Identifier list feature
Configurable FIFO overrun
Time-triggered communication option
Disable automatic retransmission mode
16-bit free running timer
Time Stamp sent in last two data bytes
Management
Maskable interrupts
Software-efficient mailbox mapping at a unique address space
3.40 Secure digital input/output and MultiMediaCards Interface
(SDMMC)
The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.
The SDMMC features include the following:
Full compliance with MultiMediaCard System Specification Version 4.51. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
Full compatibility with previous versions of MultiMediaCards (backward compatibility)
Full compliance with SD Memory Card Specifications Version 4.1. (SDR104
SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode
not supported)
Full compliance with SDIO Card Specification Version 4.0: card support for two different
databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to
maximum allowed IO speed, SPI mode and UHS-II mode not supported)
Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO
speed)
Data and command output enable signals to control external bidirectional drivers.
DS12024 Rev 3 61/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
3.41 Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume.
The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the
internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator
(LSE).This allows to use the USB device without external high speed crystal (HSE).
The major features are:
Combined Rx and Tx FIFO size of 1.25 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
One bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
Eight host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
Software configurable to OTG 1.3 and OTG 2.0 modes of operation
OTG 2.0 Supports ADP (Attach detection Protocol)
USB 2.0 LPM (Link Power Management) support
Battery charging specification revision 1.2 support
Internal FS OTG PHY support
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected.
The synchronization for this oscillator can also be taken from the USB data stream itself
(SOF signalization) which allows crystal less operation.
3.42 Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.43 Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) includes two memory controllers:
The NOR/PSRAM memory controller
The NAND/memory controller
This memory controller is also named flexible memory controller (FMC).
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
62/277 DS12024 Rev 3
The main features of the FMC controller are the following:
Interface with static-memory mapped devices including:
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (four memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Ferroelectric RAM (FRAM)
8-,16- bit data bus width
Independent chip select control for each memory bank
Independent configuration for each memory bank
Write FIFO
The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.
3.44 OctoSPI interface (OctoSPI)
The OctoSPI is a specialized communication interface targetting single, dual, quad or octal
SPI memories. It can operate in any of the three following modes:
Indirect mode: all the operations are performed using the OctoSPI registers
Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation
The OctoSPI supports two frame formats:
Classical frame format with command, address, alternate byte, dummy cycles and data
phase over 1, 2, 4 or 8 data pins
HyperbusTM frame format
The OctoSPI offers the following features:
Three functional modes: indirect, status-polling, and memory-mapped
Read and write support in memory-mapped mode
Supports for single, dual, quad and octal communication
Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel.
SDR and DTR support
Data strobe support
Fully programmable opcode for both indirect and memory mapped mode
Fully programmable frame format for both indirect and memory mapped mode
DS12024 Rev 3 63/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview
64
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
Instruction phase
Address phase
Alternate bytes phase
Dummy cycles phase
Data phase
HyperbusTM support
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses are allowed
DMA channel for indirect mode operations
Timeout management
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
3.45 OctoSPI IO manager (OctoSPIIOM)
The OctoSPI IO Manager is a low level interface allowing:
Efficient OctoSPI pin assignment with a full IO Matrix (before alternate function map)
Multiplexing single/dual/quad/octal SPI interface over the same bus
The OctoSPI IO Manager has the following features:
Support up to two single/dual/quad/octal SPI Interface
Support up to eight ports for pin assignment
Fully programmable IO matrix for pin assignment by function (data/control/clock)
Muxer for Single/Dual/Quad/Octal SPI interface multiplexing over the same bus
3.46 Development support
3.46.1 Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
64/277 DS12024 Rev 3
3.46.2 Embedded Trace Macrocell™
The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L4Sxxx devices through a small number of ETM pins to an external hardware trace
port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DS12024 Rev 3 65/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description
117
4 Pinouts and pin description
Figure 8. STM32L4S5xx and STM32L4S7xx UFBGA169 ballout(1)
1. The above figure shows the package top view.
Figure 9. STM32L4S9xx UFBGA169 ballout(1)
1. The above figure shows the package top view.
MSv38036V4
PI10 PH2 VDD PE0 PB4 PB3 VSS VDD PA15 PA14 PA13 PI0
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
PI9 PI7 VSS PE1 PB5 VDDIO2 PG9 PD0 PI6 PI2 PI1 PH15
VDD VSS PI11 PB8 PB6 PD1 PH13 PI3 PI8 VSS
PE4 PE3 PE2 PI4 PH9 PH7
PC13 VBAT PE6 PI5 PH6 VDDUSB
PC14-
OSC32_IN VSS PC6 VDDIO2
PC15-
OSC32_OUT VDD PG6 PC7
PH0-OSC_IN VSS NRST PG7 PD15 VSS
PH1-
OSC_OUT PC0 PC1 PG4 PG3 PG2
PC3 VSSA/VREF- PA0 PA5 PB0 PE14 PH4 PD14 PD12 PD11
VREF+ VDDA PA4 PA 7 PB1 PF14 PE7 PE13 PH5 PD9 PD8 VDD
OPAMP1_VI
NM PA3 VSS PA6 PF11 PF13 VSS PE12 PH10 PH11 VSS PB15
PB9 PB7 PG10 PD5
PG15 PD4
PD2 PC10
PD3 PC11PG11 PD6PE5 PH3-BOOT0
PF2 PA9PC12 PA10PG12 PD7PF1 PF0
PF3 PC8PA8 PC9PG14 PG13PF4 PF5
PB11 PG8PG1 PE10PF10 PC4
PE15 PG5PG0 PE9PC2 PC5
PF15 PE8
PH14
13
PH12
VDD
PA12
PA11
VSS
VDD
VDD
PD10
PD13
VSS
PB14
NPA2 PA1 VDD OPAMP2_VI
NM PB2 PF12 VDD PE11 PB10 PH8 VDD PB12 PB13
flflflflflflflflflflflflflflflflflflflflflflflflflfl me a: E N: n = e: m = m: N = m: 2. UN. 5 NN. n. a. S. S. 5 mm. 3 a: E N: 5 z. m: S. E E. m: a: E N: 2. 3.. van vss vunusa ma mz PAH mo FAQ w P09 P09 P07 P06 vumoz vss P68 P67 was was PGA was PG? LQFP144 PD15 PDM qu vss PD13 PDQ PDH PDm PDQ was P315 FEM P313 P312 EEEEEEEEEEEE PFSE <3 pfae=""><4 pps-e15="" vsse="" 16="" vnde="" 11="" we="" e="" 13="" w="" e="" 19="" pra="" e="" 20="" prg="" e="" 21="" pf“)="" e="" 22="" we="" 03::="" w="" e="" 23="" phivosc="" oui="" e="" 24="" nrsi="" e="" 25="" m="" e="" 26="" pm="" e="" 27="" m="" e="" 23="" m="" e="" 29="" vssa="" e="" 30="" vrefr="" e="" 31="" mare="" e="" 32="" vdda="" e="" 33="" no="" e="" 34="" pm="" e="" 35="" w="" e="" as="" a="" :="" s="" g="" mm="" 3&8;="" 3.="" ressqqs="" u="" 00)="" h="" mm)="" u="" :3="" u="" emu="" h.="" emu="" h.="" 3mm="" h.="" 2mm="" h.="" ~me="" h.="" :01="" h="" mm)="" h="" $1="" u="" en="" u="" in="" h.="" gm="" h.="" 0mm="" h.="" min="" h.="" «eu="" h.="" eu="" h.="" 00=""> H. mm> H. NE H. in H. Nmm H. .ma H. emu U 81 U an U in H. 9E H. m H. mm) MSv45224V1
Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
66/277 DS12024 Rev 3
Figure 10. STM32L4S5xx
and STM32L4S7xx LQFP144 pinout(1)
1. The above figure shows the package top view.
MSv45224V1
LQFP144
21
23
24
25
26
27
28
29
30
31
32
33
34
35
36
20
22
15
17
19
13
14
16
18
PF9
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PA1
PA2
PF8
PF10
PF5
VDD
PF7
PF3
PF4
VSS
PF6
88
86
85
84
83
82
81
80
79
78
77
76
75
74
73
89
87
94
92
90
97
96
95
93
91
135
133
132
131
130
129
128
127
126
125
124
123
122
121
136
134
141
139
137
144
143
142
140
138
47
49
50
51
52
53
54
55
56
57
58
59
60
61
72
46
48
41
43
45
38
39
40
42
44
VSS
VDD
PA6
PC5
PF11
PA4
PA5
PB0
VSS
PF14
PA7
PC4
VDD
PF15
PE7
PB1
PB2
PG0
PE8
VSS
PF12
PF13
PG1
PE9
VDD
PG3
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PG4
PG2
VSS
PG7
PG5
PC7
PC6
VDDIO2
PG8
PG6
VDD
VSS
PB9
PB7
PB3
PE1
PE0
PB6
VDDIO2
PG13
PB8
PH3-BOOT0
VSS
PG12
PG9
PB5
PB4
PG11
PD7
VDD
PG15
PG14
PG10
PD6
120 VSS
119 PD5
118 PD4
117 PD3
116 PD2
115 PD1
114 PD0
113 PC12
112 PC11
111 PC10
110 PA15
109 PA14
108 VDD
104
107
106
105
103
PA12
VSS
VDDUSB
PA13
PA11
99
98
PC9
PC8
101
100
PA9
PA8
102 PA10
68
69
70
71
PE15
PB10
VSS
PB11
64
65
66
67
PE11
PE12
PE14
PE13
62
63
VDD
PE10
37
PA3
12
11
6
8
10
4
5
7
9
PF2
PF1
VBAT
PC14-OSC32_IN
PF0
PE5
PE6
PC13
PC15-OSC32_OUT
3PE4
2PE3
1PE2
flflflflflflflflflflflfl m E m E m E vss E van E we E m E me E PHu-osc w E Pm-osc om E may E won E m E P02 E P03 E VSSANREF- E vwsr. E VDDA E m E pm E m E m E vss E van E ‘3 m ‘5 ‘5 w m ‘9 2o 2‘ 22 2a 24 25 2a 27 2a 29 so 3‘ 32 33 34 35 as J m D :a me D 39 w a 4a m D m we D 22 new a 4: p22 D 44 pm D 45 pm a 46 vss D 47 van D 454 Pm D 29 pm a 5n pm D 5‘ P641 D 52 my D 53 m g 54 P58 D 55 pa D 56 vss D 57 van D 53 Pan D 59 PEH D so P212 D 61 LQFP144 DDDDDDDDDD Pea pm Fee 965 Pea pea m2 Pom Pom van vss Pms pm2 mu pmo Pas ma VDD12D5\ nsx cm nsx cw vssnsx nsx um nsx D0? chstu vnunsx Msm225w
DS12024 Rev 3 67/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description
117
Figure 11. STM32L4S9xx LQFP144 pinout(1)
1. The above figure shows the package top view.
MSv45225V1
LQFP144
21
23
24
25
26
27
28
29
30
31
32
33
34
35
36
20
22
15
17
19
13
14
16
18
PH0-OSC_IN
NRST
PC0
PC1
PC2
PC3
VSSA/VREF-
VREF+
VDDA
PA0
PA1
PA2
PA3
VSS
VDD
PF10
PH1-OSC_OUT
PF5
VDD
PF7
PF3
PF4
VSS
PF6
88
86
85
84
83
82
81
80
79
78
77
76
75
74
73
89
87
94
92
90
97
96
95
93
91
135
133
132
131
130
129
128
127
126
125
124
123
122
121
136
134
141
139
137
144
143
142
140
138
47
49
50
51
52
53
54
55
56
57
58
59
60
61
72
46
48
41
43
45
38
39
40
42
44
PA5
PA6
PB0
PF11
PF13
PA7
PC4
PF12
PF15
PE7
PB1
PB2
PG0
PE8
VDD
VSS
VDD
PE9
PE10
PE12
PF14
PG1
VSS
PE11
PB15
VDD
PD13
PD12
PD11
PD10
PD9
PD8
VDD12DSI
DSI_CKN
DSI_CKP
VSSDSI
DSI_D0N
DSI_D0P
VCAPDSI
VDDDSI
PD14
VSS
PG5
PG3
PD15
PG8
PG7
PG6
PG4
PG2
VDD
VSS
PB9
PB7
PB3
PE1
PE0
PB6
VDDIO2
PG11
PB8
PH3-BOOT0
VSS
PG10
PD6
PB5
PB4
PG9
VDD
PD5
PG15
PG12
PD7
VSS
120 PD4
119 PD3
118 PD2
117 PD1
116 PD0
115 PC12
114 PC11
113 PC10
112 PA15
111 PA14
110 VDD
109 VSS
108 VDDUSB
104
107
106
105
103
PA10
PA13
PA12
PA11
PA9
99
98
PC7
PC6
101
100
PC9
PC8
102 PA8
68
69
70
71
VDD
PB12
PB14
PB13
64
65
66
67
PE15
PB10
VSS
PB11
62
63
PE13
PE14
37
PA4
12
11
6
8
10
4
5
7
9
PF2
PF1
VBAT
PC14-OSC32_IN
PF0
PE5
PE6
PC13
PC15-OSC32_OUT
3PE4
2PE3
1PE2
Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
68/277 DS12024 Rev 3
Figure 12. STM32L4S9xx UFBGA144 ballout(1)
1. The above figure shows the package top view.
Figure 13. STM32L4S9xx WLCSP144 ballout(1)
1. The above figure shows the package top view
MSv38491V4
VSS PE0 PB9 PH3-BOOT0 PB4 VDDIO2 VSS PD3 PC11 PA14 VDD VSS
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
VBAT VDD PE3 PB8 PB5 PB3 PD6 PD1 PA15 PA13 PA12 PA11
VSS PE5 PE2 PE1 PB7 PD0 PC10 PA10 VDDUSB PC9
PC14-
OSC32_IN
PC15-
OSC32_OUT PE4 PA9 PA8 PC6
PF2 PF1 PF0 PC8 PG7 VDDIO2
PF8 PF6 VSS PG2
VDD VSS PD11 VDD
PH0-OSC_IN PH1-
OSC_OUT PC0 PD8 DSI_D1P DSI_D1N
NRST PC1 PC3 VSSDSI DSI_CKP DSI_CKN
VSSA/VREF- VREF+ PA0 PA4 PC5 PE15 PB11 PB14 DSI_D0P DSI_D0N
VDDA PA1 PA2 PA5 PC4 VSS PG0 PE10 PB10 PB12 VDD VCAPDSI
VSS VDD PA3 PA7 PB0 VDD PF14 PG1 PE12 PE14 PB13 VSS
PE6 PB6 PG12 PD5
PG13 PD4
PD2 PC12
PG8 PC7PG10 PD7PC13 PF3
PF4 PG4PG5 PG6PG9 PG3PF5 PF7
PF10 PD13PD14 PD12PE7 PD15PF9 PF12
PD10 PD9PF15 PE11PC2 PB2
PE13 PB15PF13 PE9PA6 PB1
PF11 PE8
MSv42219V2
VSS PA14 PA15 PD0 PD5 VDD PG12 VDDIO2 PB7 PE0 PE1 VSS
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
VDD VDDUSB PA13 PC12 PD2 VSS PG10 PB3 PH3-BOOT0 PB9 PE2 VDD
PA11 PA12 PC10 PC11 PD1 PB4 PB6 PB8 PE3 PE4
PC8 PC9 PA8 PE6 PC13 VSS
PG7 PG8 VDDIO2 VBAT PC14-
OSC32_IN
PC15-
OSC32_OUT
PD15 PG2 PF3 PF2
VSS VDD VSS VDD
PD9 PD8 PB14 PF10 NRST PH0-OSC_IN
DSI_D1N DSI_D1P PB15 PC3 PC0 PH1-
OSC_OUT
DSI_CKP DSI_CKN VSSDSI PE15 PE10 PC5 PA 4 PA 1 VSSA/VREF- PC1
DSI_D0P DSI_D0N VCAPDSI PB10 PE11 PG1 VDD PF12 PC4 PA3 VREF+ VDDA
VDD VDD VSS PB11 PE12 PE7 PF13 VSS PB0 PA7 VDD VSS
PA9 PA10 PD3 PD7
PD4 PG9
PG13 PE5
PB5 PF0PC7 PD6PC6 PG6
PD14 PF4PF1 PF5PG4 PG5PD12 PG3
PD13 PF6PA 5 PF7PE9 PF14PD11 PD10
PA2 PC2PE8 PB1PB13 PE14
PA6 PA0PF15 PB2PB12 PE13
PG0 PF11
DS12024 Rev 3 69/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description
117
Figure 14. STM32L4S5xx WLCSP144 ballout(1)
1. The above figure shows the package top view.
NC (not-connected) balls must be left unconnected.
Figure 15. STM32L4S5xx UFBGA132 ballout(1)
1. The above figure shows the package top view.
MSv43442V1
VSS PA14 PA15 PD0 PD5 VDD PG12 VDDIO2 PB7 PE0 PE1 VSS
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
VDD VDDUSB PA13 PC12 PD2 VSS PG10 PB3 PH3-BOOT0 PB9 PE2 VDD
PA11 PA12 PC10 PC11 PD1 PB4 PB6 PB8 PE3 PE4
PC8 PC9 PA8 PE6 PC13 VSS
PG7 PG8 VDDIO2 VBAT PC14-
OSC32_IN
PC15-
OSC32_OUT
PD15 PG2 PF3 PF2
VSS VDD VSS VDD
PD9 PD8 PB14 PF10 NRST PH0-OSC_IN
NC NC PB15 PC3 PC0 PH1-
OSC_OUT
NC NC VSS PE15 PE10 PC5 PA4 PA1 VSSA/VREF- PC1
NC NC NC PB10 PE11 PG1 VDD PF12 PC4 PA3 VREF+ VDDA
VDD VDD VSS PB11 PE12 PE7 PF13 VSS PB0 PA7 VDD VSS
PA9 PA10 PD3 PD7
PD4 PG9
PG13 PE5
PB5 PF0PC7 PD6PC6 PG6
PD14 PF4PF1 PF5PG4 PG5PD12 PG3
PD13 PF6PA 5 PF7PE9 PF14PD11 PD10
PA2 PC2PE8 PB1PB13 PE14
PA6 PA0PF15 PB2PB12 PE13
PG0 PF11
MSv38035V5
PH3-BOOT0
4
PB7
VDD
PF2
PA5
PA4
PA6
OPAMP2_VI
NM
PF3
PF5
PG6
PG7
PE3 PE1 PB8 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12
123 56789101112
A
B
C
D
E
F
G
H
J
K
L
M
PE4 PE2 PB9 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11
PC13 PE5 PE0 PB5 PD2 PD0 PC11 VDDUSB PA10
PC14-
OSC32_IN PE6 VSS PA9 PA8 PC9
PC15-
OSC32_OUT VBAT VSS PC8 PC7 PC6
PH0-OSC_IN VSS VSS VSS
PH1-
OSC_OUT VDD VDD VDD
PC0 NRST VDD PD15 PD14 PD13
VSSA/VREF- PC1 PC2 PD12 PD11 PD10
PG15 PC3 PA2 PC4 PD9 PD8 PB15 PB14 PB13
VREF+ PA0 PA3 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12
VDDA PA1 OPAMP1_VI
NM PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15
PG14 PG13
PF1 PF0 PG12 PG10 PG9
VSS VSS
VDD VDDIO2
PF4
PG11
PA7 PG8 PF12 PF14 PF15
PF11 PF13
PG5
PG3
PG1
PG0
PG4
PG2
p22 I 1 m I 2 pa I 3 Pa I A pas I 5 van I 5 P013 I 7 P01403632 W I 3 P0503032 OUT I 9 vss I 10 van I 11 moss W I 12 mesa am I 13 LQFP100 ~st I 14 m I 15 Pm I 16 PC? I 17 PCS I 18 VSSA I 19 VREF I 20 mg. I 21 mm I 22 m I 23 pm I 24 m I 25
Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
70/277 DS12024 Rev 3
Figure 16. STM32L4S5xx and STM32L4S7xx LQFP100 pinout(1)
1. The above figure shows the package top view.
MSv38494V1
LQFP100
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
11
4
6
8
1
2
3
5
7
VSS
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PA1
PA2
PC15-OSC32_OUT
VDD
PE5
VBAT
PC14-OSC32_IN
PE2
PE3
PE4
PE6
PC13
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
67
65
72
70
68
75
74
73
71
69
91
89
88
87
86
85
84
83
82
81
80
79
78
77
76
92
90
97
95
93
100
99
98
96
94
35
37
38
39
40
41
42
43
44
45
46
47
48
49
50
34
36
29
31
33
26
27
28
30
32
PA3
VSS
PA5
PC4
PB2
VDD
PA4
PC5
PE8
PE11
PA6
PA7
PE9
PE12
PE15
PB0
PB1
PE13
PB10
VSS
PE7
PE10
PE14
PB11
VDD
PC9
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA8
PC8
PA13
PA11
PA9
VDD
VSS
VDDUSB
PA12
PA10
VDD
VSS
PB9
PB7
PB3
PE1
PE0
PB6
PD6
PD3
PB8
PH3-BOOT0
PD5
PD2
PC12
PB5
PB4
PD1
PC11
PA15
PD7
PD4
PD0
PC10
PA14
m I 1 m I 2 pa I 3 pas I A pas I 5 van I 5 P013 I 7 Pcwosc32 w I 3 P0503032 OUT I 9 vss I 10 mm I 11 moss w I 12 whose am I 13 LQFP100 ~st I 14 m I 15 PC1 I 16 PC? I 17 PCS I 18 VSSANREF I 19 VDDANREH I 20
DS12024 Rev 3 71/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description
117
Figure 17. STM32L4S9xx LQFP100 pinout(1)
1. The above figure shows the package top view.
06Y9
/4)3
















966
3+26&B,1
3+26&B287
1567
3&
3&
3&
3&
966$95()
9''$95()
966
3$
3$
3$
3$
3&26&B287
9''
3(
9%$7
3&26&B,1
3(
3(
3(
3(
3&











































































3%
3%
3$
3&
3%
9''
3$
3%
3(
3(
3$
3$
3(
3(
3(
3%
3%
3(
3%
966
3(
3(
3(
3%
9''
3&
3&
3&
3'
3'
'6,B'1
'6,B'3
9&$3'6,
3'
3'
3'
9'''6,
'6,B&.3
966'6,
3%
3$
3&
3$
3$
3$
9'''6,
'6,B&.1
9''86%
3$
3$
9''
966
3%
3%
3%
9''
966
3%
3'
3'
3%
3+%227
3'
3'
3&
3%
3%
3'
3&
3$
3'
3'
3'
3&
3$
Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
72/277 DS12024 Rev 3
Table 14. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
_f (1) I/O, Fm+ capable
_l (2) I/O, with LCD function supplied by VLCD
_u (3) I/O, with USB function supplied by VDDUSB
_a (4) I/O, with Analog switch function supplied by VDDA
_s (5) I/O supplied only by VDDIO2
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Pin
functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 15 are: FT_f, FT_fa, FT_fl, FT_fla.
2. The related I/O structures in Table 15 are: FT_l, FT_fl, FT_lu.
3. The related I/O structures in Table 15 are: FT_u, FT_lu.
4. The related I/O structures in Table 15 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.
5. The related I/O structures in Table 15 are: FT_s, FT_fs.
DS12024 Rev 3 73/277
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description
117
Table 15. STM32L4Sxxx pin definitions
Pin Number
Pin
name
(functio
n after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32L4S5xx
STM32L4S7xx STM32L4S9xx
LQFP100
BGA132
LQFP144
WLCSP144
UFBGA169
LQFP100
LQFP144
UFBGA144
WLCSP144
UFBGA169
- - - - M11 - - - - M11 VSS S - - - -
----C1-- - -C1VDDS -- - -
- - - - C3 - - - - C3 PI11 I/O FT - OCTOSPIM_P2_IO0
, EVENTOUT -
1 B2 1 B11 D3 1 1 C3 B11 D3 PE2 I/O FT_l -
TRACECK,
TIM3_ETR,
SAI1_CK1,
TSC_G7_IO1,
LCD_R0, FMC_A23,
SAI1_MCLK_A,
EVENTOUT
-
2 A1 2 C11 D2 2 2 B3 C11 D2 PE3 I/O FT_l -
TRACED0,
TIM3_CH1,
OCTOSPIM_P1_DQ
S, TSC_G7_IO2,
LCD_R1, FMC_A19,
SAI1_SD_B,
EVENTOUT
-
3 B1 3 C12 D1 3 3 D3 C12 D1 PE4 I/O FT -
TRACED1,
TIM3_CH2,
SAI1_D2,
DFSDM1_DATIN3,
TSC_G7_IO3,
DCMI_D4, LCD_B0,
FMC_A20,
SAI1_FS_A,
EVENTOUT
-
4 C2 4 D9 E4 4 4 C2 D9 E4 PE5 I/O FT -
TRACED2,
TIM3_CH3,
SAI1_CK2,
DFSDM1_CKIN3,
TSC_G7_IO4,
DCMI_D6, LCD_G0,
FMC_A21,
SAI1_SCK_A,
EVENTOUT
-
5 D2 5 D10 E3 5 5 D4 D10 E3 PE6 I/O FT -
TRACED3,
TIM3_CH4,
SAI1_D1, DCMI_D7,
LCD_G1, FMC_A22,
SAI1_SD_A,
EVENTOUT
RTC_TAMP3,
WKUP3
6 E2 6 E10 E2 6 6 B1 E10 E2 VBAT S - - - -