SN65HVD10/11/12-EP Datasheet by Texas Instruments

*FTEMS INSTRUMENTS U HHHB |:||:H:H:|
1
FEATURES APPLICATIONS
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
D PACKAGE
(TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007www.ti.com
3.3 V RS-485 TRANSCEIVERS
Digital Motor ControlControlled Baseline
Utility Meters– One Assembly/Test Site
Chassis-to-Chassis Interconnects– One Fabrication Site
Electronic Security StationsExtended Temperature Performance of Up to
Industrial Process Control– 40 °C to 125 °C and – 55 °C to 125 °C
Building AutomationEnhanced Diminishing Manufacturing Sources
Point-of-Sale (POS) Terminals and Networks(DMS) SupportEnhanced Product-Change NotificationQualification Pedigree
(1)
Operates With a 3.3 V SupplyBus-Pin ESD Protection Exceeds 16 kV HBM1/8 Unit-Load Option Available (Up to 256Nodes on the Bus)Optional Driver Output Transition Times forSignaling Rates of 1 Mbps, 10 Mbps, and25 Mbps
(2)
Meets or Exceeds the Requirements of ANSI
The SN65HVD10, SN65HVD11, and SN65HVD12TIA/EIA-485-A
combine a 3-state differential line driver anddifferential input line receiver that operate with aBus-Pin Short Circuit Protection From – 7 V to
single 3.3 V power supply. They are designed for12 V
balanced transmission lines and meet or exceedLow-Current Standby Mode . . . 1 μA (Typ)
ANSI standard TIA/EIA-485-A and ISO 8482:1993.Open-Circuit, Idle-Bus, and Shorted-Bus
These differential bus transceivers are monolithicintegrated circuits designed for bidirectional dataFailsafe Receiver
communication on multipoint bus-transmission lines.Thermal Shutdown Protection
The drivers and receivers have active-high andGlitch-Free Power-Up and Power-Down
active-low enables respectively, that can be externallyProtection for Hot-Plugging Applications
connected together to function as direction control.Low device standby supply current can be achievedSN75176 Footprint
by disabling the driver and the receiver.(1) Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over an
The driver differential outputs and receiver differentialextended temperature range. This includes, but is not limited
inputs connect internally to form a differentialto, Highly Accelerated Stress Test (HAST) or biased 85/85,temperature cycle, autoclave or unbiased HAST,
input/output (I/O) bus port that is designed to offerelectromigration, bond intermetallic life, and mold compound
minimum loading to the bus whenever the driver islife. Such qualification testing should not be viewed as
disabled or V
CC
= 0. These parts feature wide positivejustifying use of this component beyond specified
and negative common-mode voltage ranges, makingperformance and environmental limits.
them suitable for party-line applications.(2) The signaling rate of a line is the number of voltagetransitions that are made per second expressed in the unitsbps (bits per second).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2004 – 2007, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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LOGIC DIAGRAM
(POSITIVE LOGIC)
1
2
3
46
7
A
B
R
RE
DE
D
ABSOLUTE MAXIMUM RATINGS
(1) (2)
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
PACKAGESIGNALING RATE UNIT LOADS T
A
SOIC MARKINGSOIC
(2) (3)
25 Mbps 1/2 SN65HVD10QDREP V10QEP– 40 °C to 125 °C10 Mbps 1/8 SN65HVD11QDREP
(4)
V11QEP
1 Mbps 1/8 – 40 °C to 85 °C SN65HVD12IDREP V12IEP
25 Mbps 1/2 – 55 °C to 125 °C SN65HVD10MDREP V10MEP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(3) The D package is taped and reeled as indicated by the R suffix to the part number (i.e., SN65HVD10QDREP).(4) Product Preview
over operating free-air temperature range (unless otherwise noted)
SN65HVD10-EP
SN65HVD11-EP
SN65HVD12-EP
Supply voltage range, V
CC
– 0.3 V to 6 V
Voltage range at A or B 9 V to 14 V
Input voltage range at D, DE, R, or RE 0.5 V to V
CC
+ 0.5 V
Voltage input range, transient pulse, A and B, through 100 (see Figure 11 ) 50 V to 50 V
A, B, and GND 16 kVHuman body model
(3)
Electrostatic discharge All pins 4 kV
Charged-device model
(4)
All pins Charge 1 kV
See Package DissipationContinuous total power dissipation
Rating Table
Storage temperature range, T
stg
– 65 °C to 150 °C
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
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PACKAGE DISSIPATION RATINGS
0.000001
0.00001
0.0001
0.001
1/Tj in Deg K
1/tf in Hours
1205C (282 kHours, 32.1 Years)
1505C (9.7 kHours, 1.1 Years)
1405C (27.8 kHours, 3.2 Years)
1305C (86 kHours, 9.8 Years)
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
T
A
25 °C DERATING FACTOR
(1)
T
A
= 70 °C T
A
= 85 °C T
A
= 125 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING POWER RATING
D
(2)
597 mW 4.97 mW/ °C 373 mW 298 mW 100 mW
D
(3)
990 mW 8.26 mW/ °C 620 mW 496 mW 165 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
Figure 1. Estimated Device Life Based Kirkendall Voiding Failure Mode
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RECOMMENDED OPERATING CONDITIONS
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.6 V
Voltage at any bus terminal (separately or common mode) V
I
or V
IC
– 7
(1)
12 V
High-level input voltage, V
IH
D, DE, RE 2 V
CC
V
Low-level input voltage, V
IL
D, DE, RE 0 0.8 V
Differential input voltage, V
ID
(see Figure 8 ) – 12 12 V
Driver – 60High-level output current, I
OH
mAReceiver – 8
Driver 60Low-level output current, I
OL
mAReceiver 8
Differential load resistance, R
L
54 60
Differential load capacitance, C
L
50 pF
HVD10 25
Signaling rate HVD11 10 Mbps
HVD12 1
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
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DRIVER ELECTRICAL CHARACTERISTICS
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
Input clamp voltage I
I
= – 18 mA – 1.5 V
I
O
= 0 2 V
CC
|V
OD
| Differential output voltage
(2)
R
L
= 54 , See Figure 2 1.5 V
V
test
= – 7 V to 12 V, See Figure 3 1.5
Change in magnitude of differential outputΔ|V
OD
| See Figure 2 and Figure 3 – 0.2 0.2 Vvoltage
V
OC(PP)
Peak-to-peak common-mode output voltage 400 mV
V
OC(SS)
Steady-state common-mode output voltage 1.4 2.5 VSee Figure 4Change in steady-state common-mode outputΔV
OC(SS)
– 0.05 0.05 Vvoltage
I
OZ
High-impedance output current See receiver input currents
D – 100 0I
I
Input current μADE 0 100
I
OS
Short-circuit output current – 7 V V
O
12 V – 250 250 mA
C
(OD)
Differential output capacitance V
OD
= 0.4 sin (4E6 πt) + 0.5 V, DE at 0 V 16 pF
RE at V
CC
,
Receiver disabledD and DE at V
CC
, 9 15.5 mAand driver enabledNo load
RE at V
CC
,
Receiver disabledD at V
CC
,I
CC
Supply current and driver disabled 1 5 μADE at 0 V,
(standby)No load
RE at 0 V,
Receiver enabledD and DE at V
CC
, 9 15.5 mAand driver enabledNo load
(1) All typical values are at 25 °C and with a 3.3 V supply.(2) For T
A
> 85 °C, V
CC
is ± 5%.
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DRIVER SWITCHING CHARACTERISTICS
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
HVD10 5 8.5 16
t
PLH
Propagation delay time, low-to-high level output HVD11 18 25 40 ns
HVD12 135 200 330
HVD10 5 8.5 16
t
PHL
Propagation delay time, high-to-low level output HVD11 18 25 40 ns
HVD12 135 200 330
HVD10 3 4.5 11.5R
L
= 54 , C
L
= 50 pF,t
r
Differential output signal rise time HVD11 10 20 30 nsSee Figure 5HVD12 100 170 330
HVD10 3 4.5 11.5
t
f
Differential output signal fall time HVD11 10 20 30 ns
HVD12 100 170 330
HVD10 1.5
t
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) HVD11 2.5 ns
HVD12 9
HVD10 6
t
sk(pp)
(2)
Part-to-part skew HVD11 11 ns
HVD12 100
HVD10 33Propagation delay time, high impedance-to-hight
PZH
HVD11 55 nslevel output
HVD12 320R
L
= 110 , RE at 0 V,See Figure 6HVD10 26Propagation delay time, hight
PHZ
HVD11 55 nslevel-to-high-impedance output
HVD12 320
HVD10 26Propagation delay time, hight
PZL
HVD11 55 nsimpedance-to-low-level output
HVD12 320R
L
= 110 , RE at 0 V,See Figure 7HVD10 26Propagation delay time, lowt
PLZ
HVD11 75 nslevel-to-high-impedance output
HVD12 420
I and
6Propagation delay time, standby-to-high-level R
L
= 110 , RE at 3 V,Q-tempt
PZH
μsoutput See Figure 6M-temp 14
I and
6Propagation delay time, standby-to-low-level R
L
= 110 , RE at 3 V,Q-tempt
PZL
μsoutput See Figure 7M-temp 14
(1) All typical values are at 25 °C and with a 3.3 V supply.(2) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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RECEIVER ELECTRICAL CHARACTERISTICS
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Positive-going input thresholdV
IT+
I
O
= – 8 mA – 0.01 Vvoltage
Negative-going input thresholdV
IT –
I
O
= 8 mA – 0.2 Vvoltage
V
hys
Hysteresis voltage (V
IT+
– V
IT –
) 35 mV
V
IK
Enable-input clamp voltage I
I
= – 18 mA – 1.5 V
V
OH
High-level output voltage V
ID
= 200 mV, I
OH
= – 8 mA, See Figure 8 2.4 V
V
OL
Low-level output voltage V
ID
= – 200 mV, I
OL
= 8 mA, See Figure 8 0.4 V
I
OZ
High-impedance-state output current V
O
= 0 or V
CC
RE at V
CC
– 1 1 μA
V
A
or V
B
= 12 V 0.05 0.11
V
A
or V
B
= 12 V, V
CC
= 0 V 0.06 0.13HVD11, HVD12,
mAOther input at 0 VV
A
or V
B
= – 7 V – 0.1 – 0.05
V
A
or V
B
= – 7 V, V
CC
= 0 V – 0.05 ÷0.04I
I
Bus input current
V
A
or V
B
= 12 V 0.2 0.5
V
A
or V
B
= 12 V, V
CC
= 0 V 0.25 0.5HVD10,
mAOther input at 0 VV
A
or V
B
= – 7 V – 0.4 – 0.2
V
A
or V
B
= – 7 V, V
CC
= 0 V – 0.4 – 0.15
I
IH
High-level input current, RE V
IH
= 2 V – 30 0 μA
I
IL
Low-level input current, RE V
IL
= 0.8 V – 30 0 μA
C
ID
Differential input capacitance V
ID
= 0.4 sin (4E6 πt) + 0.5 V, DE at 0 V 15 pF
RE at 0 V,
Receiver enabled and driverD and DE at 0 V, 4 8 mAdisabledNo load
RE at V
CC
,D at V
CC
, Receiver disabled and driverI
CC
Supply current 1 5 μADE at 0 V, disabled (standby)No load
RE at 0 V,
Receiver enabled and driverD and DE at V
CC
, 9 15.5 mAenabledNo load
(1) All typical values are at 25 °C and with a 3.3 V supply.
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RECEIVER SWITCHING CHARACTERISTICS
THERMAL CHARACTERISTICS
(1)
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high level output HVD10 12.5 20 25 ns
t
PHL
Propagation delay time, high-to-low level output HVD10 12.5 20 25 ns
HVD11t
PLH
Propagation delay time, low-to-high level output 30 55 70 nsHVD12
V
ID
= 1.5 V to 1.5 V,HVD11t
PHL
Propagation delay time, high-to-low level output C
L
= 15 pF, See Figure 9 30 55 70 nsHVD12
HVD10 1.5
t
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) HVD11 4 ns
HVD12 4
HVD10 8
t
sk(pp)
(2)
Part-to-part skew HVD11 15 ns
HVD12 15
t
r
Output signal rise time 1 2 6C
L
= 15 pF, See Figure 9 nst
f
Output signal fall time 1 2 6
t
PZH
(1)
Output enable time to high level 16
t
PZL
(1)
Output enable time to low level 16C
L
= 15 pF, DE at 3 V,
nsSee Figure 10t
PHZ
Output disable time from high level 21
t
PLZ
Output disable time from low level 16
I and
6Propagation delay time, standby-to-high-level
Q-tempt
PZH
(2)
output
M-temp 14C
L
= 15 pF, DE at 0,
μsSee Figure 11I and
6Propagation delay time, standby-to-low-level
Q-tempt
PZL
(2)
output
M-temp 14
(1) All typical values are at 25 °C and with a 3.3 V supply.(2) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
θ
JA
Junction-to-ambient thermal resistance
(2)
High-K board
(3)
, No airflow D package 121 °C/W
θ
JB
Junction-to-board thermal resistance High-K board D package 67 °C/W
θ
JC
Junction-to-case thermal resistance D package 41 °C/W
HVD10
198 233 mW(25 Mbps)R
L
= 60 , C
L
= 50 pF,DE at V
CC
RE at 0 V, HVD11P
D
Device power dissipation 141 176 mWInput to D a 50% duty cycle square (10 Mbps)wave at indicated signaling rate
HVD12
133 161 mW(500 kbps)
T
JSD
Thermal shutdown junction temperature 165 °C
(1) See Application Information section for an explanation of these parameters.(2) The intent of θ
JA
specification is solely for a thermal performance comparison of one package to another in a standardized environment.This methodology is not meant to and will not predict the performance of a package in an application-specific environment.(3) JSD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
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{if TEXAS INSTRUMENTS www.ll.com 3750: 4» T T narsv Von 60014% T e l o f ‘ 3750114, l CL Includes Fixture and Inpul: PRR = 500 kHz, 50% Duly Cycle, l, < 6="" ns,="">< 5="" ns.="" 20="" fl‘lt="" “i,="" l="" 7="" if="" if="" generator:="" prr="500" khz,="" 50%="" duly="" cycle.="" l,="">< 5="" ns,="" l.="">< 6="" ns,="" 2c="" cl="" :="" so="" pf="" my="" 509="" c="" lncludesfixlure="" an="" instrumentation="" capacilanc="" generalnr="" generam:="" prr="500" khz,="" 50%="" duly="" cycle,="" l,="">< 6="" n="">
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PARAMETER MEASUREMENT INFORMATION
60 ±1%
VOD
0 or 3 V
_
+−7 V < V(test) < 12 V
DE
VCC
A
B
D
375 ±1%
375 ±1%
IOA
VOD 54 ±1%
0 or 3 V
VOA
VOB
IOB
DE
VCC
II
VI
A
B
VOC
27 ± 1%
Input
A
B
VA
VB
VOC(PP) VOC(SS)
VOC
27 ± 1%
CL = 50 pF ±20%
DA
B
DE
VCC
Input: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50
CL Includes Fixture and
Instrumentation Capacitance
VOD
RL = 54
± 1%
50
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50
tPLH tPHL
1.5 V 1.5 V
3 V
2 V
−2 V
90%
10%
0 V
VI
VOD
trtf
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VCC
VI
Input
Generator 90% 0 V
10%
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
Figure 2. Driver V
OD
Test Circuit and Voltage and Figure 3. Driver V
OD
With Common-Mode Loading TestCurrent Definitions Circuit
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
Figure 6. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
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{if TEXAS INSTRUMENTS www.ll.com cL = so pF flD'V Inpul Generalol 50 0 :2 Includes Fixture anh Instrumentation Capacitance Generator: PRR = 500 kHz, 50% Duty Cycle, I, < 6="" ns,="" t.="">< 6="" ns,="" 2,,="" l="" i="" 500="" b="" °'="" \="" lava="" “i="" dv="" generator:="" prr="" :="" 500="" khz,="" 50%="" duty="" cycle,="" 1,="">< 6="" ns,="">
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Input
Generator 50
3 V VO
S1
3 V
1.5 V 1.5 V
tPZL tPLZ
2.3 V 0.5 V
3 V
0 V
VOL
VI
VO
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50
RL = 110
± 1%
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VI
3 V
VID
VA
VB
IO
A
B
IBVO
R
IA
VIC
VA + VB
2
Input
Generator 50
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50
VO
1.5 V
0 V
1.5 V 1.5 V
3 V
VOH
VOL
1.5 V
10%
1.5 V
tPLH tPHL
trtf
90%
VI
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
A
B
RE
VI
R
0 V
90%
10%
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 8. Receiver Voltage and Current Definitions
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
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{if TEXAS INSTRUMENTS www.ll.com 500 Generalov: PRR = 500 kHz, 50% Duly Cycle. 1.5V \ tpmmJ‘ f tmfl‘ m
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50
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50
VO
RE
R
A
B
3 V
0 V or 3 V
3 V
1.5 V 1.5 V
tPZH(1) tPHZ
1.5 V
VOH −0.5 V
3 V
0 V
VOH
0 V
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VI
DE
D1 k ± 1%
VI
A
B
S1
D at 3 V
S1 to B
tPZL(1) tPLZ
1.5 V VOL +0.5 V
3 V
VOL
VO
D at 0 V
S1 to A
Input
Generator
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 10. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
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{if TEXAS INSTRUMENTS www.ll.com or 50f) Genevalor: PRR = 100 kHz. 50% Duly Pulse Generalor. 100 Q 11% 15 us Duration. 1% Duly Cycle n. t. smo ns
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Input
Generator 50
Generator: PRR = 100 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50
VO
RE
R
A
B
3 V
1.5 V
tPZH(2)
1.5 V
3 V
0 V
VOH
GND
VI
VO
0 V or 1.5 V
1.5 V or 0 V CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VI
1 k ± 1% A
B
S1
A at 1.5 V
B at 0 V
S1 to B
tPZL(2)
1.5 V
3 V
VOL
VO
A at 0 V
B at 1.5 V
S1 to A
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf 100 ns
100
± 1%
_
+
A
BR
D
DE
RE
0 V or 3 V
NOTE:This test is conducted to test survivability only. Data stability at the R output is not specified.
3 V or 0 V
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Receiver Enable Time From Standby (Driver Disabled)
Figure 12. Test Circuit, Transient Over Voltage Test
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{if TEXAS INSTRUMENTS www.li.com
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SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
Function Tables
abc
DRIVER
OUTPUTSINPUT ENABLED DE
A B
H H H L
L H L H
X L Z Z
Open H H L
RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUTV
ID
= V
A
– V
B
RE R
V
ID
– 0.2 V L L
– 0.2 V < V
ID
< – 0.01 V L ?
– 0.01 V V
ID
L H
X H Z
Open Circuit L H
Short Circuit L H
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65HVD10-EP SN65HVD11-EP SN65HVD12-EP
{if TEXAS INSTRUMENTS www.ll.com ")0 k0 I m Inpul 9V Inpul lkfl 9V ")0 k0 16V 16V Skfl 36 k0 45 k0 IBD k0
www.ti.com
9 V
1 k
100 k
Input
VCC
D and RE Inputs
9 V
1 k
100 k
Input
VCC
DE Input
16 V
16 V
100 kR3 R1
R2
Input
A Input
16 V
16 V
100 k
R3 R1
R2
Input
B Input
16 V
16 V
VCC
A and B Outputs
9 V
VCC
R Output
5 Output
VCC
SN65HVD10
SN65HVD11
SN65HVD12
R1/R2
9 k
36 k
36 k
R3
45 k
180 k
180 k
VCC
Output
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
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{9 TEXAS 'WM , 7 \ w w // / 0% /;// / / Vcc : 3.6 V AZ“ / / my /
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TYPICAL CHARACTERISTICS
30
40
50
60
70
0 5 10 15 20 25 30 35 40
ICC
TA = 25°C
RE at VCC
DE at VCC
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
− RMS Supply Current − mA
Signaling Rate − Mbps
HVD10 OR HVD12
RMS SUPPLY CURRENT
vs
SIGNALING RATE
RL = 54
CL = 50 pF
30
40
50
60
70
0 2.5 5 7.5 10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
Signaling Rate − Mbps
HVD11
RMS SUPPLY CURRENT
vs
SIGNALING RATE
ICC− RMS Supply Current − mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54
CL = 50 pF
30
40
50
60
70
100 400 700 1000
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
Signaling Rate − kbps
HVD12
RMS SUPPLY CURRENT
vs
SIGNALING RATE
ICC− RMS Supply Current − mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54
CL = 50 pF
−200
−150
−100
−50
0
50
100
150
200
250
300
−7−6−5 −4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
− Bus Input Current −
HVD10
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
IIAµ
VI − Bus Input Voltage − V
VCC = 0 V
VCC = 3.3 V
TA = 25°C
DE at 0 V
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
Figure 13. Figure 14.
Figure 15. Figure 16.
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{if TEXAS INSTRUMENTS www.ll.com — Driver Diflerenlial Oulpul — V
www.ti.com
−200
−150
−100
−50
0
50
100
150
−4 −2 0 2 4 6
TA = 25°C
DE at VCC
D at VCC
VCC = 3.3 V
VOH − Driver High-Level Output Voltage − V
HIGH-LEVEL OUTPUT CURRENT
vs
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
IOH − High-Level Output Current − mA
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
−7−6−5−4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
− Bus Input Current −
HVD11 OR HVD12
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
IIAµ
VI − Bus Input Voltage − V
VCC = 0 V
VCC = 3.3 V
TA = 25°C
DE at 0 V
−20
0
20
40
60
80
100
120
140
160
180
200
−4 −2 0 2 4 6 8
LOW-LEVEL OUTPUT CURRENT
vs
DRIVER LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
DE at VCC
D at 0 V
VCC = 3.3 V
VOL − Driver Low-Level Output Voltage − V
IOL− Low-Level Output Current − mA
− Driver Differential Output − V
DRIVER DIFFERENTIAL OUTPUT
vs
FREE-AIR TEMPERATURE
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
−40 −15 10 35 60 85
VOD
TA − Free-Air Temperature − °C
VCC = 3.3 V
DE at VCC
D at VCC
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
Figure 17. Figure 18.
Figure 19. Figure 20.
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Product Folder Link(s): SN65HVD10-EP SN65HVD11-EP SN65HVD12-EP
{if TEXAS INSTRUMENTS www.ll.com Vcc
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VCC − Supply Voltage − V
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
−35
−30
−25
−20
−40
−15
−10
−5
− Driver Output Current − mA
IO
00 0.50 1 1.50 2 2.50 3 3.50
TA = 25°C
DE at VCC
D at VCC
RL = 54
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
Figure 21.
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN65HVD10-EP SN65HVD11-EP SN65HVD12-EP
RT 4* 1 0 Device Number van ann vaz 256 NOTE The lme 5mm be termmaled at both ends with Ms char shame be kept as short as passwb‘e. TeK Run: 25.0MS/S Sample [ T 1 “M 2+ fl 2ko m m M 2.00m Aux .I' *1-‘7V Ifeb 2002 13:25:50 {5‘ TEXAS INSTRUMENTS www.ll.com
www.ti.com
APPLICATION INFORMATION
RTRT
Device
HVD10
HVD11
HVD12
Number of Devices on Bus
64
256
256
NOTE:The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths off the main line
should be kept as short as possible.
Stub
Driver Input
Driver Output
Receiver Input
Receiver Output
SN65HVD10-EP , , SN65HVD11-EPSN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
An example application for the HVD12 is illustrated in Figure 22 . Two HVD12 transceivers are used tocommunicate data through a 2000 foot (600 m) length of Commscope 5524 category 5e+ twisted pair cable. Thebus is terminated at each end by a 100 resistor, matching the cable characteristic impedance. Figure 23illustrates operation at a signaling rate of 250 kbps.
Figure 22. Typical Application Circuit
Figure 23. HVD12 Input and Output Through 2000 Feet of Cable
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THERMAL CHARACTERISTICS OF IC PACKAGES
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
Junction-to-Ambient Thermal Resistance ( θ
JA
)is defined as the difference in junction temperature to ambienttemperature divided by the operating power.
θ
JA
is not a constant and is a strong function of:the PCB design (50% variation)altitude (20% variation)device power (5% variation)
θ
JA
can be used to compare the thermal performance of packages if the specific test conditions are defined andused. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,and the thermal characteristics of holding fixtures. θ
JA
is often misused when it is used to calculate junctiontemperatures for other installations.
Texas Instruments uses two test PCBs as defined by JEDEC specifications. The low-k board gives averagein-use condition thermal performance and consists of a single copper trace layer 25 mm long and 2 oz thick. Thehigh-k board gives best case in-use condition and it consists of two 1 oz buried power planes with a singlecopper trace layer 25 mm long and 2 oz thick. A 4% to 50% difference in θ
JA
can be measured between thesetwo test cards
Junction-to-Case Thermal Resistance ( θ
JC
)is defined as difference in junction temperature to case divided bythe operating power. It is measured by putting the mounted package up against a copper block cold plate toforce heat to flow from die, through the mold compound into the copper block.
θ
JC
is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic topredict junction temperature because it provides pessimistic numbers if the case temperature is measured in anonstandard system and junction temperatures are backed out. It can be used with θ
JB
in one-dimensionalthermal simulation of a package system.
Junction-to-Board Thermal Resistance ( θ
JB
)is defined as the difference in the junction temperature and thePCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-platestructure. θ
JB
is defined only for the high-k test card.
θ
JB
provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermalresistance (especially for BGAs with thermal balls) and can be used for simple one-dimensional network analysisof the package system (see Figure 24 ).
Figure 24. Thermal Resistance
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): SN65HVD10-EP SN65HVD11-EP SN65HVD12-EP
I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN65HVD10MDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 V10MEP
SN65HVD10QDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V10QEP
SN65HVD12IDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 V12IEP
V62/05604-01XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V10QEP
V62/05604-03XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 V12IEP
V62/05604-04XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 V10MEP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD10-EP, SN65HVD12-EP :
Catalog: SN65HVD10, SN65HVD12
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pi» Reel Diame|er AD Dimension designed to accommodate the componeni width ED Dimension deSigned to eccemmodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w Overeii Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD10MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD10QDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD12IDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jul-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD10MDREP SOIC D 8 2500 340.5 336.1 25.0
SN65HVD10QDREP SOIC D 8 2500 340.5 336.1 25.0
SN65HVD12IDREP SOIC D 8 2500 340.5 336.1 25.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jul-2021
Pack Materials-Page 2
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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