PIC18(L)F26 to 57K42 Datasheet by Microchip Technology

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6‘ MICRDCHIP
2017-2019 Microchip Technology Inc. DS40001919E-page 1
PIC18(L)F26/27/45/46/47/55/56/57K42
Description
The PIC18(L)F26/27/45/46/47/55/56/57K42 microcontrollers are available in 28/40/44/48-pin devices. These devices
feature a 12-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD) techniques for advanced
touch sensing, averaging, filtering, oversampling and threshold comparison, Temperature Sensor, Vectored Interrupt
Controller with fixed latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with
support for Asynchronous, DMX, DALI and LIN transmissions, SPI, I2C, memory features like Memory Access Partition
(MAP) to support customers in data protection and bootloader applications, and Device Information Area (DIA) which
stores factory calibration values to help improve temperature sensor accuracy.
Core Features
C Compiler Optimized RISC Architecture
Operating Speed:
- Up to 64 MHz clock input
- 62.5 ns minimum instruction cycle
Two Direct Memory Access (DMA) Controllers
- Data transfers to SFR/GPR spaces from
either Program Flash Memory, Data
EEPROM or SFR/GPR spaces
- User-programmable source and destination
sizes
- Hardware and software-triggered data
transfers
System Bus Arbiter with User-Configurable
Priorities for Scanner and DMA1/DMA2 with
respect to the main line and interrupt execution
Vectored Interrupt Capability
- Selectable high/low priority
- Fixed interrupt latency
- Programmable vector table base address
31-Level Deep Hardware Stack
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRT)
Brown-Out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT)
- Variable prescaler selection
- Variable window size selection
- Configurable in hardware or software
Memory
Up to 128 KB Flash Program Memory
Up to 8 KB Data SRAM Memory
Up to 1 KB Data EEPROM
Memory Access Partition (MAP)
- Configurable boot and app region sizes with
individual write-protections
Programmable Code Protection
Device Information Area (DIA) stores:
- Unique IDs and Device IDs
- Temp Sensor factory-calibrated data
- Fixed Voltage Reference calibrated data
Device Configuration Information (DCI) stores:
- Erase row size
- Number of write latches per row
- Number of user rows
- Data EEPROM memory size
- Pin count
Operating Characteristics
Operating Voltage Range:
- 1.8V to 3.6V (PIC18LF26/27/45/46/55/56/
57K42)
- 2.3V to 5.5V (PIC18F26/27/45/46/47/55/56/
57K42)
Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Functionality
Doze mode: Ability to run CPU core slower than
the system clock
Idle mode: Ability to halt CPU core while internal
peripherals continue operating
Sleep mode: Lowest power consumption
Peripheral Module Disable (PMD):
-
Ability to disable unused peripherals
to
minimize power consumption
28/40/44/48-Pin, Low-Power High-Performance
Microcontrollers with XLP Technology
2017-2019 Microchip Technology Inc. DS40001919E-page 2
PIC18(L)F26/27/45/46/47/55/56/57K42
eXtreme Low-Power (XLP) Features
Sleep mode: 60 nA @ 1.8V, typical
Windowed Watchdog Timer: 720 nA @ 1.8V,
typical
Secondary Oscillator: 580 nA @ 32 kHz
Operating Current:
- 5 uA @ 32 kHz, 1.8V, typical
- 65 uA/MHz @ 1.8V, typical
Digital Peripherals
Three 8-Bit Timers (TMR2/4/6) with Hardware
Limit Timer (HLT)
- Hardware monitoring and Fault detection
Four 16-Bit Timers (TMR0/1/3/5)
Four Configurable Logic Cell (CLC):
- Integrated combinational and sequential logic
Three Complementary Waveform Generators
(CWGs):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
- Programmable dead band
- Fault-shutdown input
Four Capture/Compare/PWM (CCP) modules
Four 10-bit Pulse-Width Modulators (PWMs)
Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control
- High resolution using 20-bit accumulator and
20-bit increment values
DSM: Data Signal Modulator
- Multiplex two carrier clocks, with glitch
prevention feature
- Multiple sources for each carrier
Programmable CRC with Memory Scan:
- Reliable data/program memory monitoring for
fail-safe operation (e.g., Class B)
- Calculate CRC over any portion of program
memory or data EEPROM
Two UART Modules:
- Modules are asynchronous and compatible
with RS-232 and RS-485
- One of the UART modules supports LIN
Master and Slave, DMX-512 mode, DALI
Gear and Device protocols
- Automatic and user-timed BREAK period
generation
- DMA Compatible
- Automatic checksums
- Programmable 1, 1.5, and 2 Stop bits
- Wake-up on BREAK reception
One SPI module:
- Configurable length bytes
- Configurable length data packets
- Receive-without-transmit option
- Transmit-without-receive option
- Transfer byte counter
- Separate Transmit and Receive Buffers with
2-byte FIFO and DMA capabilities
•Two I
2C modules, SMBus, PMBus™ compatible:
- Supports Standard-mode (100 kHz), Fast-
mode (400 kHz) and Fast-mode plus (1 MHz)
modes of operation
- Dedicated Address, Transmit and Receive
buffers
- Bus Collision Detection with arbitration
- Bus time-out detection and handling
- Multi-Master mode
- Separate Transmit and Receive Buffers with
2-byte FIFO and DMA capabilities
-I
2C, SMBus 2.0 and SMBus 3.0, and 1.8V
input level selections
Device I/O Port Features:
- 24 I/O pins (PIC18(L)F2xK42)
- 35 I/O pins (PIC18(L)F4xK42)
- 43 I/O pins (PIC18(L)F5xK42)
- One input-only pin (RE3)
- Individually programmable I/O direction,
open-drain, slew rate, weak pull-up control
- Interrupt-on-change (on up to 25 I/O pins)
- Three External Interrupt Pins
Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
Signal Measurement Timer (SMT):
- 24-bit timer/counter with prescaler
2017-2019 Microchip Technology Inc. DS40001919E-page 3
PIC18(L)F26/27/45/46/47/55/56/57K42
Analog Peripherals
Analog-to-Digital Converter with Computation
(ADC2):
- 12-bit with up to 35 external channels
- Automated post-processing
- Automated math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Operates in Sleep
- Integrated charge pump for improved low-
voltage operation
Hardware Capacitive Voltage Divider (CVD):
- Automates touch sampling and reduces
software size and CPU usage when touch or
proximity sensing is required
- Adjustable sample and hold capacitor array
- Two guard ring output drives
Temperature Sensor
- Internal connection to ADC
- Can be calibrated for improved accuracy
Two Comparators:
- Low-Power/High-Speed mode
- Fixed Voltage Reference at noninverting
input(s)
- Comparator outputs externally accessible
5-bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
Voltage Reference
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
Flexible Oscillator Structure
High-Precision Internal Oscillator
- Selectable frequency range up to 64 MHz
- ±1% at calibration (nominal)
Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
External 32 kHz Crystal Oscillator (SOSC)
External Oscillator Block with:
- x4 PLL with external sources
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
Fail-Safe Clock Monitor
Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator sources
2017-2019 Microchip Technology Inc. DS40001919E-page 4
PIC18(L)F26/27/45/46/47/55/56/57K42
PIC18(L)F2X/4X/5XK42 FAMILY TYPES
Device
Data Sheet Index
Program Flash Memory (KB)
Data EEPROM (B)
Data SRAM (bytes)
I/O Pins
12-bit ADC2
(ch)
5-bit DAC
Comparator
8-bit/ (with HLT) /16-bit Timer
Window Watchdog Timer
(WWDT)
Signal Measurement Timer
(SMT)
CCP/10-bit PWM
CWG
NCO
CLC
Zero-Cross Detect
Direct Memory Access (DMA)
(ch)
Memory Access Partition
Vectored Interrupts
UART
I2C/SPI
Peripheral Pin Select
Peripheral Module Disable
Debug (1)
PIC18(L)F24K42 A16 256 1024 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F25K42 A32 256 2048 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F26K42 B 64 1024 4096 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F27K42 B 128 1024 8192 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F45K42 B 32 256 2048 36 35 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F46K42 B 64 1024 4096 36 35 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F47K42 B 128 1024 8192 36 35 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F55K42 B 32 256 2048 44 43 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F56K42 B 64 1024 4096 44 43 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
PIC18(L)F57K42 B 128 1024 8192 44 43 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 2 2/1 Y Y I
Note 1: I – Debugging integrated on chip.
Data Sheet Index:
Shaded devices are not described in this document.
A: DS40001869 PIC18(L)F24/25K42 Data Sheet, 28-Pin
B: DS40001919 PIC18(L)F26/27/45/46/47/55/56/57K42 Data Sheet, 28/40/44/48-Pin
Note: For other small form-factor package availability and marking information, visit
http://www.microchip.com/packaging or contact your local sales office.
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2017-2019 Microchip Technology Inc. DS40001919E-page 5
PIC18(L)F26/27/45/46/47/55/56/57K42
Pin Diagrams
PIC18(L)F2XK42
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
11
12
13
14 15
16
17
18
19
20
28
27
26
25
24
23
22
21
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RC5
RC4
RC7
RC6
RB7/ICSPDAT
Note: See Table 1 for location of all peripheral functions.
28-pin SPDIP, SOIC, SSOP
2
3
6
1
18
19
20
21
15
7
16
17
RC0
5
4
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB0
VDD
VSS
RC7
RC6
RC5
RC4
RE3/MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC1
RC2
RC3
910 138141211
27 26 2328 2224
25
RB3
RB2
RB1
PIC18(L)F2XK42
Note 1: See Table 1 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the
only VSS connection to the device.
28-pin QFN (6x6x0.9mm), UQFN (6x6x0.5mm)
jjjjjjjjjjjjjjjjjjjj DDDDDDDDDDDDDDDDDDDD 33 32 11121314151617131920
2017-2019 Microchip Technology Inc. DS40001919E-page 6
PIC18(L)F26/27/45/46/47/55/56/57K42
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
RB6/ICSPCLK
RB5
RB4
RB0
VDD
VSS
RD2
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD0
RD1
RC5
RC4
RD3
RD4
RC7
RC6
RD7
RD6
RD5
RB7/ICSPDAT
1
RB3
RB2
RB1
PIC18(L)F4XK42
Note: See Table 2 for location of all peripheral functions.
40-pin PDIP
10
11
2
3
4
5
6
1
18 19 20
21
22
12 13 14 15
38
8
7
40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36 34
35
9
37
RA1
RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RA3
RA2
PIC18(L)F4XK42
Note 1: See Table 2 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only
VSS connection to the device.
40-pin UQFN (5x5x0.5mm)
2017-2019 Microchip Technology Inc. DS40001919E-page 7
PIC18(L)F26/27/45/46/47/55/56/57K42
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
NC RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA6
RA7
NC
VSS
NC
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
NC
RB0
RB1
RB2
RA3
RA2
RA1
PIC18(L)F4XK42
Note 1: See Tab le 2 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the
only VSS connection to the device.
44-pin QFN (8x8x0.9mm)
2017-2019 Microchip Technology Inc. DS40001919E-page 8
PIC18(L)F26/27/45/46/47/55/56/57K42
10
11
2
3
6
1
20
21
22
23
24
16
17
42
8
7
48
47
46
45
44
43
18
19
31
32
33
34
35
25
26
27
28
29
30
40
39
9
41
5
4
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RF3
RC0
RA1
RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
RA3
RA2
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RA6
RA7
VSS
RC1
VDD
RE2
RE1
RE0
RA5
RA4
12
RF4
13
14
15
RF5
RF7
RF6
36 RF0
37
38 RF2
RF1
Note: See Tab le 3 for location of all peripheral functions.
PIC18(L)F5XK42
48-pin TQFP (7x7x1mm)/
48-pin UQFN (6x6x0.5mm)
CLCNO”
2017-2019 Microchip Technology Inc. DS40001919E-page 9
PIC18(L)F26/27/45/46/47/55/56/57K42
Pin Allocation Tables
TABLE 1: 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42)
I/O
28-Pin SPDIP/SOIC/SSOP
28-Pin (U)QFN
ADC
2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I
2
C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
RA0 227 ANA0 C1IN0-
C2IN0-
— — CLCIN0
(1)
IOCA0
RA1 3 28 ANA1 C1IN1-
C2IN1-
— — CLCIN1
(1)
——IOCA1
RA2 4 1 ANA2 V
REF
-DAC1OUT1 C1IN0+
C2IN0+
IOCA2
RA352ANA3V
REF
+ C1IN1+ — MDCARL
(1)
——IOCA3
RA4 6 3 ANA4 — — MDCARH
(1)
T0CKI
(1)
IOCA4
RA5 7 4 ANA5 SS1
(1)
—MDSRC
(1)
——IOCA5
RA6 10 7ANA6 — — IOCA6 OSC2
CLKOUT
RA7 9 6 ANA7 IOCA7 OSC1
CLKIN
RB0 21 18 ANB0 C2IN1+ ZCD — — — CCP4
(1)
CWG1IN
(1)
INT0
(1)
IOCB0
RB1 22 19 ANB1 C1IN3-
C2IN3-
—SCL2
(3,4)
—— — CWG2IN
(1)
——INT1
(1)
IOCB1
RB2 23 20 ANB2 SDA2
(3,4)
CWG3IN
(1)
INT2
(1)
IOCB2
RB3 24 21 ANB3 C1IN2-
C2IN2-
—— — —IOCB3—
RB4 25 22 ANB4
ADCACT
(1)
— — T5G
(1)
IOCB4
RB5 26 23 ANB5 T1G
(1)
CCP3
(1)
——IOCB5
RB6 27 24 ANB6 — — CTS2
(1)
CLCIN2
(1)
IOCB6 ICSPCLK
RB7 28 25 ANB7 DAC1OUT2 RX2
(1)
T6IN(1) — CLCIN3
(1)
IOCB7 ICSPDAT
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels
will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds.
new; Wm
2017-2019 Microchip Technology Inc. DS40001919E-page 10
PIC18(L)F26/27/45/46/47/55/56/57K42
RC0 11 8ANC0 — — T1CKI
(1)
T3CKI
(1)
T3G
(1)
SMTWIN1
(1)
IOCC0 SOSCO
RC1 12 9 ANC1 SMTSIG1
(1)
CCP2
(1)
IOCC1 SOSCI
RC2 13 10 ANC2 — — T5CKI
(1)
CCP1
(1)
IOCC2
RC3 14 11 ANC3 SCL1
(3,4)
SCK1
(1)
——T2IN
(1)
— IOCC3
RC4 15 12 ANC4 SDA1
(3,4)
SDI1
(1)
IOCC4
RC5 16 13 ANC5 T4IN
(1)
— IOCC5
RC6 17 14 ANC6 — — CTS1
(1)
IOCC6
RC7 18 15 ANC7 RX1
(1)
— IOCC7
RE3 126 — — IOCE3 MCLR
V
PP
V
DD
20 17
V
SS
8,
19
5,
16
— —
OUT
(2)
—— ADGRDA
ADGRDB
——
C1OUT
C2OUT
SDA1
SCL1
SDA2
SCL2
SS1
SCK1
SDO1
DTR1
RTS1
TX1
DTR2
RTS2
TX2
DSM TMR0 CCP1
CCP2
CCP3
CCP4
PWM5OUT
PWM6OUT
PWM7OUT
PWM8OUT
CWG1A
CWG1B
CWG1C
CWG1D
CWG2A
CWG2B
CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
NCO CLKR ——
TABLE 1: 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42) (CONTINUED)
I/O
28-Pin SPDIP/SOIC/SSOP
28-Pin (U)QFN
ADC
2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I
2
C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels
will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds.
m
2017-2019 Microchip Technology Inc. DS40001919E-page 11
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 2: 40/44-PIN ALLOCATION TABLE FOR PIC18(L)F4XK42
I/O
40-Pin PDIP
44-Pin TQFP
40-Pin UQFN
44-Pin QFN
ADC2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I2C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
RA0 219 17 19 ANA0 C1IN0-
C2IN0-
CLCIN0(1) IOCA0
RA1 3 20 18 20 ANA1 C1IN1-
C2IN1-
— CLCIN1(1) — IOCA1
RA2 421 19 21 ANA2 VREF-DAC1OUT1 C1IN0+
C2IN0+
— — — — IOCA2
RA3 5 22 20 22 ANA3 VREF+ C1IN1+ — MDCARL(1) — IOCA3
RA4 623 21 23 ANA4 MDCARH(1) T0CKI(1) IOCA4
RA5 7 24 22 24 ANA5 SS1(1) —MDSRC
(1) — IOCA5
RA6 14 31 29 33 ANA6 — — — — IOCA6 OSC2
CLKOUT
RA7 13302832 ANA7 — — — — IOCA7 OSC1
CLKIN
RB0 33 8 8 9 ANB0 C2IN1+ ZCD — — CCP4(1) CWG1IN(1) INT0(1)
IOCB0
RB1 34 9 9 10 ANB1 C1IN3-
C2IN3-
—SCL2
(3,4)
—— — CWG2IN
(1) ——INT1
(1)
IOCB1
RB2 35 10 10 11 ANB2 SDA2
(3,4)
CWG3IN(1) INT2(1)
IOCB2
RB3 36 11 11 12 ANB3 C1IN2-
C2IN2-
— — — — IOCB3
RB4 37 14 12 14 ANB4
ADCACT(1) — — T5G(1) IOCB4
RB5 38151315 ANB5 T1G
(1) CCP3(1) — IOCB5
RB6 39 16 14 16 ANB6 CTS2(1) - CLCIN2(1) IOCB6 ICSPCLK
RB7 40 17 15 17 ANB7 DAC1OUT2 RX2(1) —T6IN
(1) — CLCIN3(1) IOCB7 ICSPDAT
RC0 15 32 30 34 ANC0 — — T1CKI(1)
T3CKI(1)
T3G(1)
SMTWIN1(1)
IOCC0 SOSCO
RC1 16 35 31 35 ANC1 SMTSIG1(1) CCP2(1) IOCC1 SOSCI
RC2 17 36 32 36 ANC2 — — T5CKI(1) CCP1(1) — IOCC2
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4/RD0/RD1 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
2017-2019 Microchip Technology Inc. DS40001919E-page 12
PIC18(L)F26/27/45/46/47/55/56/57K42
RC3 18 37 33 37 ANC3 SCL1
(3,4)
SCK1(1) ——T2IN
(1) ——IOCC3
RC4 23 42 38 42 ANC4 SDA1
(3,4)
SDI1(1) — IOCC4
RC5 24 43 39 43 ANC5 T4IN(1) ——IOCC5
RC6 25 44 40 44 ANC6 CTS1(1) — IOCC6
RC7 26 1 1 1 ANC7 RX1(1) ——IOCC7
RD0 19 38 34 38 AND0 (4) — — — — —
RD1 20 39 35 39 AND1 (4) —— ——— —
RD2 21 40 36 40 AND2 — — — — —
RD3 22 41 37 41 AND3
RD4 27 2 2 2 AND4 — — — — —
RD5 28 3 3 3 AND5 — — — — —
RD6 29 4 4 4 AND6 — — — — —
RD7 30 5 5 5 AND7 — — — — —
RE0 825 23 25 ANE0 — — — — —
RE1 9 26 24 26 ANE1
RE2 10 27 25 27 ANE2 — — — — —
RE3 1 18 16 18 IOCE3 MCLR
VPP
VDD 11,
32
7,
28
7,
26
7,
28
— — — — —
VSS 12,
31
6,
29
6,
27
6,
30
— —— — ———
TABLE 2: 40/44-PIN ALLOCATION TABLE FOR PIC18(L)F4XK42 (CONTINUED)
I/O
40-Pin PDIP
44-Pin TQFP
40-Pin UQFN
44-Pin QFN
ADC2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I2C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4/RD0/RD1 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
my
2017-2019 Microchip Technology Inc. DS40001919E-page 13
PIC18(L)F26/27/45/46/47/55/56/57K42
OUT(2) — — — — ADGRDA
ADGRDB
C1OUT
C2OUT
SDA1
SCL1
SDA2
SCL2
SS1
SCK1
SDO1
DTR1
RTS1
TX1
DTR2
RTS2
TX2
DSM TMR0 CCP1
CCP2
CCP3
CCP4
PWM5OUT
PWM6OUT
PWM7OUT
PWM8OUT
CWG1A
CWG1B
CWG1C
CWG1D
CWG2A
CWG2B
CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
NCO CLKR — —
TABLE 2: 40/44-PIN ALLOCATION TABLE FOR PIC18(L)F4XK42 (CONTINUED)
I/O
40-Pin PDIP
44-Pin TQFP
40-Pin UQFN
44-Pin QFN
ADC2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I2C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4/RD0/RD1 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
m
2017-2019 Microchip Technology Inc. DS40001919E-page 14
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 3: 48-PIN ALLOCATION TABLE FOR PIC18(L)F5XK42
I/O
48-Pin TQFP
48-Pin UQFN
ADC2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I2C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
RA0 21 21 ANA0 C1IN0-
C2IN0-
CLCIN0(1) IOCA0
RA1 22 22 ANA1 C1IN1-
C2IN1-
— CLCIN1(1) — IOCA1 —
RA2 23 23 ANA2 VREF-DAC1OUT1 C1IN0+
C2IN0+
— — — — — IOCA2
RA3 24 24 ANA3 VREF+ C1IN1+ — MDCARL(1) - — IOCA3 —
RA4 25 25 ANA4 — — — MDCARH(1) T0CKI(1) IOCA4
RA5 26 26 ANA5 — — — SS1(1) —MDSRC
(1) — IOCA5 —
RA6 33 33 ANA6 — — — IOCA6 OSC2
CLKOUT
RA7 32 32 ANA7 — — — IOCA7 OSC1
CLKIN
RB0 8 8 ANB0 C2IN1+ ZCD CCP4(1) CWG1IN(1) INT0(1)
IOCB0
RB1 9 9 ANB1 C1IN3-
C2IN3-
—SCL2
(3,4) —— — CWG2IN
(1) ——INT1
(1)
IOCB1
RB2 10 10 ANB2 — — — SDA2(3,4) CWG3IN(1) INT2(1)
IOCB2
RB3 11 11 ANB3 C1IN2-
C2IN2-
— — — — — IOCB3
RB4 16 16 ANB4
ADCACT(1) — — — T5G(1) IOCB4
RB5 17 17 ANB5 — — — T1G(1) CCP3(1) - — IOCB5 —
RB6 18 18 ANB6 — — — CTS2(1) CLCIN2(1) IOCB6 ICSPCLK
RB7 19 19 ANB7 DAC1OUT2 — — — RX2(1) —T6IN
(1) — CLCIN3(1) IOCB7 ICSPDAT
RC0 34 34 ANC0 — — — T1CKI(1)
T3CKI(1)
T3G(1)
SMTWIN1(1)
IOCC0 SOSCO
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4/RD0/RD1 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
2017-2019 Microchip Technology Inc. DS40001919E-page 15
PIC18(L)F26/27/45/46/47/55/56/57K42
RC1 35 35 ANC1 - — — — SMTSIG1(1) CCP2(1) IOCC1 SOSCI
RC2 40 40 ANC2 - — — — T5CKI(1) CCP1(1) IOCC2
RC3 41 41 ANC3 - SCL1(3,4) SCK1(1) T2IN(1) - IOCC3
RC4 46 46 ANC4 — — — SDA1(3,4) SDI1(1) — IOCC4 —
RC5 47 47 ANC5 — — — T4IN(1) IOCC5
RC6 48 48 ANC6 — — — CTS1(1) — IOCC6 —
RC7 1 1 ANC7 — — — RX1(1) IOCC7
RD0 42 42 AND0 (4) —— — ————
RD1 43 43 AND1 — — — (4) — — — — — —
RD2 44 44 AND2 — — — — — — —
RD3 45 45 AND3 — — — — — — —
RD4 2 2 AND4 — — — — — — —
RD5 3 3 AND5 — — — — — — —
RD6 4 4 AND6 — — — — — —
RD7 5 5 AND7 — — — — — — —
RE0 27 27 ANE0 — — — — — —
RE1 28 28 ANE1 — — — — — — —
RE2 29 29 ANE2 — — — — — —
RE3 20 20 — — — — — — IOCE3 MCLR
VPP
RF0 36 36 ANF0 — — — — — — —
RF1 37 37 ANF1 — — — — — — —
RF2 38 38 ANF2 — — — — — — —
RF3 39 39 ANF3 — — — — — — —
RF4 12 12 ANF4 — — — — — — —
RF5 13 13 ANF5 — — — — — — —
RF6 14 14 ANF6 — — — — — — —
RF7 15 15 ANF7 — — — — — — —
TABLE 3: 48-PIN ALLOCATION TABLE FOR PIC18(L)F5XK42 (CONTINUED)
I/O
48-Pin TQFP
48-Pin UQFN
ADC2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I2C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4/RD0/RD1 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
2017-2019 Microchip Technology Inc. DS40001919E-page 16
PIC18(L)F26/27/45/46/47/55/56/57K42
VDD 7,
30
7,
30
———— — ——
VSS 6,
31
6,
31
— — — — — — —
OUT(2) — — ADGRDA
ADGRDB
—— C1OUT
C2OUT
—SDA1
SCL1
SDA2
SCL2
SS1
SCK1
SDO1
DTR1
RTS1
TX1
DTR2
RTS2
TX2
DSM TMR0 CCP1
CCP2
CCP3
CCP4
PWM5OUT
PWM6OUT
PWM7OUT
PWM8OUT
CWG1A
CWG1B
CWG1C
CWG1D
CWG2A
CWG2B
CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
NCO CLKR —
TABLE 3: 48-PIN ALLOCATION TABLE FOR PIC18(L)F5XK42 (CONTINUED)
I/O
48-Pin TQFP
48-Pin UQFN
ADC2
Voltage Reference
DAC
Comparators
Zero Cross Detect
I2C
SPI
UART
DSM
Timers/SMT
CCP and PWM
CWG
CLC
NCO
Clock Reference (CLKR)
Interrupt-on-Change
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All output signals shown in this row are PPS remappable.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins can be configured for I2C and SMB™ 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4/RD0/RD1 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
2017-2019 Microchip Technology Inc. DS40001919E-page 17
PIC18(L)F26/27/45/46/47/55/56/57K42
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 19
2.0 Guidelines for Getting Started with PIC18(L)F26/27/45/46/47/55/56/57K42 Microcontrollers ................................................... 23
3.0 PIC18 CPU................................................................................................................................................................................. 26
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Device Configuration .................................................................................................................................................................. 65
6.0 Resets ........................................................................................................................................................................................ 81
7.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 92
8.0 Reference Clock Output Module .............................................................................................................................................. 111
9.0 Interrupt Controller ................................................................................................................................................................... 115
10.0 Power-Saving Operation Modes .............................................................................................................................................. 170
11.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 178
12.0 8x8 Hardware Multiplier............................................................................................................................................................ 187
13.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 189
14.0 Cyclic Redundancy Check (CRC) Module with Memory Scanner............................................................................................ 213
15.0 Direct Memory Access (DMA) .................................................................................................................................................. 228
16.0 I/O Ports ................................................................................................................................................................................... 260
17.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 275
18.0 Interrupt-on-Change ................................................................................................................................................................. 286
19.0 Peripheral Module Disable (PMD)............................................................................................................................................ 290
20.0 Timer0 Module ......................................................................................................................................................................... 299
21.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 305
22.0 Timer2/4/6 Module ................................................................................................................................................................... 320
23.0 Capture/Compare/PWM Module .............................................................................................................................................. 342
24.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 355
25.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 362
26.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 406
27.0 Configurable Logic Cell (CLC).................................................................................................................................................. 434
28.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 449
29.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 459
30.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 464
31.0 Universal Asynchronous Receiver Transmitter (UART) With Protocol Support ....................................................................... 475
32.0 Serial Peripheral Interface (SPI) Module.................................................................................................................................. 513
33.0 I2C Module ............................................................................................................................................................................... 545
34.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 598
35.0 Temperature Indicator Module ................................................................................................................................................. 600
36.0 Analog-to-Digital Converter with Computation (ADC2) Module ............................................................................................... 602
37.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 640
38.0 Comparator Module ................................................................................................................................................................. 644
39.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 653
40.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 661
41.0 Instruction Set Summary .......................................................................................................................................................... 663
42.0 Register Summary.................................................................................................................................................................... 717
43.0 Development Support............................................................................................................................................................... 734
44.0 Electrical Specifications............................................................................................................................................................ 738
45.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 770
46.0 Packaging Information.............................................................................................................................................................. 798
The Microchip WebSite ..................................................................................................................................................................... 831
Customer Change Notification Service ............................................................................................................................................. 831
Customer Support ............................................................................................................................................................................. 831
Product Identification System ........................................................................................................................................................... 832
2017-2019 Microchip Technology Inc. DS40001919E-page 18
PIC18(L)F26/27/45/46/47/55/56/57K42
TO OUR VALUED CUSTOMERS
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2017-2019 Microchip Technology Inc. DS40001919E-page 19
PIC18(L)F26/27/45/46/47/55/56/57K42
1.0 DEVICE OVERVIEW
This document contains device specific information for
the following devices:
This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the
addition of high-endurance Program Flash Mem-
ory, Universal Asynchronous Receiver Transmit-
ter (UART), Serial Peripheral Interface (SPI),
Inter-integrated Circuit (I2C), Direct Memory
Access (DMA), Configurable Logic Cells (CLC),
Signal Measurement Timer (SMT), Numerically
Controlled Oscillator (NCO), and Analog-to-Digital
Converter with Computation (ADC2).
1.1 New Features
Direct Memory Access Controller: The Direct
Memory Access (DMA) Controller is designed to
service data transfers between different memory
regions directly without intervention from the
CPU. By eliminating the need for CPU-intensive
management of handling interrupts intended for
data transfers, the CPU now can spend more time
on other tasks.
Vectored Interrupt Controller: The Vectored
Interrupt Controller module reduces the numerous
peripheral interrupt request signals to a single
interrupt request signal to the CPU. It assembles
all of the interrupt request signals and resolves
the interrupts based on both a fixed natural order
priority and a user-assigned priority, thereby
eliminating scanning of interrupt sources.
Universal Asynchronous Receiver
Transmitter: The Universal Asynchronous
Receiver Transmitter (UART) module is a serial
I/O communications peripheral. It contains all the
clock generators, shift registers and data buffers
necessary to perform an input or output serial
data transfer, independent of device program
execution. The UART can be configured as a full-
duplex asynchronous system or one of several
automated protocols. Full-Duplex mode is useful
for communications with peripheral systems, with
DMX/DALI/LIN support.
Serial Peripheral Interface: The Serial
Peripheral Interface (SPI) module is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices
communicate in a master/slave environment
where the master device initiates the
communication. A slave device is controlled
through a Chip Select known as Slave Select.
Example slave devices include serial EEPROMs,
shift registers, display drivers, A/D converters, or
another PIC.
I2C Module: The I2C module provides a
synchronous interface between the
microcontroller and other I2C-compatible devices
using the two-wire I2C serial bus. Devices
communicate in a master/slave environment. The
I2C bus specifies two signal connections - Serial
Clock (SCL) and Serial Data (SDA). Both the SCL
and SDA connections are bidirectional open-drain
lines, each requiring pull-up resistors to the
supply voltage.
12-bit A/D Converter with Computation: This
module incorporates programmable acquisition
time, allowing for a channel to be selected and a
conversion to be initiated without waiting for a
sampling period and thus, reduces code
overhead. It has a new module called ADC2 with
computation features, which provides a digital
filter and threshold interrupt functions.
1.2 Details on Individual Family
Members
Devices in the PIC18(L)F26/27/45/46/47/55/56/57K42
family are available in 28-pin and 40/44/48-pin
packages. The block diagram for this device is shown
in Figure 3-1.
The similarities and differences among the devices are
listed in the PIC18(L)F2X/4X/5XK42 Family Types
Table (page 4). The pinouts for all devices are listed in
Table 1.
• PIC18F26K42 • PIC18LF26K42
• PIC18F27K42 • PIC18LF27K42
• PIC18F45K42 • PIC18LF45K42
• PIC18F46K42 • PIC18LF46K42
• PIC18F47K42 • PIC18LF47K42
• PIC18F55K42 • PIC18LF55K42
• PIC18F56K42 • PIC18LF56K42
• PIC18F57K42 • PIC18LF57K42
2017-2019 Microchip Technology Inc. DS40001919E-page 20
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 1-1: DEVICE FEATURES
Features PIC18(L)F26K42 PIC18(L)F27K42 PIC18(L)F45K42 PIC18(L)F46K42 PIC18(L)F47K42 PIC18(L)F55K42 PIC18(L)F56K42 PIC18(L)F57K42
Program Memory
(Bytes) 65536 131072 32768 65536 131072 32768 65536 131072
Program Memory
(Instructions) 32768 65536 16384 32768 65536 16384 32768 65536
Data Memory (Bytes) 4096 8192 2048 4096 8192 2048 4096 8192
Data EEPROM
Memory (Bytes) 1024 1024 256 1024 1024 256 1024 1024
Packages
28-pin SPDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin UQFN
28-pin SPDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin UQFN
40-pin PDIP
40-pin UQFN
44-pin TQFP
44-pin QFN
40-pin PDIP
40-pin UQFN
44-pin TQFP
44-pin QFN
40-pin PDIP
40-pin UQFN
44-pin TQFP
44-pin QFN
48-pin TQFP
48-pin UQFN
48-pin TQFP
48-pin UQFN
48-pin TQFP
48-pin UQFN
I/O Ports A,B,C,E(1) A,B,C,E(1) A,B,C,D, E(1) A,B,C,D, E(1) A,B,C,D, E(1) A,B,C,D, E(1), F A,B,C,D, E(1), F A,B,C,D, E(1), F
12-Bit Analog-to-Digital
Conversion Module
(ADC2) with
Computation
Accelerator
5 internal
24 external
5 internal
24 external
5 internal
35 external
5 internal
35 external
5 internal
35 external
5 internal
43 external
5 internal
43 external
5 internal
43 external
Capture/Compare/
PWM Modules (CCP) 4
10-Bit Pulse-Width
Modulator (PWM) 4
Timers (16-/8-bit) 4/3
Serial Communications 1 UART, 1 UART with DMX/DALI/LIN, 2 I2C, 1 SPI
Complementary
Waveform Generator
(CWG)
3
Zero-Cross Detect
(ZCD) 1
Data Signal Modulator
(DSM) 1
Signal Measurement
Timer (SMT) 1
5-bit Digital to Analog
Converter (DAC) 1
Numerically Controlled
Oscillator (NCO) 1
2017-2019 Microchip Technology Inc. DS40001919E-page 21
PIC18(L)F26/27/45/46/47/55/56/57K42
Comparator Module 2
Direct Memory Access
(DMA) 2
Configurable Logic Cell
(CLC) 4
Peripheral Pin Select
(PPS) Yes
Peripheral Module
Disable (PMD) Yes
16-bit CRC with
Scanner Yes
Programmable High/
Low-Voltage Detect
(HLVD)
Yes
Resets (and Delays)
POR, Programmable BOR,
RESET Instruction,
Stack Overflow,
Stack Underflow
(PWRT, OST),
MCLR, WDT, MEMV
Instruction Set 81 Instructions;
87 with Extended Instruction Set enabled
Maximum Operating
Frequency 64 MHz
Note 1: PORTE is partially implemented. Pin RE3 is an input-only pin on 28/40/44/48-pin variants. In addition to that, on 40/44/48-pin variants, PORTE also
consists of RE0, RE1 and RE2 pins.
TABLE 1-1: DEVICE FEATURES (CONTINUED)
Features PIC18(L)F26K42 PIC18(L)F27K42 PIC18(L)F45K42 PIC18(L)F46K42 PIC18(L)F47K42 PIC18(L)F55K42 PIC18(L)F56K42 PIC18(L)F57K42
2017-2019 Microchip Technology Inc. DS40001919E-page 22
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1.3 Register and Bit naming
conventions
1.3.1 REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance, and control identifier.
The control registers section will show just one
instance of all the register names with an ‘x’ in the place
of the peripheral instance number. This naming
convention may also be applied to peripherals when
there is only one instance of that peripheral in the
device to maintain compatibility with other devices in
the family that contain more than one.
1.3.2 BIT NAMES
There are two variants for bit names:
Short name: Bit function abbreviation
Long name: Peripheral abbreviation + short name
1.3.2.1 Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the T0CON0 register
can be set in C programs with the instruction
T0CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.3.2.2 Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the Timer0 enable
bit is the Timer0 prefix, T0, appended with the enable
bit short name, EN, resulting in the unique bit name
T0EN.
Long bit names are useful in both C and assembly
programs. For example, in C the T0CON0 enable bit
can be set with the T0EN = 1 instruction. In assembly,
this bit can be set with the BSF T0CON0,T0EN
instruction.
1.3.2.3 Bit Fields
Bit fields are two or more adjacent bits in the same
register. For example, the four Least Significant bits of
the T0CON0 register contain the output prescaler
select bits. The short name for this field is OUTPS and
the long name is T0OUTPS. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
Timer0 output prescaler to the 1:6 Postscaler:
T0CON0bits.OUTPS = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name OUTPS3. The following two exam-
ples demonstrate assembly program sequences for
setting the Timer0 output prescaler to 1:6 Postscaler:
Example 1:
MOVLW ~(1<<OUTPS3 | 1<<OUTPS1)
ANDWF T0CON0,F
MOVLW 1<<OUTPS2 | 1<<OUTPS0
IORWF T0CON0,F
Example 2:
BCF T0CON0,OUTPS3
BSF T0CON0,OUTPS2
BCF T0CON0,OUTPS1
BSF T0CON0,OUTPS0
1.3.3 REGISTER AND BIT NAMING
EXCEPTIONS
1.3.3.1 Status, Interrupt, and Mirror Bits
Status, interrupt enables, interrupt flags, and mirror bits
are contained in registers that span more than one
peripheral. In these cases, the bit name shown is
unique so there is no prefix or short name variant.
2017-2019 Microchip Technology Inc. DS40001919E-page 23
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2.0 GUIDELINES FOR GETTING
STARTED WITH PIC18(L)F26/
27/45/46/47/55/56/57K42
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC18(L)F26/27/45/46/47/55/
56/57K42 family of 8-bit microcontrollers requires
attention to a minimal set of device pin connections
before proceeding with development.
The following pins must always be connected:
All VDD and VSS pins (see Section 2.2 “Power
Supply Pins”)
•MCLR
pin (see Section 2.3 “Master Clear (MCLR)
Pin”)
These pins must also be connected if they are being
used in the end application:
ICSPCLK/ICSPDAT pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.4 “ICSP™ Pins”)
OSCI and OSCO pins when an external oscillator
source is used (see Section 2.5 “External
Oscillator Pins”)
Additionally, the following pins may be required:
•V
REF+/VREF- pins are used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
2.2 Power Supply Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins (VDD and VSS) is required.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, make sure that the
trace length from the pin to the capacitor is no
greater than 0.25 inch (6 mm).
Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type
capacitor in parallel to the above described
decoupling capacitor. The value of the second
capacitor can be in the range of 0.01 F to
0.001 F. Place this second capacitor next to
each primary decoupling capacitor. In high-speed
circuit designs, consider implementing a decade
pair of capacitances as close to the power and
ground pins as possible (e.g., 0.1 F in parallel
with 0.001 F).
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2 TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank
capacitor for integrated circuits, including
microcontrollers, to supply a local power source. The
value of the tank capacitor should be determined based
on the trace resistance that connects the power supply
source to the device, and the maximum current drawn
by the device in the application. In other words, select
the tank capacitor so that it meets the acceptable
voltage sag at the device. Typical values range from
4.7 F to 47 F.
C1
R1
Rev. 10-000249A
9/1/2015
VDD
PIC18(L)Fxxxxx
R2
MCLR
C2
VDD
Vss
Vss
Key (all values are recommendations):
C1 and C2 : 0.1 PF, 20V ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
2017-2019 Microchip Technology Inc. DS40001919E-page 24
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2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
2.4 ICSP™ Pins
The ICSPCLK and ICSPDAT pins are used for In-
Circuit Serial Programming™ (ICSP™) and debugging
purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of ohms, not to exceed 100.
Pull-up resistors, series diodes and capacitors on the
ICSPCLK and ICSPDAT pins are not recommended as
they will interfere with the programmer/debugger
communications to the device. If such discrete
components are an application requirement, they
should be removed from the circuit during
programming and debugging. Alternatively, refer to the
AC/DC characteristics and timing requirements
information in the respective device Flash
programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., ICSPCLK/ICSPDAT pins),
programmed into the device, matches the physical
connections for the ICSP to the Microchip debugger/
emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 43.0 “Development Support”.
Note 1: R1  10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R2  470 will limit any current flowing into
MCLR from the external capacitor, C1, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C1
R2
R1
VDD
MCLR
JP PIC18(L)Fxxxxx
xx xng Secondary OsmHalur
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2.5 External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to Section
7.0 “Oscillator Module (with Fail-Safe Clock
Monitor)” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-3. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O
assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
For additional information and design guidance on
oscillator circuits, refer to these Microchip application
notes, available at the corporate website
(www.microchip.com):
• AN826, Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
AN849, “Basic PICmicro® Oscillator Design”
AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work
2.6 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 k
to 10 k resistor to VSS on unused pins and drive the
output to logic low.
FIGURE 2-3: SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
GND
`
`
`
OSC1
OSC2
SOSCO
SOSCI
Copper Pour Primary Oscillator
Crystal
Secondary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
SOSC: C1 SOSC: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
(SOSC)
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3.0 PIC18 CPU
This family of devices contains a PIC18 8-bit CPU core
based on the modified Harvard architecture. The PIC18
CPU supports:
System Arbitration, which decides memory
access allocation depending on user priorities
Vectored Interrupt capability with automatic two
level deep context saving
31-level deep hardware stack with overflow and
underflow reset capabilities
Support Direct, Indirect, and Relative Addressing
modes
8x8 Hardware Multiplier
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FIGURE 3-1: PIC18(L)F26/27/45/46/47/55/56/57K42 FAMILY BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
Address Latch
Data Address[12]
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
614 4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8x8 Multiply
8
BITOP
8
8
ALU[8]
20
8
8
Table Pointer[21]
inc/dec logic
21
8
Data Bus[8]
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
Note 1: RE3 is only available when MCLR functionality is disabled.
2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 7.0, Oscillator Module (with Fail-Safe Clock Monitor) for additional information.
W
Instruction Bus [16]
STKPTR Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
WWDT
OSC1(2)
OSC2(2)
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
MCLR(1)
Block
LFINTOSC
Oscillator
64 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
SOSCO
SOSCI
Address Latch
Program Memory
(8/16/32/64 Kbytes)
Data Latch
Ports
Peripherals
Data
EEPROM
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3.1 System Arbitration
The System Arbiter resolves memory access between
the System Level Selections (i.e., Main, Interrupt
Service Routine) and Peripheral Selection (i.e., DMA
and Scanner) based on user-assigned priorities. Each
of the system level and peripheral selections has its
own priority selection registers. Memory access priority
is resolved using the number written to the
corresponding Priority registers, 0 being the highest
priority and 4 the lowest. The default priorities are listed
in Table 3-1.
In case the user wants to change priorities, ensure
each Priority register is written with a unique value from
0 to 4.
FIGURE 3-2: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
TABLE 3-1: DEFAULT PRIORITIES
Selection Priority register
Reset value
System Level ISR 0
MAIN 1
Peripheral DMA1 2
DMA2 3
SCANNER 4
Rev. 20-000318A
11/2/2016
Data EEPROM SFR/GPR
SRAM Data
Program Flash
Memory
CPU Memory Access
NVMCON Scanner DMA 1
Priority
Program Flash Memory Data
Data EEPROM Data
SFR/GPR Data
Legend
System Arbiter
DMA 2
WW?
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3.1.1 PRIORITY LOCK
The System arbiter grants memory access to the
peripheral selections (DMAx, Scanner) when the
PRLOCKED bit (PRLOCK Register) is set.
Priority selections are locked by setting the
PRLOCKED bit of the PRLOCK register. Setting and
clearing this bit requires a special sequence as an extra
precaution against inadvertent changes. Examples of
setting and clearing the PRLOCKED bit are shown in
Example 3-1 and Example 3-2.
EXAMPLE 3-1: PRIORITY LOCK
SEQUENCE
EXAMPLE 3-2: PRIORITY UNLOCK
SEQUENCE
3.2 Memory Access Scheme
The user can assign priorities to both system level and
peripheral selections based on which the system
arbiter grants memory access. Let us consider the
following priority scenarios between ISR, MAIN, and
Peripherals.
3.2.1 ISR PRIORITY > MAIN PRIORITY >
PERIPHERAL PRIORITY
When the Peripheral Priority (DMAx, Scanner) is lower
than ISR and MAIN Priority, and the peripheral
requires:
1. Access to the Program Flash Memory, then the
peripheral waits for an instruction cycle in which
the CPU does not need to access the PFM
(such as a branch instruction) and uses that
cycle to do its own Program Flash Memory
access, unless a PFM Read/Write operation is
in progress.
2. Access to the SFR/GPR, then the peripheral
waits for an instruction cycle in which the CPU
does not need to access the SFR/GPR (such as
MOVLW, CALL, NOP) and uses that cycle to do its
own SFR/GPR access.
3. Access to the Data EEPROM, then the
peripheral has access to Data EEPROM unless
a Data EEPROM Read/Write operation is being
performed.
This results in the lowest throughput for the peripheral
to access the memory, and does so without any impact
on execution times.
3.2.2 PERIPHERAL PRIORITY > ISR
PRIORITY > MAIN PRIORITY
When the Peripheral Priority (DMAx, Scanner) is higher
than ISR and MAIN Priority, the CPU operation is
stalled when the peripheral requests memory.
The CPU is held in its current state until the peripheral
completes its operation. Since the peripheral requests
access to the bus, the peripheral cannot be disabled
until it completes its operation.
This results in the highest throughput for the peripheral
to access the memory, but has the cost of stalling other
execution while it occurs.
; Disable interrupts
BCF INTCON0,GIE
; Bank to PRLOCK register
BANKSEL PRLOCK
MOVLW 55h
; Required sequence, next 4
instructions
MOVWF PRLOCK
MOVLW AAh
MOVWF PRLOCK
; Set PRLOCKED bit to grant memory
access to peripherals
BSF PRLOCK,0
; Enable Interrupts
BSF INTCON0,GIE
; Disable interrupts
BCF INTCON0,GIE
; Bank to PRLOCK register
BANKSEL PRLOCK
MOVLW 55h
; Required sequence, next 4
instructions
MOVWF PRLOCK
MOVLW AAh
MOVWF PRLOCK
; Clear PRLOCKED bit to allow changing
priority settings
BCF PRLOCK,0
; Enable Interrupts
BSF INTCON0,GIE
Note: It is always required that the ISR priority
be higher than Main priority.
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3.2.3 ISR PRIORITY > PERIPHERAL
PRIORITY > MAIN PRIORITY
In this case, interrupt routines and peripheral operation
(DMAx, Scanner) will stall the CPU. Interrupt will
preempt peripheral operation. This results in lowest
interrupt latency and highest throughput for the
peripheral to access the memory.
3.2.4 PERIPHERAL 1 PRIORITY > ISR
PRIORITY > MAIN PRIORITY >
PERIPHERAL 2 PRIORITY
In this case, the Peripheral 1 will stall the execution of
the CPU. However, Peripheral 2 can access the
memory in cycles unused by Peripheral 1.
The operation of the System Arbiter is controlled
through the following registers:
REGISTER 3-1: ISRPR: INTERRUPT SERVICE ROUTINE PRIORITY REGISTER
REGISTER 3-2: MAINPR: MAIN ROUTINE PRIORITY REGISTER
REGISTER 3-3: DMA1PR: DMA1 PRIORITY REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— ISRPR[2:0]
bit 7 bit 0
Legend:
R = Readable bit
u = Bit is unchanged
1 = bit is set
W = Writable bit
x = Bit is unknown
0 = bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-3 Unimplemented: Read as ‘0
bit 2-0 ISRPR[2:0]: Interrupt Service Routine Priority Selection bits
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-1/1
— MAINPR[2:0]
bit 7 bit 0
Legend:
R = Readable bit
u = Bit is unchanged
1 = bit is set
W = Writable bit
x = Bit is unknown
0 = bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-3 Unimplemented: Read as ‘0
bit 2-0 MAINPR[2:0]: Main Routine Priority Selection bits
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0
— DMA1PR[2:0]
bit 7 bit 0
Legend:
R = Readable bit
u = Bit is unchanged
1 = bit is set
W = Writable bit
x = Bit is unknown
0 = bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-3 Unimplemented: Read as ‘0
bit 2-0 DMA1PR[2:0]: DMA1 Priority Selection bits
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REGISTER 3-4: DMA2PR: DMA2 PRIORITY REGISTER
REGISTER 3-5: SCANPR: SCANNER PRIORITY REGISTER
REGISTER 3-6: PRLOCK: PRIORITY LOCK REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 R/W-1/1
— DMA2PR[2:0]
bit 7 bit 0
Legend:
R = Readable bit
u = Bit is unchanged
1 = bit is set
W = Writable bit
x = Bit is unknown
0 = bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-3 Unimplemented: Read as ‘0
bit 2-0 DMA2PR[2:0]: DMA2 Priority Selection bits
U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-0/0 R/W-0/0
— SCANPR[2:0]
bit 7 bit 0
Legend:
R = Readable bit
u = Bit is unchanged
1 = bit is set
W = Writable bit
x = Bit is unknown
0 = bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-3 Unimplemented: Read as ‘0
bit 2-0 SCANPR[2:0]: Scanner Priority Selection bits
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — PRLOCKED
bit 7 bit 0
Legend:
R = Readable bit
u = Bit is unchanged
1 = bit is set
W = Writable bit
x = Bit is unknown
0 = bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-1 Unimplemented: Read as ‘0
bit 0 PRLOCKED: PR Register Lock bit(1, 2)
0 = Priority Registers can be modified by write operations; Peripherals do not have access to the
memory
1 = Priority Registers are locked and cannot be written; Peripherals have access to the memory
Note 1: The PRLOCKED bit can only be set or cleared after the unlock sequence.
2: If PR1WAY = 1, the PRLOCKED bit cannot be cleared after it has been set. A device Reset will clear the
bit and allow one more set.
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TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CPU
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
page
ISRPR — — ISRPR2 ISRPR1 ISRPR0 30
MAINPR — — MAINPR2 MAINPR1 MAINPR0 30
DMA1PR — — DMA1PR2 DMA1PR1 DMA1PR0 30
DMA2PR — — DMA2PR2 DMA2PR1 DMA2PR0 31
SCANPR — — SCANPR2 SCANPR1 SCANPR0 31
PRLOCK — — PRLOCKED 31
Legend: — = Unimplemented location, read as ‘0’.
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4.0 MEMORY ORGANIZATION
There are three types of memory in PIC18
microcontroller devices:
Program Flash Memory
Data RAM
Data EEPROM
As Harvard architecture devices, the data and program
memories use separate buses; this allows for
concurrent access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Program Flash Memory and Data EEPROM Memory is
provided in Section 13.0 “Nonvolatile Memory
(NVM) Control”.
4.1 Program Flash Memory
Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2 Mbyte
program memory space. Accessing any
unimplemented memory will return all ‘0’s (a NOP
instruction).
These devices contain the following:
PIC18(L)F45/46K42: 32 Kbytes of Flash memory,
up to 16,384 single-word instructions
PIC18(L)F26/46/56K42: 64 Kbytes of Flash
memory, up to 32,768 single-word instructions
PIC18(L)F27/47/57K42: 128 Kbytes of Flash
memory, up to 65,536 single-word instructions
The Reset vector for the device is at address 000000h.
PIC18(L)F26/27/45/46/47/55/56/57K42 devices
feature a vectored interrupt controller with a dedicated
interrupt vector table in the program memory, see
Section 9.0 “Interrupt Controller”.
4.2 Memory Access Partition (MAP)
Program Flash memory is partitioned into:
Application Block
Boot Block, and
Storage Area Flash (SAF) Block
4.2.1 APPLICATION BLOCK
Application block is where the user’s program resides
by default. Default settings of the configuration bits
(BBEN = 1 and SAFEN = 1) assign all memory in the
program Flash memory area to the application block.
The WRTAPP configuration bit is used to protect the
application block.
4.2.2 BOOT BLOCK
Boot block is an area in program memory that is ideal
for storing bootloader code. Code placed in this area
can be executed by the CPU. The boot block can be
write-protected, independent of the main application
block. The Boot Block is enabled by the BBEN bit and
size is based on the value of the BBSIZE bits of
Configuration word (Register 5-7), see Tab l e 5- 1 for
boot block sizes. The WRTB Configuration bit is used
to write-protect the Boot Block.
4.2.3 STORAGE AREA FLASH
Storage Area Flash (SAF) is the area in program
memory that can be used as data storage. SAF is
enabled by the SAFEN bit of the Configuration word in
Register 5-7. If enabled, the code placed in this area
cannot be executed by the CPU. The SAF block is
placed at the end of memory and spans 128 Words.
The WRTSAF Configuration bit is used to write-protect
the Storage Area Flash.
Note: For memory information on this family of
devices, see Ta ble 4 -1 and Tabl e 4-3 .
Note: If write-protected locations are written to,
memory is not changed and the WRERR
bit defined in Register 13-1 is set.
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TABLE 4-1: PROGRAM AND DATA EEPROM MEMORY MAP
PIC18(L)F45/46K42 PIC18(L)F26/46/56K42 PIC18(L)F27/47/57K42
PC[21:0] PC[21:0] PC[21:0]
Note 1 Stack (31 levels) Stack (31 levels) Stack (31 levels) Note 1
00 0000h Reset Vector Reset Vector Reset Vector 00 0000h
••• ••• ••• ••• •••
00 0008h Interrupt Vector High(2) Interrupt Vector High(2) Interrupt Vector High(2) 00 0008h
••• ••• ••• ••• •••
00 0018h Interrupt Vector Low(2) Interrupt Vector Low(2) Interrupt Vector Low(2) 00 0018h
00 001Ah
00 7FFFh
Program Flash Memory (16
KW)(3)
Program Flash Memory (32
KW)(3)
Program Flash Memory (64
KW)(3)
00 001Ah
00 7FFFh
00 8000h
00 FFFFh
Reserved(4)
00 8000h
00 FFFFh
01 0000h
Reserved(4)
01 0000h
01 FFFFh 01 FFFFh
02 0000h
1F FFFFh Reserved(4) 02 0000h
1F FFFFh
20 0000
•••
20 000Fh
User IDs (8 Words)(5) 20 0000h
•••
20 000Fh
20 0010h
•••
2F FFFFh
Reserved
20 0010h
•••
2F FFFFh
30 0000h
•••
30 0009h
Configuration Words (5 Words)(5) 30 0000h
•••
30 0009h
30 000Ah
•••
30 FFFFh
Reserved
30 000Ah
•••
30 FFFFh
31 0000h
•••
31 00FFh
Data EEPROM (256 Bytes)
Data EEPROM (1024Bytes)
31 0000h
•••
31 00FFh
31 0100h
•••
31 03FFh Reserved
31 0100h
•••
31 03FFh
31 0400h
•••
3E FFFFh
Reserved
31 0400h
•••
3E FFFFh
3F 0000h
•••
3F 003Fh
Device Information Area(5),(7) 3F 0000h
•••
3F 003Fh
3F0040h
•••
3F FEFFh
Reserved
3F0040h
•••
3F FEFFh
3F FF00h
•••
3F FF09h
Device Configuration Information (5 Words)(5),(6),(7) 3F FF00h
•••
3F FF09h
3F FF0Ah
•••
3F FFFBh
Reserved
3F FF0Ah
•••
3F FFFBh
3F FFFCh
•••
3F FFFDh
Revision ID (1 Word)(5),(6),(7) 3F FFFCh
•••
3F FFFDh
3F FFFEh
•••
3F FFFFh
Device ID (1 Word)(5),(6),(7) 3F FFFEh
•••
3F FFFFh
Note 1: The stack is a separate SRAM panel, apart from all user memory panels.
2: 00 0008h location is used as the reset default for the IVTBASE register, the vector table can be relocated in the
memory by programming the IVTBASE register.
3: Storage area Flash is implemented as the last 128 Words of user Flash.
4: The addresses do not roll over. The region is read as ‘0’.
5: Not code-protected.
6: Hard-coded in silicon.
7: This region cannot be written by the user and it’s not affected by a Bulk Erase.
BBEN
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TABLE 4-2: PROGRAM FLASH MEMORY PARTITION
Region Address
Partition(3)
BBEN =1
SAFEN =1
BBEN =1
SAFEN =0
BBEN =0
SAFEN =1
BBEN =0
SAFEN =0
Program
Flash
Memory
00 0000h
•••
Last Boot Block Memory
Address
APPLICATION
BLOCK
APPLICATION
BLOCK
BOOT
BLOCK
BOOT
BLOCK
Last Boot Block Memory
Address(1) + 1
•••
Last Program Memory
Address(2) - 100h APPLICATION
BLOCK
APPLICATION
BLOCK
Last Program Memory
Address(2) - FEh(4)
•••
Last Program Memory
Address(2)
STORAGE
AREA
FLASH
STORAGE
AREA
FLASH
Note 1: Last Boot Block Memory Address is based on BBSIZE[2:0], see Table 5 -1 .
2: For Last Program Memory Address, see Tab l e 4- 1 .
3: Refer to Register 5-7: Configuration Word 4L for BBEN and SAFEN definitions.
4: Storage area Flash is implemented as the last 128 Words of User Flash.
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4.2.4 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bit wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC[15:8] bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC[20:16] bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by
any operation that reads PCL. This is useful for
computed offsets to the PC (see Section
4.3.2.1 “Computed GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by two to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
4.2.5 RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer. The stack space is not part of either
program or data space. The Stack Pointer is readable
and writable and the address on the top of the stack is
readable and writable through the Top-of-Stack (TOS)
Special File Registers. Data can also be pushed to, or
popped from the stack, using these registers.
A CALL, CALLW or RCALL instruction causes a push
onto the stack; the Stack Pointer is first incremented
and the location pointed to by the Stack Pointer is
written with the contents of the PC (already pointing to
the instruction following the CALL). A RETURN type
instruction causes a pop from the stack; the contents of
the location pointed to by the STKPTR are transferred
to the PC and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits in the PCON0 register
indicate if the stack has overflowed or underflowed.
4.2.5.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is readable
and writable. A set of three registers, TOSU:TOSH:TOSL,
holds the contents of the stack location pointed to by the
STKPTR register (Figure 4-1). This allows users to
implement a software stack, if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU:TOSH:TOSL registers. These
values can be placed on a user-defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the Global Interrupt Enable (GIE)
bits while accessing the stack to prevent inadvertent
stack corruption.
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FIGURE 4-1: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
4.2.5.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 4-4) contains the Stack
Pointer value. The STKOVF (Stack Overflow) Status bit
and the STKUNF (Stack Underflow) Status bit can be
accessed using the PCON0 register. The value of the
Stack Pointer can be 0 through 31. On Reset, the Stack
Pointer value will be zero. The user may read and write
the Stack Pointer value. This feature can be used by a
Real-Time Operating System (RTOS) for stack mainte-
nance. After the PC is pushed onto the stack 32 times
(without popping any values off the stack), the
STKOVF bit is set. The STKOVF bit is cleared by soft-
ware or by a POR. The action that takes place when the
stack becomes full depends on the state of the
STVREN (Stack Overflow Reset Enable) Configuration
bit. (Refer to Section 5.1 “Configuration Words” for
a description of the device Configuration bits.)
If STVREN is set (default), a Reset will be generated
and a Stack Overflow will be indicated by the STKOVF
bit when the 32nd push is initiated. This includes CALL
and CALLW instructions, as well as stacking the return
address during an interrupt response. The STKOVF bit
will remain set and the Stack Pointer will be set to zero.
If STVREN is cleared, the STKOVF bit will be set on the
32nd push and the Stack Pointer will remain at 31 but
no Reset will occur. Any additional pushes will
overwrite the 31st push but the STKPTR will remain at
31.
Setting STKOVF = 1 in software will change the bit, but
will not generate a Reset.
The STKUNF bit is set when a stack pop returns a
value of zero. The STKUNF bit is cleared by software
or by POR. The action that takes place when the stack
becomes full depends on the state of the STVREN
(Stack Overflow Reset Enable) Configuration bit.
(Refer to Section 5.1 “Configuration Words” for a
description of the device Configuration bits).
If STVREN is set (default) and the stack has been
popped enough times to unload the stack, the next pop
will return a value of zero to the PC, it will set the
STKUNF bit and a Reset will be generated. This
condition can be generated by the RETURN, RETLW and
RETFIE instructions.
When STVREN = 0, STKUNF will be set but no Reset
will occur.
4.2.5.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack [20:0]
Top-of-Stack
000D58h
TOSLTOSHTOSU
34h1Ah00h
STKPTR[4:0]
Top-of-Stack Registers Stack Pointer
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
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4.3 Register Definitions: Stack Pointer
REGISTER 4-1: TOSU: TOP OF STACK UPPER BYTE
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—TOS[20:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0
bit 4-0 TOS[20:16]: Top of Stack Location bits
REGISTER 4-2: TOSH: TOP OF STACK HIGH BYTE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TOS[15:8]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TOS[15:8]: Top of Stack Location bits
REGISTER 4-3: TOSL: TOP OF STACK LOW BYTE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TOS[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TOS[7:0]: Top of Stack Location bits
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4.3.1 FAST REGISTER STACK
There are three levels of fast stack registers available -
one for CALL type instructions and two for interrupts. A
fast register stack is provided for the STATUS, WREG
and BSR registers, to provide a “fast return” option for
interrupts. It is loaded with the current value of the cor-
responding register when the processor vectors for an
interrupt. All interrupt sources will push values into the
stack registers. The values in the registers are then
loaded back into their associated registers if the
RETFIE, FAST instruction is used to return from the
interrupt. Refer to Section 4.5.6 “Call Shadow Regis-
ter” for interrupt call shadow registers.
Example 4-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 4-1: FAST REGISTER STACK
CODE EXAMPLE
REGISTER 4-4: STKPTR: STACK POINTER REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— STKPTR[4:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0
bit 4-0 STKPTR[4:0]: Stack Pointer Location bits
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
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4.3.2 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
Computed GOTO
Table Reads
4.3.2.1 Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 4-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of two (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 4-2: COMPUTED GOTO USING
AN OFFSET VALUE
4.3.2.2 Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the data that is read from or written to program
memory.
Table read and table write operations are discussed
further in Section 13.1.1 “Table Reads and Table
Writes”.
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
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4.4 PIC18 Instruction Cycle
4.4.1 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four cycles of the
oscillator clock. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 4-3).
A fetch cycle begins with the Program Counter (PC)
incrementing followed by the execution cycle.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR). This instruction is
then decoded and executed during the next few
oscillator clock cycles. Data memory is read (operand
read) and written (destination write) during the
execution cycle as well.
EXAMPLE 4-3: INSTRUCTION PIPELINE FLOW
Note: There are some instructions that take multiple cycles to execute. Refer to Section 41.0 “Instruction Set
Summary” for details.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
DDUUUDh DDUUUZh 000004h DDUUUBh OFh 55h DDUUUBh EFh 03h 00000An FDh 00h 0000007 Cm 23h 00000En F4h 55h 000mm. 00h 50h 000012h FM 807 DDUUMh F4h 55h 000mm. 000mm. 00001An
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4.4.2 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instructions are stored as either two bytes or four bytes
in program memory. The Least Significant Byte of an
instruction word is always stored in a program memory
location with an even address (LSb = 0). To maintain
alignment with instruction boundaries, the PC
increments in steps of two and the LSb will always read
0’ (see Section 4.2.4 “Program Counter”).
Figure 4-2 shows an example of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC[20:1],
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-2 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 41.0 “Instruction Set Summary”
provides further details of the instruction set.
4.4.3 MULTI-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LFSR and two
three-word instructions: MOVFFL and MOVSFL. In all
cases, the second and the third word of the instruction
always has ‘1111’ as its four Most Significant bits; the
other 12 bits are literal data, usually a data memory
address.
The use of ‘1111’ in the four MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
and used by the instruction sequence. If the first word
is skipped for some reason and the second or third
word is executed by itself, a NOP is executed instead.
This is necessary for cases when the multi-word
instruction is preceded by a conditional instruction that
changes the PC. Example 4-4 shows how this works.
FIGURE 4-2: INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
Instruction 4: MOVFFL 123h, 456h 00h 60h 000012h
F4h 8Ch 000014h
F4h 56h 000016h
000018h
00001Ah
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EXAMPLE 4-4: TWO-WORD INSTRUCTIONS
EXAMPLE 4-5: THREE-WORD INSTRUCTIONS
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
0000 0000 0110 0000 MOVFFL REG1, REG2 ; Yes, skip this word
1111 0100 1000 1100 ; Execute this word as a NOP
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
0000 0000 0110 0000 MOVFFL REG1, REG2 ; No, execute this word
1111 0100 1000 1100 ; 2nd word of instruction
1111 0100 0101 0110 ; 3rd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
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4.5 Data Memory Organization
Data memory in PIC18F26/27/45/46/47/55/56/57K42
devices is implemented as static RAM. Each register in
the data memory has a 14-bit address, allowing up to
16384 bytes of data memory. The memory space is
divided into 64 banks that contain 256 bytes each.
Figure 4-3 shows the data memory organization for the
PIC18F26/27/45/46/47/55/56/57K42 devices in this
data sheet.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (select SFRs
and GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to some SFRs
and the lower portion of GPR Bank 0 without using the
Bank Select Register (BSR). Section 4.5.4 “Access
Bank” provides a detailed description of the Access
RAM.
4.5.1 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 64 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 14-bit address, or an 8-bit
low-order address and a 6-bit Bank Select Register.
This SFR holds the six Most Significant bits of a
location address; the instruction itself includes the
eight Least Significant bits. Only the six lower bits of the
BSR are implemented (BSR[5:0]). The upper two bits
are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory; the eight bits in the instruction show the
location in the bank and can be thought of as an offset
from the bank’s lower boundary. The relationship
between the BSR’s value and the bank division in data
memory is shown in Figure 4-3.
Since up to 64 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 3Fh will end up corrupting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory maps in
Figure 4-3 indicate which banks are implemented.
aaoon SEFFh FGDh
2017-2019 Microchip Technology Inc. DS40001919E-page 45
PIC18(L)F26/27/45/46/47/55/56/57K42
FIGURE 4-4: DATA MEMORY MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES
Bank BSR[5:0] Address
addr[7:0] PIC18(L)F45K42
PIC18(L)F55K42
PIC18(L)F26K42
PIC18(L)F46K42
PIC18(L)F56K42
PIC18(L)F27K42
PIC18(L)F47K42
PIC18(L)F57K42
Address
addr[13:0]
Bank 0 00 0000
00h Access RAM Access RAM Access RAM 0000h
005Fh
GPR GPR GPR 0060h
FFh 00FFh
Bank 1 00 0001 00h
FFh
GPR GPR GPR
0100h
·
·
·
·
·
·
·
03FFh
Bank 2 00 0010 00h
FFh
Bank 3 00 0011
00h
·
·
·
FFh
Banks
4 to 7
00 0100
-
00 0111
00h
·
·
·
FFh
GPR GPR GPR
0400h
·
·
·
07FFh
Banks
8 to 15
00 1000
-
00 1111
00h
·
·
·
FFh
Unimplemented
GPR
GPR
0800h
·
·
·
0FFFh
Banks
16 to 31
01 0000
-
01 1111
00h
·
·
·
FFh Unimplemented
1000h
·
·
·
1FFFh
Banks
32 to 55
10 0000
-
11 0111
00h
·
·
·
FFh
Unimplemented
2000h
·
·
·
37FFh
Banks
56 to 62
11 1000
-
11 1110
00h
·
·
·
FFh
SFR SFR SFR
3800h
·
·
·
3EFFh
Bank 63 11 1111
00h
·
·
·
FFh
SFR SFR SFR
3800h
3EFFh
3F60h
3FFFh
Virtual Bank
Access RAM 00h
5Fh
SFR 60h
FFh
2017-2019 Microchip Technology Inc. DS40001919E-page 46
PIC18(L)F26/27/45/46/47/55/56/57K42
FIGURE 4-5: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR[5:0]) to the registers of the Access Bank.
Data Memory
Bank Select(2)
70
From Opcode
0000
0000h
0100h
0200h
0300h
3F00h
3E00h
3FFFh
Bank 0
Bank 1
Bank 2
Bank 62
Bank 63
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 61
0010 11111111
70
BSR(1)
2017-2019 Microchip Technology Inc. DS40001919E-page 47
PIC18(L)F26/27/45/46/47/55/56/57K42
4.5.2 GENERAL PURPOSE REGISTER
FILE
General Purpose RAM is available starting Bank 0 of
data memory. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
4.5.3 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (3FFFh) and extend downward to occupy
Bank 56 through 63 (3800h to 3FFFh). A list of these
registers is given in Ta bl e 4 -3 to Table 4-11. A bitwise
summary of these registers can be found in
Section 42.0 “Register Summary”.
4.5.4 ACCESS BANK
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 63. The lower half is known
as the “Access RAM” and is composed of GPRs. This
upper half is also where some of the SFRs of the device
are mapped. These two areas are mapped
contiguously in the Access Bank and can be addressed
linearly by an 8-bit address (Figure 4-4).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction uses the Access Bank address
map; the current value of the BSR is ignored.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient and
switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 4.8.3 Mapping the Access Bank in
Indexed Literal Offset Mode”.
E B 9376543210 E B 9376543210
2017-2019 Microchip Technology Inc. DS40001919E-page 48
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES (DMA ACCESS ONLY)
40FFh 40DFh —40BFh 409Fh 407Fh 405Fh —403Fh 401Fh
40FEh —40DEh 40BEh 409Eh —407Eh 405Eh 403Eh 401Eh
40FDh 40DDh T6PR_M2 40BDh ADRESH_M2 409Dh 407Dh 405Dh —403Dh 401Dh
40FCh 40DCh PWM5DCH_M2 40BCh ADRESL_M2 409Ch 407Ch 405Ch —403Ch 401Ch
40FBh TMR5H_M1 40DBh PWM5DCL_M2 40BBh ADPCH_M2 409Bh —407Bh 405Bh 403Bh 401Bh
40FAh TMR5L_M1 40DAh T6PR_M1 40BAh ADCLK_M1 409Ah —407Ah 405Ah 403Ah 401Ah
40F9h TMR3H_M1 40D9h CCPR1H_M2 40B9h ADACT_M1 4099h 4079h 4059h 4039h 4019h
40F8h TMR3L_M1 40D8h CCPR1L_M2 40B8h ADREF_M1 4098h 4078h 4058h 4038h 4018h
40F7h TMR1H_M1 40D7h T4PR_M4 40B7h ADCON3_M1 4097h 4077h 4057h 4037h 4017h
40F6h TMR1L_M1 40D6h PWM8DCH_M1 40B6h ADCON2_M1 4096h ADRESH_M1 4076h 4056h 4036h 4016h
40F5h 40D5h PWM8DCL_M1 40B5h ADCON1_M1 4095h ADRESL_M1 4075h 4055h 4035h 4015h
40F4h 40D4h T4PR_M3 40B4h ADCON0_M1 4094h ADPCH_M1 4074h 4054h 4034h 4014h
40F3h 40D3h PWM7DCH_M1 40B3h ADCAP_M2 4093h ADCAP_M1 4073h 4053h 4033h 4013h
40F2h 40D2h PWM7DCL_M1 40B2h ADACQH_M2 4092h ADACQH_M1 4072h 4052h 4032h 4012h
40F1h 40D1h T4PR_M2 40B1h ADACQL_M2 4091h ADACQL_M1 4071h 4051h 4031h 4011h
40F0h 40D0h CCPR4H_M1 40B0h ADPREVH_M2 4090h ADPREVH_M1 4070h 4050h 4030h 4010h
40EFh PWM8DCH_M2 40CFh CCPR4L_M1 40AFh ADPREVL_M2 408Fh ADPREVL_M1 406Fh 404Fh —402Fh 400Fh
40EEh PWM8DCL_M2 40CEh T4PR_M1 40AEh ADRPT_M2 408Eh ADRPT_M1 406Eh 404Eh 402Eh 400Eh
40EDh PWM7DCH_M2 40CDh CCPR3H_M1 40ADh ADCNT_M2 408Dh ADCNT_M1 406Dh 404Dh —402Dh 400Dh
40ECh PWM7DCL_M2 40CCh CCPR3L_M1 40ACh ADACCU_M2 408Ch ADACCU_M1 406Ch 404Ch —402Ch 400Ch
40EBh PWM6DCH_M2 40CBh T2PR_M3 40ABh ADACCH_M2 408Bh ADACCH_M1 406Bh 404Bh 402Bh 400Bh
40EAh PWM6DCL_M2 40CAh PWM6DCH_M1 40AAh ADACCL_M2 408Ah ADACCL_M1 406Ah 404Ah 402Ah 400Ah
40E9h PWM5DCH_M3 40C9h PWM6DCL_M1 40A9h ADFLTRH_M2 4089h ADFLTRH_M1 4069h 4049h 4029h 4009h
40E8h PWM5DCL_M3 40C8h T2PR_M2 40A8h ADFLTRL_M2 4088h ADFLTRL_M1 4068h 4048h 4028h 4008h
40E7h CCPR4H_M2 40C7h PWM5DCH_M1 40A7h ADSTPTH_M2 4087h ADSTPTH_M1 4067h 4047h 4027h 4007h
40E6h CCPR4L_M2 40C6h PWM5DCL_M1 40A6h ADSTPTL_M2 4086h ADSTPTL_M1 4066h 4046h 4026h 4006h
40E5h CCPR3H_M2 40C5h T2PR_M2 40A5h ADERRH_M2 4085h ADERRH_M1 4065h 4045h 4025h 4005h
40E4h CCPR3L_M2 40C4h CCPR2H_M1 40A4h ADERRL_M2 4084h ADERRL_M1 4064h 4044h 4024h 4004h
40E3h CCPR2H_M2 40C3h CCPR2L_M1 40A3h ADUTHH_M2 4083h ADUTHH_M1 4063h IOCEF_M1 4043h 4023h 4003h
40E2h CCPR2L_M2 40C2h T2PR_M1 40A2h ADUTHL_M2 4082h ADUTHL_M1 4062h IOCCF_M1 4042h 4022h 4002h
40E1h CCPR1H_M3 40C1h CCPR1H_M1 40A1h ADLTHH_M2 4081h ADLTHH_M1 4061h IOCBF_M1 4041h 4021h 4001h
40E0h CCPR1L_M3 40C0h CCPR1L_M1 40A0h ADLTHL_M2 4080h ADLTHL_M1 4060h IOCAF_M1 4040h 4020h 4000h
Note 1: Addresses in this table are accessible ONLY through DMA Source and Destination Address Registers. CPU does not have access to these registers.
E E 937654 to E B s 321
2017-2019 Microchip Technology Inc. DS40001919E-page 49
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-4: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 63
3FFFh TOSU 3FDFh INDF2 3FBFh LATF(3) 3F9Fh T4PR 3F7Fh CCP1CAP 3F5Fh CCPTMRS1 3F3Fh NCO1CLK 3F1Fh SMT1CON1
3FFEh TOSH 3FDEh POSTINC2 3FBEh LATE(2) 3F9Eh T4TMR 3F7Eh CCP1CON 3F5Eh CCPTMRS0 3F3Eh NCO1CON 3F1Eh SMT1CON0
3FFDh TOSL 3FDDh POSTDEC2 3FBDh LATD(2) 3F9Dh T5CLK 3F7Dh CCPR1H 3F5Dh 3F3Dh NCO1INCU 3F1Dh SMT1PRU
3FFCh STKPTR 3FDCh PRECIN2 3FBCh LATC 3F9Ch T5GATE 3F7Ch CCPR1L 3F5Ch 3F3Ch NCO1INCH 3F1Ch SMT1PRH
3FFBh PCLATU 3FDBh PLUSW2 3FBBh LATB 3F9Bh T5GCON 3F7Bh CCP2CAP 3F5Bh 3F3Bh NCO1INCL 3F1Bh SMT1PRL
3FFAh PCLATH 3FDAh FSR2H 3FBAh LATA 3F9Ah T5CON 3F7Ah CCP2CON 3F5Ah CWG1STR 3F3Ah NCO1ACCU 3F1Ah SMT1CPWU
3FF9h PCL 3FD9h FSR2L 3FB9h T0CON1 3F99h TMR5H 3F79h CCPR2H 3F59h CWG1AS1 3F39h NCO1ACCH 3F19h SMT1CPWH
3FF8h TBLPRTU 3FD8h STATUS 3FB8h T0CON0 3F98h TMR5L 3F78h CCPR2L 3F58h CWG1AS0 3F38h NCO1ACCL 3F18h SMT1CPWL
3FF7h TBLPTRH 3FD7h IVTBASEU 3FB7h TMR0H 3F97h T6RST 3F77h CCP3CAP 3F57h CWG1CON1 3F37h 3F17h SMT1CPRU
3FF6h TBLPTRL 3FD6h IVTBASEH 3FB6h TMR0L 3F96h T6CLK 3F76h CCP3CON 3F56h CWG1CON0 3F36h 3F16h SMT1CPRH
3FF5h TABLAT 3FD5h IVTBASEL 3FB5h T1CLK 3F95h T6HLT 3F75h CCPR3H 3F55h CWG1DBF 3F35h 3F15h SMT1CPRL
3FF4h PRODH 3FD4h IVTLOCK 3FB4h T1GATE 3F94h T6CON 3F74h CCPR3L 3F54h CWG1DBR 3F34h 3F14h SMT1TMRU
3FF3h PRODL 3FD3h INTCON1 3FB3h T1GCON 3F93h T6PR 3F73h CCP4CAP 3F53h CWG1ISM 3F33h 3F13h SMT1TMRH
3FF2h 3FD2h INTCON0 3FB2h T1CON 3F92h T6TMR 3F72h CCP4CON 3F52h CWG1CLK 3F32h 3F12h SMT1TMRL
3FF1h PCON1 3FD1h 3FB1h TMR1H 3F91h 3F71h CCPR4H 3F51h CWG2STR 3F31h —3F11h
3FF0h PCON0 3FD0h 3FB0h TMR1L 3F90h 3F70h CCPR4L 3F50h CWG2AS1 3F30h 3F10h
3FEFh INDF0 3FCFh PORTF(3) 3FAFh T2RST 3F8Fh 3F6Fh 3F4Fh CWG2AS0 3F2Fh 3F0Fh
3FEEh POSTINC0 3FCEh PORTE 3FAEh T2CLK 3F8Eh 3F6Eh PWM5CON 3F4Eh CWG2CON1 3F2Eh —3F0Eh
3FEDh POSTDEC0 3FCDh PORTD(2) 3FADh T2HLT 3F8Dh 3F6Dh PWM5DCH 3F4Dh CWG2CON0 3F2Dh —3F0Dh
3FECh PRECIN0 3FCCh PORTC 3FACh T2CON 3F8Ch 3F6Ch PWM5DCL 3F4Ch CWG2DBF 3F2Ch —3F0Ch
3FEBh PLUSW0 3FCBh PORTB 3FABh T2PR 3F8Bh —3F6Bh 3F4Bh CWG2DBR 3F2Bh —3F0Bh
3FEAh FSR0H 3FCAh PORTA 3FAAh T2TMR 3F8Ah 3F6Ah PWM6CON 3F4Ah CWG2ISM 3F2Ah —3F0Ah
3FE9h FSR0L 3FC9h 3FA9h T3CLK 3F89h 3F69h PWM6DCH 3F49h CWG2CLK 3F29h 3F09h
3FE8h WREG 3FC8h 3FA8h T3GATE 3F88h 3F68h PWM6DCL 3F48h CWG3STR 3F28h 3F08h
3FE7h INDF1 3FC7h TRISF(3) 3FA7h T3GCON 3F87h 3F67h —3F47hCWG3AS13F27h 3F07h
3FE6h POSTINC1 3FC6h TRISE(2) 3FA6h T3CON 3F86h 3F66h PWM7CON 3F46h CWG3AS0 3F26h 3F06h
3FE5h POSTDEC1 3FC5h TRISD(2) 3FA5h TMR3H 3F85h 3F65h PWM7DCH 3F45h CWG3CON1 3F25h 3F05h
3FE4h PRECIN1 3FC4h TRISC 3FA4h TMR3L 3F84h 3F64h PWM7DCL 3F44h CWG3CON0 3F24h 3F04h
3FE3h PLUSW1 3FC3h TRISB 3FA3h T4RST 3F83h 3F63h 3F43h CWG3DBF 3F23h SMT1WIN 3F03h
3FE2h FSR1H 3FC2h TRISA 3FA2h T4CLK 3F82h 3F62h PWM8CON 3F42h CWG3DBR 3F22h SMT1SIG 3F02h
3FE1h FSR1L 3FC1h 3FA1h T4HLT 3F81h 3F61h PWM8DCH 3F41h CWG3ISM 3F21h SMT1CLK 3F01h
3FE0h BSR 3FC0h 3FA0h T4CON 3F80h 3F60h PWM8DCL 3F40h CWG3CLK 3F20h SMT1STAT 3F00h
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
ADCLK ADACT ADREF ADSTAT ADcoNa ADcoNz ADcom ADCOND ADPREH ADPREL ADCAP ADACQH ADACQL ADPCH ADRESH ADRESL ADPREVH ADPREVL ADRPT ADCNT ADACCU ADACCH ADACCL ADFLTRH ADFLTRL ADSTPTH ADSTPTL ADERRH ADERRL ADUTHH ADUTHL ADLTHH CMTPCH ADLTHL CMtNCH DActcoNu thcom CMtCONO DACtCONt CM2PCH CMQNCH cMzcom cMzcoNo HLVDCDM HLVDCOND ZCDCON FVRCON CMOUT DAka-mmumm DAka-mmumm
2017-2019 Microchip Technology Inc. DS40001919E-page 50
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-5: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 62
3EFFh ADCLK 3EDFh ADLTHH 3EBFh CM1PCH 3E9Fh 3E7Fh 3E5Fh 3E3Fh 3E1Fh
3EFEh ADACT 3EDEh ADLTHL 3EBEh CM1NCH 3E9Eh DAC1CON0 3E7Eh 3E5Eh 3E3Eh 3E1Eh
3EFDh ADREF 3EDDh 3EBDh CM1CON1 3E9Dh 3E7Dh 3E5Dh 3E3Dh 3E1Dh
3EFCh ADSTAT 3EDCh 3EBCh CM1CON0 3E9Ch DAC1CON1 3E7Ch 3E5Ch 3E3Ch 3E1Ch
3EFBh ADCON3 3EDBh 3EBBh CM2PCH 3E9Bh 3E7Bh 3E5Bh 3E3Bh 3E1Bh
3EFAh ADCON2 3EDAh 3EBAh CM2NCH 3E9Ah 3E7Ah 3E5Ah 3E3Ah 3E1Ah
3EF9h ADCON1 3ED9h 3EB9h CM2CON1 3E99h 3E79h 3E59h 3E39h 3E19h
3EF8h ADCON0 3ED8h 3EB8h CM2CON0 3E98h 3E78h 3E58h 3E38h 3E18h
3EF7h ADPREH 3ED7h ADCP 3EB7h 3E97h 3E77h 3E57h 3E37h 3E17h
3EF6h ADPREL 3ED6h 3EB6h 3E96h 3E76h 3E56h 3E36h 3E16h
3EF5h ADCAP 3ED5h 3EB5h 3E95h 3E75h 3E55h 3E35h 3E15h
3EF4h ADACQH 3ED4h 3EB4h 3E94h 3E74h 3E54h 3E34h 3E14h
3EF3h ADACQL 3ED3h 3EB3h 3E93h 3E73h 3E53h 3E33h 3E13h
2EF2h 3ED2h 3EB2h 3E92h 3E72h 3E52h 3E32h 3E12h
3EF1h ADPCH 3ED1h 3EB1h 3E91h 3E71h 3E51h 3E31h 3E11h
3EF0h ADRESH 3ED0h 3EB0h 3E90h 3E70h 3E50h 3E30h 3E10h
3EEFh ADRESL 3ECFh 3EAFh 3E8Fh 3E6Fh 3E4Fh 3E2Fh 3E0Fh
3EEEh ADPREVH 3ECEh 3EAEh 3E8Eh 3E6Eh 3E4Eh 3E2Eh 3E0Eh
3EEDh ADPREVL 3ECDh 3EADh 3E8Dh 3E6Dh 3E4Dh 3E2Dh 3E0Dh
3EECh ADRPT 3ECCh 3EACh 3E8Ch 3E6Ch 3E4Ch 3E2Ch 3E0Ch
3EEBh ADCNT 3ECBh 3EABh 3E8Bh 3E6Bh 3E4Bh 3E2Bh 3E0Bh
3EEAh ADACCU 3ECAh HLVDCON1 3EAAh 3E8Ah 3E6Ah 3E4Ah 3E2Ah 3E0Ah
3EE9h ADACCH 3EC9h HLVDCON0 3EA9h 3E89h 3E69h 3E49h 3E29h 3E09h
3EE8h ADACCL 3EC8h 3EA8h 3E88h 3E68h 3E48h 3E28h 3E08h
3EE7h ADFLTRH 3EC7h 3EA7h 3E87h 3E67h 3E47h 3E27h 3E07h
3EE6h ADFLTRL 3EC6h 3EA6h 3E86h 3E66h 3E46h 3E26h 3E06h
3EE5h ADSTPTH 3EC5h 3EA5h 3E85h 3E65h 3E45h 3E25h 3E05h
3EE4h ADSTPTL 3EC4h 3EA4h 3E84h 3E64h 3E44h 3E24h 3E04h
3EE3h ADERRH 3EC3h ZCDCON 3EA3h 3E83h 3E63h 3E43h 3E23h 3E03h
3EE2h ADERRL 3EC2h 3EA2h 3E82h 3E62h 3E42h 3E22h 3E02h
3EE1h ADUTHH 3EC1h FVRCON 3EA1h 3E81h 3E61h 3E41h 3E21h 3E01h
3EE0h ADUTHL 3EC0h CMOUT 3EA0h 3E80h 3E60h 3E40h 3E20h 3E00h
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
2017-2019 Microchip Technology Inc. DS40001919E-page 51
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-6: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 61
3DFFh 3DDFh U2FIFO 3DBFh —3D9Fh—3D7Fh 3D5Fh I2C2CON2 3D3Fh —3D1Fh
3DFEh 3DDEh U2BRGH 3DBEh —3D9Eh—3D7Eh 3D5Eh I2C2CON1 3D3Eh —3D1Eh
3DFDh 3DDDh U2BRGL 3DBDh 3D9Dh 3D7Dh 3D5Dh I2C2CON0 3D3Dh 3D1Dh
3DFCh 3DDCh U2CON2 3DBCh 3D9Ch 3D7Ch I2C1BTO 3D5Ch I2C2ADR3 3D3Ch 3D1Ch SPI1CLK
3DFBh 3DDBh U2CON1 3DBBh —3D9Bh 3D7Bh I2C1CLK 3D5Bh I2C2ADR2 3D3Bh 3D1Bh SPI1INTE
3DFAh U1ERRIE 3DDAh U2CON0 3DBAh —3D9Ah 3D7Ah I2C1PIE 3D5Ah I2C2ADR1 3D3Ah 3D1Ah SPI1INTF
3DF9h U1ERRIR 3DD9h —3DB9h 3D99h 3D79h I2C1PIR 3D59h I2C2ADR0 3D39h 3D19h SPI1BAUD
3DF8h U1UIR 3DD8h U2P3L 3DB8h 3D98h 3D78h I2C1STAT1 3D58h I2C2ADB1 3D38h 3D18h SPI1TWIDTH
3DF7h U1FIFO 3DD7h —3DB7h 3D97h 3D77h I2C1STAT0 3D57h I2C2ADB0 3D37h 3D17h SPI1STATUS
3DF6h U1BRGH 3DD6h U2P2L 3DB6h 3D96h 3D76h I2C1ERR 3D56h I2C2CNT 3D36h 3D16h SPI1CON2
3DF5h U1BRGL 3DD5h —3DB5h 3D95h 3D75h I2C1CON2 3D55h I2C2TXB 3D35h 3D15h SPI1CON1
3DF4h U1CON2 3DD4h U2P1L 3DB4h 3D94h 3D74h I2C1CON1 3D54h I2C2RXB 3D34h 3D14h SPI1CON0
3DF3h U1CON1 3DD3h —3DB3h 3D93h 3D73h I2C1CON0 3D53h —3D33h 3D13h SPI1TCNTH
3DF2h U1CON0 3DD2h U2TXB 3DB2h 3D92h 3D72h I2C1ADR3 3D52h —3D32h 3D12h SPI1TCNTL
3DF1h U1P3H 3DD1h —3DB1h 3D91h 3D71h I2C1ADR2 3D51h —3D31h—3D11hSPI1TXB
3DF0h U1P3L 3DD0h U2RXB 3DB0h 3D90h 3D70h I2C1ADR1 3D50h —3D30h 3D10h SPI1RXB
3DEFh U1P2H 3DCFh —3DAFh—3D8Fh 3D6Fh I2C1ADR0 3D4Fh —3D2Fh—3D0Fh
3DEEh U1P2L 3DCEh —3DAEh—3D8Eh 3D6Eh I2C1ADB1 3D4Eh —3D2Eh—3D0Eh
3DEDh U1P1H 3DCDh 3DADh 3D8Dh 3D6Dh I2C1ADB0 3D4Dh 3D2Dh 3D0Dh
3DECh U1P1L 3DCCh 3DACh 3D8Ch 3D6Ch I2C1CNT 3D4Ch 3D2Ch 3D0Ch
3DEBh U1TXCHK 3DCBh —3DABh—3D8Bh 3D6Bh I2C1TXB 3D4Bh —3D2Bh—3D0Bh
3DEAh U1TXB 3DCAh —3DAAh—3D8Ah 3D6Ah I2C1RXB 3D4Ah —3D2Ah—3D0Ah
3DE9h U1RXCHK 3DC9h —3DA9h 3D89h 3D69h —3D49h—3D29h—3D09h
3DE8h U1RXB 3DC8h —3DA8h 3D88h 3D68h —3D48h—3D28h—3D08h
3DE7h 3DC7h —3DA7h 3D87h 3D67h —3D47h—3D27h—3D07h
3DE6h 3DC6h —3DA6h 3D86h 3D66h I2C2BTO 3D46h —3D26h—3D06h
3DE5h 3DC5h —3DA5h 3D85h 3D65h I2C2CLK 3D45h —3D25h—3D05h
3DE4h 3DC4h —3DA4h 3D84h 3D64h I2C2PIE 3D44h —3D24h—3D04h
3DE3h 3DC3h —3DA3h 3D83h 3D63h I2C2PIR 3D43h —3D23h—3D03h
3DE2h U2ERRIE 3DC2h —3DA2h 3D82h 3D62h I2C2STAT1 3D42h —3D22h—3D02h
3DE1h U2ERRIR 3DC1h —3DA1h 3D81h 3D61h I2C2STAT0 3D41h —3D21h—3D01h
3DE0h U2UIR 3DC0h —3DA0h 3D80h 3D60h I2C2ERR 3D40h —3D20h—3D00h
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
B 6543210 E B 9376543210
2017-2019 Microchip Technology Inc. DS40001919E-page 52
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-7: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 60
3CFFh —3CDFh—3CBFh—3C9Fh—3C7Fh 3C5Fh CLC4GLS3 3C3Fh —3C1Fh
3CFEh MD1CARH 3CDEh —3CBEh—3C9Eh 3C7Eh CLCDATA0 3C5Eh CLC4GLS2 3C3Eh —3C1Eh
3CFDh MD1CARL 3CDDh —3CBDh 3C9Dh 3C7Dh CLC1GLS3 3C5Dh CLC4GLS1 3C3Dh 3C1Dh
3CFCh MD1SRC 3CDCh —3CBCh 3C9Ch 3C7Ch CLC1GLS2 3C5Ch CLC4GLS0 3C3Ch 3C1Ch
3CFBh MD1CON1 3CDBh —3CBBh—3C9Bh 3C7Bh CLC1GLS1 3C5Bh CLC4SEL3 3C3Bh —3C1Bh
3CFAh MD1CON0 3CDAh —3CBAh—3C9Ah 3C7Ah CLC1GLS0 3C5Ah CLC4SEL2 3C3Ah —3C1Ah
3CF9h 3CD9h —3CB9h—3C99h 3C79h CLC1SEL3 3C59h CLC4SEL1 3C39h 3C19h
3CF8h 3CD8h —3CB8h—3C98h 3C78h CLC1SEL2 3C58h CLC4SEL0 3C38h 3C18h
3CF7h 3CD7h —3CB7h—3C97h 3C77h CLC1SEL1 3C57h CLC4POL 3C37h 3C17h
3CF6h 3CD6h —3CB6h—3C96h 3C76h CLC1SEL0 3C56h CLC4CON 3C36h 3C16h
3CF5h 3CD5h —3CB5h—3C95h 3C75h CLC1POL 3C55h —3C35h 3C15h
3CF4h 3CD4h —3CB4h—3C94h 3C74h CLC1CON 3C54h —3C34h 3C14h
3CF3h 3CD3h —3CB3h—3C93h 3C73h CLC2GLS3 3C53h —3C33h 3C13h
3CF2h 3CD2h —3CB2h—3C92h 3C72h CLC2GLS2 3C52h —3C32h 3C12h
3CF1h 3CD1h —3CB1h—3C91h 3C71h CLC2GLS1 3C51h —3C31h—3C11h
3CF0h 3CD0h —3CB0h—3C90h 3C70h CLC2GLS0 3C50h —3C30h 3C10h
3CEFh —3CCFh—3CAFh—3C8Fh 3C6Fh CLC2SEL3 3C4Fh —3C2Fh—3C0Fh
3CEEh 3CCEh —3CAEh—3C8Eh 3C6Eh CLC2SEL2 3C4Eh —3C2Eh—3C0Eh
3CEDh 3CCDh —3CADh 3C8Dh 3C6Dh CLC2SEL1 3C4Dh —3C2Dh 3C0Dh
3CECh 3CCCh —3CACh 3C8Ch 3C6Ch CLC2SEL0 3C4Ch —3C2Ch 3C0Ch
3CEBh 3CCBh —3CABh—3C8Bh 3C6Bh CLC2POL 3C4Bh —3C2Bh—3C0Bh
3CEAh 3CCAh —3CAAh—3C8Ah 3C6Ah CLC2CON 3C4Ah —3C2Ah—3C0Ah
3CE9h 3CC9h —3CA9h—3C89h 3C69h CLC3GLS3 3C49h —3C29h 3C09h
3CE8h 3CC8h —3CA8h—3C88h 3C68h CLC3GLS2 3C48h —3C28h 3C08h
3CE7h 3CC7h —3CA7h—3C87h 3C67h CLC3GLS1 3C47h —3C27h 3C07h
3CE6h CLKRCLK 3CC6h —3CA6h—3C86h 3C66h CLC3GLS0 3C46h —3C26h 3C06h
3CE5h CLKRCON 3CC5h —3CA5h—3C85h 3C65h CLC3SEL3 3C45h —3C25h 3C05h
3CE4h 3CC4h —3CA4h—3C84h 3C64h CLC3SEL2 3C44h —3C24h 3C04h
3CE3h 3CC3h —3CA3h—3C83h 3C63h CLC3SEL1 3C43h —3C23h 3C03h
3CE2h 3CC2h —3CA2h—3C82h 3C62h CLC3SEL0 3C42h —3C22h 3C02h
3CE1h 3CC1h —3CA1h—3C81h 3C61h CLC3POL 3C41h —3C21h 3C01h
3CE0h 3CC0h —3CA0h—3C80h 3C60h CLC3CON 3C40h —3C20h 3C00h
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
E B 9376543210 E B 9376543210
2017-2019 Microchip Technology Inc. DS40001919E-page 53
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-8: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 59
3BFFh DMA1SIRQ 3BDFh DMA2SIRQ 3BBFh —3B9Fh—3B7Fh—3B5Fh—3B3Fh—3B1Fh
3BFEh DMA1AIRQ 3BDEh DMA2AIRQ 3BBEh —3B9Eh—3B7Eh 3B5Eh —3B3Eh—3B1Eh
3BFDh DMA1CON1 3BDDh DMA2CON1 3BBDh —3B9Dh—3B7Dh—3B5Dh—3B3Dh—3B1Dh
3BFCh DMA1CON0 3BDCh DMA2CON0 3BBCh —3B9Ch—3B7Ch—3B5Ch—3B3Ch—3B1Ch
3BFBh DMA1SSAU 3BDBh DMA2SSAU 3BBBh —3B9Bh—3B7Bh 3B5Bh —3B3Bh—3B1Bh
3BFAh DMA1SSAH 3BDAh DMA2SSAH 3BBAh —3B9Ah—3B7Ah 3B5Ah —3B3Ah—3B1Ah
3BF9h DMA1SSAL 3BD9h DMA2SSAL 3BB9h —3B99h 3B79h —3B59h—3B39h 3B19h
3BF8h DMA1SSZH 3BD8h DMA2SSZH 3BB8h —3B98h 3B78h —3B58h—3B38h 3B18h
3BF7h DMA1SSZL 3BD7h DMA2SSZL 3BB7h —3B97h 3B77h —3B57h—3B37h 3B17h
3BF6h DMA1SPTRU 3BD6h DMA2SPTRU 3BB6h —3B96h 3B76h —3B56h—3B36h 3B16h
3BF5h DMA1SPTRH 3BD5h DMA2SPTRH 3BB5h —3B95h 3B75h —3B55h—3B35h 3B15h
3BF4h DMA1SPTRL 3BD4h DMA2SPTRL 3BB4h —3B94h 3B74h —3B54h—3B34h 3B14h
3BF3h DMA1SCNTH 3BD3h DMA2SCNTH 3BB3h —3B93h 3B73h —3B53h—3B33h 3B13h
3BF2h DMA1SCNTL 3BD2h DMA2SCNTL 3BB2h —3B92h 3B72h —3B52h—3B32h 3B12h
3BF1h DMA1DSAH 3BD1h DMA2DSAH 3BB1h —3B91h 3B71h —3B51h—3B31h—3B11h
3BF0h DMA1DSAL 3BD0h DMA2DSAL 3BB0h —3B90h 3B70h —3B50h—3B30h 3B10h
3BEFh DMA1DSZH 3BCFh DMA2DSZH 3BAFh —3B8Fh—3B6Fh—3B4Fh—3B2Fh—3B0Fh
3BEEh DMA1DSZL 3BCEh DMA2DSZL 3BAEh —3B8Eh—3B6Eh 3B4Eh —3B2Eh—3B0Eh
3BEDh DMA1DPTRH 3BCDh DMA2DPTRH 3BADh —3B8Dh—3B6Dh—3B4Dh—3B2Dh—3B0Dh
3BECh DMA1DPTRL 3BCCh DMA2DPTRL 3BACh —3B8Ch—3B6Ch—3B4Ch—3B2Ch—3B0Ch
3BEBh DMA1DCNTH 3BCBh DMA2DCNTH 3BABh —3B8Bh—3B6Bh 3B4Bh —3B2Bh—3B0Bh
3BEAh DMA1DCNTL 3BCAh DMA2DCNTL 3BAAh —3B8Ah—3B6Ah 3B4Ah —3B2Ah—3B0Ah
3BE9h DMA1BUF 3BC9h DMA2BUF 3BA9h —3B89h 3B69h —3B49h—3B29h 3B09h
3BE8h —3BC8h—3BA8h—3B88h 3B68h —3B48h—3B28h 3B08h
3BE7h —3BC7h—3BA7h—3B87h 3B67h —3B47h—3B27h 3B07h
3BE6h —3BC6h—3BA6h—3B86h 3B66h —3B46h—3B26h 3B06h
3BE5h —3BC5h—3BA5h—3B85h 3B65h —3B45h—3B25h 3B05h
3BE4h —3BC4h—3BA4h—3B84h 3B64h —3B44h—3B24h 3B04h
3BE3h —3BC3h—3BA3h—3B83h 3B63h —3B43h—3B23h 3B03h
3BE2h —3BC2h—3BA2h—3B82h 3B62h —3B42h—3B22h 3B02h
3BE1h —3BC1h—3BA1h—3B81h 3B61h —3B41h—3B21h 3B01h
3BE0h —3BC0h—3BA0h—3B80h 3B60h —3B40h—3B20h 3B00h
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
ssssssss
2017-2019 Microchip Technology Inc. DS40001919E-page 54
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-9: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 58
3AFFh 3ADFh SPI1SDIPPS 3ABFh PPSLOCK 3A9Fh —3A7Fh—3A5Fh—3A3Fh 3A1Fh RD7PPS(2)
3AFEh 3ADEh SPI1SCKPPS 3ABEh (4) 3A9Eh —3A7Eh 3A5Eh —3A3Eh 3A1Eh RD6PPS(2)
3AFDh 3ADDh ADACTPPS 3ABDh —3A9Dh—3A7Dh—3A5Dh—3A3Dh 3A1Dh RD5PPS(2)
3AFCh 3ADCh CLCIN3PPS 3ABCh —3A9Ch—3A7Ch—3A5Ch—3A3Ch 3A1Ch RD4PPS(2)
3AFBh 3ADBh CLCIN2PPS 3ABBh —3A9Bh 3A7Bh RD1I2C(2) 3A5Bh RB2I2C 3A3Bh 3A1Bh RD3PPS(2)
3AFAh 3ADAh CLCIN1PPS 3ABAh —3A9Ah 3A7Ah RD0I2C(2) 3A5Ah RB1I2C 3A3Ah 3A1Ah RD2PPS(2)
3AF9h 3AD9h CLCIN0PPS 3AB9h —3A99h(4) 3A79h (4) 3A59h (4) 3A39h 3A19h RD1PPS(2)
3AF8h 3AD8h MD1SRCPPS 3AB8h —3A98h(4) 3A78h (4) 3A58h (4) 3A38h 3A18h RD0PPS(2)
3AF7h 3AD7h MD1CARHPPS 3AB7h —3A97h 3A77h 3A57h IOCBF 3A37h 3A17h RC7PPS
3AF6h 3AD6h MD1CARLPPS 3AB6h —3A96h 3A76h 3A56h IOCBN 3A36h 3A16h RC6PPS
3AF5h 3AD5h CWG3INPPS 3AB5h —3A95h 3A75h 3A55h IOCBP 3A35h 3A15h RC5PPS
3AF4h 3AD4h CWG2INPPS 3AB4h —3A94hINLVLF
(3) 3A74h INLVLD(2) 3A54h INLVLB 3A34h 3A14h RC4PPS
3AF3h 3AD3h CWG1INPPS 3AB3h 3A93h SLRCONF(3) 3A73h SLRCOND(2) 3A53h SLRCONB 3A33h 3A13h RC3PPS
3AF2h 3AD2h SMT1SIGPPS 3AB2h 3A92h ODCONF(3) 3A72h ODCOND(2) 3A52h ODCONB 3A32h 3A12h RC2PPS
3AF1h 3AD1h SMT1WINPPS 3AB1h —3A91hWPUF
(3) 3A71h WPUD(2) 3A51h WPUB 3A31h 3A11h RC1PPS
3AF0h 3AD0h CCP4PPS 3AB0h 3A90h ANSELF(3) 3A70h ANSELD(2) 3A50h ANSELB 3A30h 3A10h RC0PPS
3AEFh 3ACFh CCP3PPS 3AAFh —3A8Fh—3A6Fh—3A4Fh 3A2Fh RF7PPS(3) 3A0Fh RB7PPS
3AEEh 3ACEh CCP2PPS 3AAEh —3A8Eh—3A6Eh 3A4Eh 3A2Eh RF6PPS(3) 3A0Eh RB6PPS
3AEDh 3ACDh CCP1PPS 3AADh —3A8Dh—3A6Dh—3A4Dh 3A2Dh RF5PPS(3) 3A0Dh RB5PPS
3AECh 3ACCh T6INPPS 3AACh —3A8Ch—3A6Ch—3A4Ch 3A2Ch RF4PPS(3) 3A0Ch RB4PPS
3AEBh 3ACBh T4INPPS 3AABh —3A8Bh 3A6Bh RC4I2C 3A4Bh 3A2Bh RF3PPS(3) 3A0Bh RB3PPS
3AEAh 3ACAh T2INPPS 3AAAh —3A8Ah 3A6Ah RC3I2C 3A4Ah 3A2Ah RF2PPS(3) 3A0Ah RB2PPS
3AE9h U2CTSPPS 3AC9h T5GPPS 3AA9h —3A89h(4) 3A69h (4) 3A49h (4) 3A29h RF1PPS(3) 3A09h RB1PPS
3AE8h U2RXPPS 3AC8h T5CKIPPS 3AA8h —3A88h(4) 3A68h (4) 3A48h (4) 3A28h RF0PPS(3) 3A08h RB0PPS
3AE7h 3AC7h T3GPPS 3AA7h 3A87h IOCEF 3A67h IOCCF 3A47h IOCAF 3A27h 3A07h RA7PPS
3AE6h U1CTSPPS 3AC6h T3CKIPPS 3AA6h 3A86h IOCEN 3A66h IOCCN 3A46h IOCAN 3A26h 3A06h RA6PPS
3AE5h U1RXPPS 3AC5h T1GPPS 3AA5h 3A85h IOCEP 3A65h IOCCP 3A45h IOCAP 3A25h 3A05h RA5PPS
3AE4h I2C2SDAPPS 3AC4h T1CKIPPS 3AA4h 3A84h INLVLE 3A64h INLVLC 3A44h INLVLA 3A24h 3A04h RA4PPS
3AE3h I2C2SCLPPS 3AC3h T0CKIPPS 3AA3h 3A83h SLRCONE(2) 3A63h SLRCONC 3A43h SLRCONA 3A23h 3A03h RA3PPS
3AE2h I2C1SDAPPS 3AC2h INT2PPS 3AA2h 3A82h ODCONE(2) 3A62h ODCONC 3A42h ODCONA 3A22h RE2PPS(2) 3A02h RA2PPS
3AE1h I2C1SCLPPS 3AC1h INT1PPS 3AA1h 3A81h WPUE 3A61h WPUC 3A41h WPUA 3A21h RE1PPS(2) 3A01h RA1PPS
3AE0h SPI1SSPPS 3AC0h INT0PPS 3AA0h 3A80h ANSELE(2) 3A60h ANSELC 3A40h ANSELA 3A20h RE0PPS(2) 3A00h RA0PPS
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
4: Reserved, maintain as ‘0’.
9376543210 E B 9376543210
2017-2019 Microchip Technology Inc. DS40001919E-page 55
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-10: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 57
39FFh 39DFh OSCFRQ 39BFh 399Fh 397Fh 395Fh WDTU 393Fh 391Fh
39FEh 39DEh OSCTUNE 39BEh 399Eh —397Eh 395Eh WDTH 393Eh 391Eh
39FDh 39DDh OSCEN 39BDh 399Dh 397Dh SCANTRIG 395Dh WDTL 393Dh 391Dh
39FCh 39DCh OSCSTAT 39BCh 399Ch 397Ch SCANCON0 395Ch WDTCON1 393Ch 391Ch
39FBh 39DBh OSCCON3 39BBh 399Bh 397Bh SCANHADRU 395Bh WDTCON0 393Bh 391Bh
39FAh 39DAh OSCCON2 39BAh 399Ah PIE10 397Ah SCANHADRH 395Ah 393Ah 391Ah
39F9h 39D9h OSCCON1 39B9h 3999h PIE9 3979h SCANHADRL 3959h 3939h 3919h
39F8h 39D8h CPUDOZE 39B8h 3998h PIE8 3978h SCANLADRU 3958h 3938h 3918h
39F7h SCANPR 39D7h 39B7h 3997h PIE7 3977h SCANLADRH 3957h 3937h 3917h
39F6h 39D6h 39B6h 3996h PIE6 3976h SCANLADRL 3956h 3936h 3916h
39F5h 39D5h 39B5h — 3995h PIE5 3975h — 3955h — 3935h 3915h
39F4h DMA2PR 39D4h 39B4h — 3994h PIE4 3974h — 3954h — 3934h — 3914h
39F3h DMA1PR 39D3h 39B3h — 3993h PIE3 3973h — 3953h — 3933h — 3913h
39F2h MAINPR 39D2h 39B2h — 3992h PIE2 3972h — 3952h — 3932h — 3912h
39F1h ISRPR 39D1h VREGCON(1) 39B1h — 3991h PIE1 3971h — 3951h — 3931h 3911h
39F0h 39D0h BORCON 39B0h — 3990h PIE0 3970h — 3950h — 3930h — 3910h
39EFh PRLOCK 39CFh —39AFh 398Fh 396Fh 394Fh —392Fh 390Fh
39EEh —39CEh 39AEh 398Eh —396Eh 394Eh 392Eh 390Eh
39EDh 39CDh —39ADh 398Dh 396Dh 394Dh 392Dh 390Dh
39ECh 39CCh —39ACh 398Ch 396Ch 394Ch 392Ch 390Ch
39EBh —39CBh 39ABh 398Bh —396Bh 394Bh 392Bh 390Bh
39EAh —39CAh 39AAh PIR10 398Ah IPR10 396Ah 394Ah 392Ah 390Ah
39E9h 39C9h 39A9h PIR9 3989h IPR9 3969h CRCCON1 3949h 3929h 3909h
39E8h 39C8h 39A8h PIR8 3988h IPR8 3968h CRCCON0 3948h 3928h 3908h
39E7h 39C7h PMD7 39A7h PIR7 3987h IPR7 3967h CRCXORH 3947h 3927h 3907h
39E6h NVMCON2 39C6h PMD6 39A6h PIR6 3986h IPR6 3966h CRCXORL 3946h 3926h 3906h
39E5h NVMCON1 39C5h PMD5 39A5h PIR5 3985h IPR5 3965h CRCSHIFTH 3945h 3925h 3905h
39E4h 39C4h PMD4 39A4h PIR4 3984h IPR4 3964h CRCSHIFTL 3944h 3924h 3904h
39E3h NVMDAT 39C3h PMD3 39A3h PIR3 3983h IPR3 3963h CRCACCH 3943h 3923h 3903h
39E2h 39C2h PMD2 39A2h PIR2 3982h IPR2 3962h CRCACCL 3942h 3922h 3902h
39E1h NVMADRH(4)39C1h PMD1 39A1h PIR1 3981h IPR1 3961h CRCDATH 3941h 3921h 3901h
39E0h NVMADRL 39C0h PMD0 39A0h PIR0 3980h IPR0 3960h CRCDATL 3940h 3920h 3900h
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
4: Unimplemented in PIC18(L)F45/46K42.
E B 9376543210 E B 9376543210
2017-2019 Microchip Technology Inc. DS40001919E-page 56
PIC18(L)F26/27/45/46/47/55/56/57K42
TABLE 4-11: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F26/27/45/46/47/55/56/57K42 DEVICES BANK 56
38FFh 38DFh —38BFh 389Fh IVTADU 387Fh 385Fh —383Fh 381Fh
38FEh —38DEh 38BEh 389Eh IVTADH 387Eh 385Eh 383Eh 381Eh
38FDh 38DDh —38BDh 389Dh IVTADL 387Dh 385Dh 383Dh 381Dh
38FCh 38DCh —38BCh 389Ch 387Ch 385Ch 383Ch 381Ch
38FBh —38DBh 38BBh 389Bh —387Bh 385Bh 383Bh 381Bh
38FAh —38DAh 38BAh 389Ah —387Ah 385Ah 383Ah 381Ah
38F9h 38D9h 38B9h 3899h 3879h 3859h 3839h 3819h
38F8h 38D8h 38B8h 3898h 3878h 3858h 3838h 3818h
38F7h 38D7h 38B7h 3897h 3877h 3857h 3837h 3817h
38F6h 38D6h 38B6h 3896h 3876h 3856h 3836h 3816h
38F5h 38D5h 38B5h 3895h 3875h 3855h 3835h 3815h
38F4h 38D4h 38B4h 3894h 3874h 3854h 3834h 3814h
38F3h 38D3h 38B3h 3893h 3873h 3853h 3833h 3813h
38F2h 38D2h 38B2h 3892h 3872h 3852h 3832h 3812h
38F1h 38D1h 38B1h 3891h 3871h 3851h 3831h 3811h
38F0h 38D0h 38B0h 3890h PRODH_SHAD 3870h 3850h 3830h 3810h
38EFh 38CFh —38AFh 388Fh PRODL_SHAD 386Fh 384Fh —382Fh 380Fh
38EEh —38CEh 38AEh 388Eh FSR2H_SHAD 386Eh 384Eh 382Eh 380Eh
38EDh 38CDh —38ADh 388Dh FSR2L_SHAD 386Dh 384Dh 382Dh 380Dh
38ECh 38CCh —38ACh 388Ch FSR1H_SHAD 386Ch 384Ch 382Ch 380Ch
38EBh —38CBh 38ABh 388Bh FSR1L_SHAD 386Bh 384Bh 382Bh 380Bh
38EAh —38CAh 38AAh 388Ah FSR0H_SHAD 386Ah 384Ah 382Ah 380Ah
38E9h 38C9h 38A9h — 3889h FSR0L_SHAD 3869h — 3849h — 3829h — 3809h
38E8h 38C8h 38A8h 3888h PCLATU_SHAD 3868h 3848h 3828h 3808h
38E7h 38C7h 38A7h 3887h PCLATH_SHAD 3867h 3847h 3827h 3807h
38E6h 38C6h 38A6h 3886h BSR_SHAD 3866h 3846h 3826h 3806h
38E5h 38C5h 38A5h 3885h WREG_SHAD 3865h 3845h 3825h 3805h
38E4h 38C4h 38A4h 3884h STATUS_SHAD 3864h 3844h 3824h 3804h
38E3h 38C3h 38A3h 3883h SHADCON 3863h 3843h 3823h 3803h
38E2h 38C2h 38A2h 3882h BSR_CSHAD 3862h 3842h 3822h 3802h
38E1h 38C1h 38A1h 3881h WREG_CSHAD 3861h 3841h 3821h 3801h
38E0h 38C0h 38A0h 3880h STATUS_CSHAD 3860h 3840h 3820h 3800h
Legend: Unimplemented data memory locations and registers, read as ‘0’.
Note 1: Unimplemented in LF devices.
2: Unimplemented in PIC18(L)F26/27K42.
3: Unimplemented in PIC18(L)F26/27/45/46/47K42.
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4.5.5 STATUS REGISTER
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
If the STATUS register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, the
results of the instruction are not written; instead, the
STATUS register is updated according to the
instruction performed. Therefore, the result of an
instruction with the STATUS register as its destination
may be different than intended. As an example, CLRF
STATUS will set the Z bit and leave the remaining
Status bits unchanged (‘0uuu u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF,
MOVWF and MOVFFL instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C, DC, OV or N bits in the STATUS
register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Section
41.2 “Extended Instruction Set” and Tab le 41 - 3.
4.5.6 CALL SHADOW REGISTER
When CALL instruction is used, the WREG, BSR and
STATUS are automatically saved in hardware and can
be accessed using the WREG_CSHAD, BSR_CSHAD
and STATUS_CSHAD registers.
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
Note: The contents of these registers should be
handled correctly to avoid erroneous code
execution.
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4.6 Register Definitions: Status Registers
REGISTER 4-2: STATUS: STATUS REGISTER
U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
—TOPD NOV Z DC C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0
bit 6 TO: Time-Out bit
1 = Set at power-up or by execution of CLRWDT or SLEEP instruction
0 = A WDT time-out occurred
bit 5 PD: Power-Down bit
1 = Set at power-up or by execution of CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 4 N: Negative bit used for signed arithmetic (2’s complement); indicates if the result is negative,
(ALU MSb = 1).
1 = The result is negative
0 = The result is positive
bit 3 OV: Overflow bit used for signed arithmetic (2’s complement); indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for current signed arithmetic operation
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1,2)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
2: For Rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the Source
register.
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4.7 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
•Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in detail in Section 4.8.1 “Indexed
Addressing with Literal Offset”.
4.7.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 4.8 “Data Memory
and the Extended Instruction Set” for
more information.
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4.7.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and byte-
oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 4.5.2 “General
Purpose Register File”) or a location in the Access
Bank (Section 4.5.4 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 4.5.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 14-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFFL, include the entire
14-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its
original contents. When ‘d’ is ‘0’, the results are stored
in the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
4.7.3 INDIRECT ADDRESSING
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations which are to be read
or written. Since the FSRs are themselves located in
RAM as Special File Registers, they can also be
directly manipulated under program control. This
makes FSRs very useful in implementing data
structures, such as tables and arrays in data memory.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 4-6.
EXAMPLE 4-6: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
4.7.3.1 FSR Registers and the INDF
Operand
At the core of indirect addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. Each FSR
pair holds a 14-bit value, therefore, the two upper bits
of the FSRnH register are not used. The 14-bit FSR
value can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers; they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses the data addressed by its
corresponding FSR register pair. A read from INDF1,
for example, reads the data at the address indicated by
FSR1H:FSR1L. Instructions that use the INDF
registers as operands actually use the contents of their
corresponding FSR as a pointer to the instruction’s
target. The INDF operand is just a convenient way of
using the pointer.
Because indirect addressing uses a full 14-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
mm ,
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4.7.3.2 FSR Registers, POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers which cannot be directly
read or written. Accessing these registers actually
accesses the location to which the associated FSR
register pair points, and also performs a specific action
on the FSR value. They are:
POSTDEC: accesses the location to which the
FSR points, then automatically decrements the
FSR by 1 afterwards
POSTINC: accesses the location to which the
FSR points, then automatically increments the
FSR by 1 afterwards
PREINC: automatically increments the FSR by 1,
then uses the location to which the FSR points in
the operation
PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the location to which the result points in the
operation.
In this context, accessing an INDF register uses the
value in the associated FSR register without changing
it. Similarly, accessing a PLUSW register gives the
FSR value an offset by that in the W register; however,
neither W nor the FSR is actually changed in the
operation. Accessing the other virtual registers
changes the value of the FSR register.
FIGURE 4-6: INDIRECT ADDRESSING
FSR1H:FSR1L
0
7
Data Memory
0000h
0100h
0200h
0300h
3F00h
3E00h
3FFFh
Bank 0
Bank 1
Bank 2
Bank 62
Bank 63
Bank 3
through
Bank 61
ADDWF, INDF1, 1
07
Using an instruction with one of the
indirect addressing registers as the
operand....
...uses the 14-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
3ECCh. This means the contents of
location 3ECCh will be added to that
of the W register and stored back in
3ECCh.
xx111110 11001100
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Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is,
rollovers of the FSRnL register from FFh to 00h carry
over to the FSRnH register. On the other hand, results
of these operations do not change the value of any
flags in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
4.7.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
3FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to either
the INDF2 or POSTDEC2 register will write the same
value to the FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly, operations by indirect addressing are generally
permitted on all other SFRs. Users should exercise the
appropriate caution that they do not inadvertently change
settings that might affect the operation of the device.
4.8 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing.
Specifically, the use of the Access Bank for many of the
core PIC18 instructions is different; this is due to the
introduction of a new addressing mode for the data
memory space.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
4.8.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
The use of the Access Bank is forced (‘a’ = 0) and
The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addressing), or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
4.8.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 4-7.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section
41.2.1 “Extended Instruction Syntax”.
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FIGURE 4-7: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations 3F60h to 3FFFh
(Bank 63) of data memory.
Locations below 60h are not
available in this Addressing
mode.
When ‘a’ = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 63 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
0000h
0060h
0100h
3F00h
3F60h
3FFFh
Valid range
00h
60h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 62
Bank 63
SFRs
0000h
0060h
0100h
3F00h
3F60h
3FFFh
Data Memory
Bank 0
Bank 1
through
Bank 62
Bank 63
SFRs
FSR2H FSR2L
ffffffff001001da
ffffffff001001da
0000h
0060h
0100h
3F00h
3F60h
3FFFh
Data Memory
Bank 0
Bank 1
through
Bank 62
Bank 63
SFRs
for ‘f’
BSR
00000000
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4.8.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom section of Bank 0, this
mode maps the contents from a user defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 4.5.4 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 4-8.
Remapping of the Access Bank applies only to
operations using the Indexed Literal Offset mode.
Operations that use the BSR (Access RAM bit is ‘1’) will
continue to use direct addressing as before.
4.9 PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 41.2 “Extended Instruction Set”.
FIGURE 4-8: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Data Memory
0000h
0100h
0200h
3F60h
3F00h
3FFFh
Bank 1
Bank 63
Bank 2
through
Bank 62
SFRs
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(0120h) to the pointer plus
05Fh (017Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Special File Registers at
3F60h through 3FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR. Access Bank
00h
60h
FFh
SFRs
Bank 1 “Window”
Bank 0
Window
Example Situation:
0120h
017Fh
5Fh
Bank 1
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5.0 DEVICE CONFIGURATION
Device configuration consists of the Configuration
Words, User ID, Device ID, Rev ID, Device Information
Area (DIA), (see Section 5.7 “Device Information
Area”), and the Device Configuration Information
(DCI) regions, (see Section 5.8 “Device Configura-
tion Information”).
5.1 Configuration Words
There are six Configuration Word bits that allow the
user to setup the device with several choices of
oscillators, Resets and memory protection options.
These are implemented as Configuration Word 1
through Configuration Word 6 at 300000h through
30000Bh.
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5.2 Register Definitions: Configuration Words
REGISTER 5-1: CONFIGURATION WORD 1L (30 0000h)
U-1 R/W-1 R/W-1 R/W-1 U-1 R/W-1 R/W-1 R/W-1
RSTOSC[2:0] — FEXTOSC[2:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘1
bit 6-4 RSTOSC[2:0]: Power-up Default Value for COSC bits
111 = EXTOSC operating per FEXTOSC[2:0] bits
110 = HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1
101 = LFINTOSC
100 = SOSC
011 = Reserved
010 = EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC[2:0] bits
001 = Reserved
000 = HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1; resets COSC/NOSC to 3’b110
bit 3 Unimplemented: Read as ‘1
bit 2-0 FEXTOSC[2:0]: FEXTOSC External Oscillator Mode Selection bits
111 = ECH (External Clock High Power)(1)
110 = ECM (External Clock Medium Power)(1)
101 = ECL (External Clock Low Power)(1)
100 = Oscillator is not enabled
011 = Reserved (do not use)
010 = HS (crystal oscillator) above 8 MHz
001 = XT (crystal oscillator) above 500 kHz, below 8 MHz
000 = LP (crystal oscillator) optimized for 32.768 kHz
Note 1: Refer to Table 44-8 for External Clock/Oscillator Timing Requirements.
If FEXTOSC 2 0 : EC mgh rmd or \ow or Nol Enabled. Otherwise.
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REGISTER 5-2: CONFIGURATION WORD 1H (30 0001h)
U-1 U-1 R/W-1 U-1 R/W-1 U-1 R/W-1 R/W-1
—FCMEN—CSWEN —PR1WAYCLKOUTEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘1
bit 5 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = FSCM timer is enabled
0 = FSCM timer is disabled
bit 4 Unimplemented: Read as ‘1
bit 3 CSWEN: Clock Switch Enable bit
1 = Writing to NOSC and NDIV is allowed
0 = The NOSC and NDIV bits cannot be changed by user software
bit 2 Unimplemented: Read as ‘1
bit 1 PR1WAY: PRLOCKED One-Way Set Enable bit
1 = PRLOCKED bit can be cleared and set only once; Priority registers remain locked after one
clear/set cycle
0 = PRLOCKED bit can be set and cleared multiple times (subject to the unlock sequence)
bit 0 CLKOUTEN: Clock Out Enable bit
If FEXTOSC[2:0] = EC (high, mid or low) or Not Enabled:
1 = CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = CLKOUT function is enabled; FOSC/4 clock appears at OSC2
Otherwise:
This bit is ignored.
If LVP : ,. If LVP : 2.
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REGISTER 5-3: CONFIGURATION WORD 2L (30 0002h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
BOREN[1:0] LPBOREN IVT1WAY MVECEN PWRTS[1:0] MCLRE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 BOREN[1:0]: Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit.
11 = Brown-out Reset is enabled, SBOREN bit is ignored
10 = Brown-out Reset is enabled while running, disabled in Sleep; SBOREN is ignored
01 = Brown-out Reset is enabled according to SBOREN
00 = Brown-out Reset is disabled
bit 5 LPBOREN: Low-Power BOR Enable bit
1 = Low-Power BOR is disabled
0 = Low-Power BOR is enabled
bit 4 IVT1WAY: IVTLOCK bit One-Way Set Enable bit
1 =
IVTLOCKED bit can be cleared and set only once; IVT registers remain locked after one clear/set
cycle
0 =
IVTLOCK ED bit can be set and cleared multiple times (subject to the unlock sequence)
bit 3 MVECEN: Multi-vector Enable bit
1 = Multi-vector enabled; Vector table used for interrupts
0 = Legacy interrupt behavior
bit 2-1 PWRTS[1:0]: Power-up Timer Selection bits
11 = PWRT is disabled
10 = PWRT set at 64 ms (2048 LFINTOSC Cycles)
01 = PWRT set at 16 ms (512 LFINTOSC Cycles)
00 = PWRT set at 1 ms (32 LFINTOSC Cycles)
bit 0 MCLRE: Master Clear (MCLR) Enable bit
If LVP = 1:
RE3 pin function is MCLR
If LVP = 0:
1 =MCLR pin is MCLR
0 =MCLR pin function is a port defined function
PICW BFXXK42 Devxces. PICW 8LFXXK42 Devwce.
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REGISTER 5-4: CONFIGURATION WORD 2H (30 0003h)
R/W-1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
XINST —DEBUGSTVREN PPS1WAY ZCD BORV[1:0](1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 XINST: Extended Instruction Set Enable bit
1 = Extended instruction set and Indexed Addressing mode are disabled (Legacy mode)
0 = Extended instruction set and Indexed Addressing mode are enabled
bit 6 Unimplemented: Read as ‘1
bit 5 DEBUG: Debugger Enable bit
1 = Background debugger is disabled
0 = Background debugger is enabled
bit 4 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 3 PPS1WAY: PPSLOCKED One-Way Set Enable bit
1 = PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set
cycle
0 = PPSLOCKED bit can be set and cleared multiple times (subject to the unlock sequence)
bit 2 ZCD: Zero-Cross Detect Enable bit
1 = ZCD is disabled; ZCD can be enabled by setting the bit SEN of the ZCDCON register
0 = ZCD is always enabled
bit 1-0 BORV[1:0]: Brown-out Reset Voltage Selection bits(1)
PIC18FXXK42 Devices:
11 = Brown-out Reset Voltage (VBOR) is set to 2.45V
10 = Brown-out Reset Voltage (VBOR) is set to 2.45V
01 = Brown-out Reset Voltage (VBOR) is set to 2.7V
00 = Brown-out Reset Voltage (VBOR) is set to 2.85V
PIC18LFXXK42 Device:
11 = Brown-out Reset Voltage (VBOR) is set to 1.90V
10 = Brown-out Reset Voltage (VBOR) is set to 2.45V
01 = Brown-out Reset Voltage (VBOR) is set to 2.7V
00 = Brown-out Reset Voltage (VBOR) is set to 2.85V
Note 1: The higher voltage setting is recommended for operation at or above 16 MHz.
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REGISTER 5-5: CONFIGURATION WORD 3L (30 0004h)
U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— WDTE[1:0] WDTCPS[4:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘1
bit 6-5 WDTE[1:0]: WDT Operating Mode bits
00 = WDT is disabled, SWDTEN is ignored
01 = WDT is enabled/disabled by the SWDTEN bit in WDTCON0
10 = WDT is enabled while Sleep = 0, suspended when Sleep = 1; SWDTEN is ignored
11 = WDT is enabled regardless of Sleep; SWDTEN is ignored
bit 4-0 WDTCPS[4:0]: WDT Period Select bits
WDTCPS[4:0]
WDTPS at POR
Software Control
of WDTPS?
Value Divider Ratio Typical Time-out
(FIN =31kHz)
00000 00000 1:32 251ms
No
00001 00001 1:64 262ms
00010 00010 1:128 274ms
00011 00011 1:256 288ms
00100 00100 1:512 2916 ms
00101 00101 1:1024 210 32 ms
00110 00110 1:2048 211 64 ms
00111 00111 1:4096 212 128 ms
01000 01000 1:8192 213 256 ms
01001 01001 1:16384 214 512 ms
01010 01010 1:32768 215 1s
01011 01011 1:65536 216 2s
01100 01100 1:131072 217 4s
01101 01101 1:262144 218 8s
01110 01110 1:524299 219 16s
01111 01111 1:1048576 220 32s
10000 10000 1:2097152 221 64s
10001 10001 1:4194304 222 128s
10010 10010 1:8388608 223 256s
10011
...
11110
10011
...
11110
1:32 251ms No
11111 01011 1:65536 216 2s Yes
IfWDTE[1.0] Fuses : mm. Otherwise.
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REGISTER 5-6: CONFIGURATION WORD 3H (30 0005h)
U-1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— WDTCCS[2:0] WDTCWS[2:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘1
bit 5-3 WDTCCS[2:0]: WDT Input Clock Selector bits
If WDTE[1:0] Fuses = 2’b00:
These bits are ignored.
Otherwise:
000 = WDT reference clock is the 31.0 kHz LFINTOSC
001 = WDT reference clock is the 31.25 kHz MFINTOSC
010 = WDT reference clock is SOSC
011 = Reserved (default to LFINTOSC)
110 = Reserved (default to LFINTOSC)
111 = Software control
bit 2-0 WDTCWS[2:0]: WDT Window Select bits
WDTCWS[2:0]
Window at POR Software
Control of
Window
Keyed
Access
Required?
Value Window Delay
Percent of Time
Window Opening
Percent of Time
000 000 87.5 12.5
No Yes
001 001 75 25
010 010 62.5 37.5
011 011 50 50
100 100 37.5 62.5
101 101 25 75
110 111 n/a 100
111 111 n/a 100 Yes No
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REGISTER 5-7: CONFIGURATION WORD 4L (30 0006h)
R/W-1 U-1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WRTAPP (1) SAFEN (1) BBEN (1) BBSIZE[2:0] (2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WRTAPP: Application Block Write Protection bit(1)
1 = Application Block is NOT write-protected
0 = Application Block is write-protected
bit 6-5 Unimplemented: Read as ‘1
bit 4 SAFEN: Storage Area Flash Enable bit(1)
1 = SAF is disabled
0 = SAF is enabled
bit 3 BBEN: Boot Block Enable bit(1)
1 = Boot Block disabled
0 = Boot Block enabled
bit 2-0 BBSIZE[2:0]: Boot Block Size Selection bits(2)
Refer to Tab l e 5- 1 .
Note 1: Bits are implemented as sticky bits. Once protection is enabled through ICSP™ or a self-write, it can only be
reset through a Bulk Erase.
2: BBSIZE[2:0] bits can only be changed when BBEN =1. Once BBEN =0, BBSIZE[2:0] can only be changed
through a Bulk Erase.
TABLE 5-1: BOOT BLOCK SIZE BITS
BBEN BBSIZE[2:0] Boot Block Size
(words) END_ADDRESS_BOOT
Device Size(1)
16k 32k 64k
1 xxx 0—XXX
0 111 512 00 03FFh X X X
0 110 1024 00 07FFh X X X
0 101 2048 00 0FFFh X X X
0 100 4096 00 1FFFh X X X
0 011 8192 00 3FFFh X X X
0 010 16384 00 7FFFh —XX
0 001 32768 00 FFFFh Note 2 X
0 000 32768 00 FFFFh — —
Note 1: For each device, the quoted device size specification is listed in Tabl e 4- 1 .
2: The maximum boot block size is half the user program memory size. All selections higher than the maximum size default
to maximum boot block size of half PFM. For example, all settings of BBSIZE = 000 through BBSIZE = 011, default to a
boot block size of 8 kW on a 16 kW device.
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REGISTER 5-8: CONFIGURATION WORD 4H (30 0007h)
U-1 U-1 R/W-1 U-1 R/W-1 R/W-1 R/W-1 R/W-1
—LVP
(2) — WRTSAF (1,3) WRTD (1,4) WRTC (1) WRTB(1,5)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘1
bit 5 LVP: Low-Voltage Programming Enable bit(2)
1 = Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE (Register 5-3) is
ignored.
0 = HV on MCLR/VPP must be used for programming.
bit 4 Unimplemented: Read as ‘1
bit 3 WRTSAF: Storage Area Flash (SAF) Write Protection bit(1,3)
1 = SAF is NOT write-protected
0 = SAF is write-protected
bit 2 WRTD: Data EEPROM Write Protection bit(1,4)
1 = Data EEPROM NOT write-protected
0 = Data EEPROM write-protected
bit 1 WRTC: Configuration Register Write Protection bit(1)
1 = Configuration Register NOT write-protected
0 = Configuration Register write-protected
bit 0 WRTB: Boot Block Write Protection bit(1,5)
1 = Boot Block NOT write-protected
0 = Boot Block write-protected
Note 1: Bits are implemented as sticky bits. Once protection is enabled through ICSP or a self write, it can only be
reset through a Bulk Erase.
2: The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of
this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or acci-
dentally eliminating LVP mode from the configuration state.
3: Unimplemented if SAF is not present and only applicable if SAFEN =0.
4: Unimplemented if data EEPROM is not present.
5: Only applicable if BBEN =0.
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REGISTER 5-9: CONFIGURATION WORD 5L (30 0008h)
U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/W-1
— — —CP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘1
bit 0 CP: User Program Flash Memory and Data EEPROM Code Protection bit
1 = User Program Flash Memory and Data EEPROM code protection is disabled
0 = User Program Flash Memory and Data EEPROM code protection is enabled
REGISTER 5-10: CONFIGURATION WORD 5H (30 0009h)
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Value for blank device ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 Unimplemented: Read as ‘1
TABLE 5-2: SUMMARY OF CONFIGURATION WORDS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
30 0000h CONFIG1L —RSTOSC[2:0] FEXTOSC[2:0] 1111 1111
30 0001h CONFIG1H —FCMEN— CSWEN —PR1WAYCLKOUTEN1111 1111
30 0002h CONFIG2L BOREN[1:0] LPBOREN IVT1WAY MVECEN PWRTS[1:0] MCLRE 1111 1111
30 0003h CONFIG2H XINST DEBUGSTVREN PPS1WAY ZCD BORV[1:0] 1111 1111
30 0004h CONFIG3L — WDTE[1:0] WDTCPS[4:0] 1111 1111
30 0005h CONFIG3H — WDTCCS[2:0] WDTCWS[2:0] 1111 1111
30 0006h CONFIG4L WRTAPP SAFEN BBEN BBSIZE[2:0] 1111 1111
30 0007h CONFIG4H —LVP WRTSAF WRTD WRTC WRTB 1111 1111
30 0008h CONFIG5L — — CP1111 1111
30 0009h CONFIG5H — — 1111 1111
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5.3 Code Protection
Code protection allows the device to be protected from
external access. Program memory protection and data
memory are controlled through the CP Configuration
bit. Internal access to the program memory is
unaffected by code protection setting.
The entire program memory space and Data
EEPROM is protected from external reads and writes
by the CP bit in Configuration Words. When CP = 0,
external reads and writes of memory are inhibited and
a read will return all ‘0’s. The CPU can continue to
read program memory and data EEPROM, regardless
of the protection bit settings. Self-writing the program
memory or Data EEPROM is dependent upon the
write protection settings.
5.4 User ID
Eight words in the memory space (200000h-20000Fh)
are designated as ID locations where the user can
store checksum or other code identification numbers.
These locations are readable and writable during
normal execution. See Section 13.2 “Device
Information Area, Device Configuration Area, User
ID, Device ID and Configuration Word Access” for
more information on accessing these memory
locations. For more information on checksum
calculation, see the “PIC18(L)F26/27/45/46/47/55/56/
57K42 Memory Programming Specification
(DS40001886).
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5.5 Device ID and Revision ID
The 16-bit device ID word is located at 3F FFFEh and
the 16-bit revision ID is located at 3F FFFCh. These
locations are read-only and cannot be erased or
modified.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID,
Revision ID and Configuration Words. Refer to 13.0
“Nonvolatile Memory (NVM) Control” for more
information on accessing these locations.
5.6 Register Definitions: Device ID and Revision ID
REGISTER 5-11: DEVICE ID: DEVICE ID REGISTER
RRRRRRRR
DEV[15:8]
bit 15 bit 8
RRRRRRRR
DEV[7:0]
bit 7 bit 0
Legend:
R = Readable bit ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 15-0 DEV[15:0]: Device ID bits
Device Device ID
PIC18F26K42 6C60h
PIC18F27K42 6C40h
PIC18F45K42 6C20h
PIC18F46K42 6C00h
PIC18F47K42 6BE0h
PIC18F55K42 6BC0h
PIC18F56K42 6BA0h
PIC18F57K42 6B80h
PIC18LF26K42 6DA0h
PIC18LF27K42 6D80h
PIC18LF45K42 6D60h
PIC18LF46K42 6D40h
PIC18LF47K42 6D20h
PIC18LF55K42 6D00h
PIC18LF56K42 6CE0h
PIC18LF57K42 6CC0h
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REGISTER 5-12: REVISION ID: REVISION ID REGISTER
RRRRRRRR
1010 MJRREV[5:2]
bit 15 bit 8
RRRRRRRR
MJRREV[1:0] MNRREV[5:0]
bit 7 bit 0
Legend:
R = Readable bit ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 15-12 Read as ‘1010
These bits are fixed with value ‘1010’ for all devices in this family.
bit 11-6 MJRREV[5:0]: Major Revision ID bits
These bits are used to identify a major revision. A major revision is indicated by revision (A0, B0, C0,
etc.)
Revision A = 0b00 0000
bit 5-0 MNRREV[5:0]: Minor Revision ID bits
These bits are used to identify a minor revision.
Revision A0 = 0b00 0000
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5.7 Device Information Area
The Device Information Area (DIA) is a dedicated
region in the Program memory space. The DIA
contains the calibration data for the internal
temperature indicato