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2N7002K Datasheet

Vishay Siliconix

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Datasheet

2N7002K
www.vishay.com Vishay Siliconix
S17-1299-Rev. F, 21-Aug-17 1Document Number: 71333
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
N-Channel 60 V (D-S) MOSFET
Marking code: 7K
FEATURES
Low on-resistance: 2
Low threshold: 2 V (typ.)
Low input capacitance: 25 pF
Fast switching speed: 25 ns
Low input and output leakage
• TrenchFET® power MOSFET
2000 V ESD protection
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
BENEFITS
Low offset voltage
Low voltage operation
Easily driven without buffer
High speed circuits
Low error voltage
APPLICATIONS
Direct logic-level interface: TTL/CMOS
• Drivers:
relays, solenoids, lamps, hammers,
display, memories, transistors, etc.
Battery operated systems
Solid state relays
Notes
a. Pulse width limited by maximum junction temperature
b. Surface mounted on FR4 board
PRODUCT SUMMARY
VDS (V) 60
RDS(on) max. () at VGS = 10 V 2
Qg typ. (nC) 0.4
ID (A) 0.3
Configuration Single
Top View
SOT-23 (TO-236)
1
G
2
S
D
3
Available
Available
Available
N-Channel MOSFET
S
D
G
ORDERING INFORMATION
Package SOT-23
Lead (Pb)-free 2N7002K-T1-E3
Lead (Pb)-free and halogen-free 2N7002K-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 60 V
Gate-source voltage VGS ± 20
Continuous drain current (TJ = 150 °C) bTA = 25 °C ID
0.3
ATA = 100 °C 0.19
Pulsed drain current aIDM 0.8
Power dissipation bTA = 25 °C PD
0.35 W
TA = 100 °C 0.14
Maximum junction-to-ambient bRthJA 350 °C/W
Operating junction and storage temperature range TJ, Tstg -55 to +150 °C
2N7002K
www.vishay.com Vishay Siliconix
S17-1299-Rev. F, 21-Aug-17 2Document Number: 71333
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. For DESIGN AID ONLY, not subject to production testing
b. Pulse test: pulse width 300 μs duty cycle 2 %
c. Switching time is essentially independent of operating temperature
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP.
aMAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 10 μA 60 - - V
Gate-threshold voltage VGS(th) VDS = VGS, ID = 250 μA 1 - 2.5
Gate-body leakage IGSS
VDS = 0 V, VGS = ± 20 V - - ± 10 μA
VDS = 0 V, VGS = ± 15 V - - 1
VDS = 0 V, VGS = ± 10 V - - ± 150
nAVDS = 0 V, VGS = ± 10 V, TJ = 85 °C - - ± 1000
VDS = 0 V, VGS = ± 5 V - - ± 100
Zero gate voltage drain current IDSS
VDS = 60 V, VGS = 0 V - - 1 μA
VDS = 60 V, VGS = 0 V, TJ = 125 °C - - 500
On-state drain current bID(on)
VGS = 10 V, VDS = 7.5 V 800 - - mA
VGS = 4.5 V, VDS = 10 V 500 - -
Drain-source on-resistance bRDS(on)
VGS = 10 V, ID = 500 mA - - 2
VGS = 4.5 V, ID = 200 mA - - 4
Forward transconductance bgfs VDS = 10 V, ID = 200 mA 100 - - mS
Diode forward voltage VSD IS = 200 mA, VGS = 0 V - - 1.3 V
Dynamic a, b
Total gate charge QgVDS = 10 V, VGS = 4.5 V
ID 250 mA -0.40.6nC
Input capacitance Ciss VDS = 25 V, VGS = 0 V
f = 1 MHz
-30-
pFOutput capacitance Coss -6-
Reverse transfer capacitance Crss -2.5-
Switching a, c
Turn-on time td(on) VDD = 30 V, RL = 150
ID 200 mA, VGEN = 10 V, Rg = 10
--25
ns
Turn-off time td(off) --35
2N7002K
www.vishay.com Vishay Siliconix
S17-1299-Rev. F, 21-Aug-17 3Document Number: 71333
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0.0
0.2
0.4
0.6
0.8
1.0
012 34 5
V
DS
- Drain-to-Source Voltage (V)
- Drain Current (A)I
D
V
GS
= 10 V
3 V
5 V
4 V
6 V
7 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4
.
0
0 200 400 600 800 1000
I
D - Drain Current (mA)
V
GS
= 4.5 V
V
GS
= 10 V
- On-Resistance ()RDS(on)
0
1
2
3
4
5
6
7
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VDS = 10 V
ID = 250 mA
- Gate-to-Source Voltage (V)
Qg - Total Gate Charge (nC)
VGS
0
300
600
900
1200
0123456
VGS
- Gate-to-Source Voltage (V)
- Drain Current (mA)ID
T
J
= - 55 °C
125 °C
25 °C
0
8
16
24
32
40
0 5 10 15 20 25
VDS
- Drain-to-Source Voltage (V)
C - Capacitance (pF)
Crss
Coss
Ciss
VGS = 0 V
0.0
0.4
0.8
1.2
1.6
2
.
0
- 50 - 25 0 25 50 75 100 125 150
TJ
- Junction Temperature (°C)
V
GS
= 10 V at 500 mA
V
GS
= 4.5 V
at 200 mA
(Normalized)- On-ResistanceR
DS(on)
2N7002K
www.vishay.com Vishay Siliconix
S17-1299-Rev. F, 21-Aug-17 4Document Number: 71333
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage Variance Over Temperature
On-Resistance vs. Gate-Source Voltage
Single Pulse Power, Junction-to-Ambient
1.2 1.5
1
100
1000
0.0 0.3 0.6 0.9
T
J
= 125 °C
V
SD
- Source-to-Drain Voltage (V)
- Source Current (A)I
S
10
T
J
= - 55 °C
V
GS
= 0 V
T
J
= 25 °C
Variance (V)VGS(th)
- 0.8
- 0.6
- 0.4
- 0.2
0.0
0.2
0.4
- 50 - 25 0 2 5 5 0 7 5 100 125 150
I
D
= 250 µA
TJ - Junction Temperature (°C)
0
1
2
3
4
5
0246810
VGS
- Gate-to-Source Voltage (V)
I
D
= 500 mA
I
D
= 200 mA
- On-Resistance ()R
DS(on)
0.01
0
1
2.5
100 600 0.1
Power (W)
Time (s)
1.5
2
0.5
1
10
T
A
= 25 °C
2N7002K
www.vishay.com Vishay Siliconix
S17-1299-Rev. F, 21-Aug-17 5Document Number: 71333
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71333.
10 10
-3
10
-2
1 1 0 600 10
-1 -4
100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = R
th JA
= 350 °C/W
3. T JM
- T
A = PDMZthJA(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
10
-3
10
-2
1 10 10
-1
10
-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
Vishay Siliconix
Package Information
Document Number: 71196
09-Jul-01
www.vishay.com
1
SOT-23 (TO-236): 3-LEAD
b
E
E1
1
3
2
Se
e1
D
A2
A
A1C
Seating Plane
0.10 mm
0.004"
CC
L1
L
q
Gauge Plane
Seating Plane
0.25 mm
Dim MILLIMETERS INCHES
Min Max Min Max
A0.89 1.12 0.035 0.044
A10.01 0.10 0.0004 0.004
A20.88 1.02 0.0346 0.040
b0.35 0.50 0.014 0.020
c0.085 0.18 0.0030.007
D2.80 3.04 0.110 0.120
E2.10 2.64 0.0830.104
E11.20 1.40 0.047 0.055
e0.95 BSC 0.0374 Ref
e11.90 BSC 0.0748 Ref
L0.40 0.60 0.016 0.024
L10.64 Ref 0.025 Ref
S0.50 Ref 0.020 Ref
q3°8°3°8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
AN807
Vishay Siliconix
Document Number: 70739
26-Nov-03
www.vishay.com
1
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
ambient air. This pattern uses all the available area underneath the
body for this purpose.
FIGURE 1. Footprint With Copper Spreading
0.114
2.9
0.059
1.5
0.0394
1.0
0.037
0.95
0.150
3.8
0.081
2.05
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
Application Note 826
Vishay Siliconix
Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SOT-23
0.106
(2.692)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.022
(0.559)
0.049
(1.245)
0.029
(0.724)
0.037
(0.950)
0.053
(1.341)
0.097
(2.459)
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www.vishay.com Vishay
Revision: 01-Jan-2019 1Document Number: 91000
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.
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