The Qorivva MPC564xA microcontroller delivers the performance and precision needed for next-generation transmission control and engine management needs. Designed with the e200z4 dual-issue core built on Power Architecture® technology, the Qorivva MPC564xA can process two instructions per clock cycle, enabling it to run more instructions per cycle and with higher performance than single-issue cores at the same MHz. Consequently, when running at the same performance level as a single-core device, it uses less power.
The Qorivva MPC564xA supports up to 300 DMIPS performance while maintaining the low power required for high-temperature applications, such as transmissions.
The Qorivva MPC564xA’s key features include a z4 core up to 150 MHz DSP capability, up to 4 MB of flash memory, 8 KB instruction cache, up to 192 KB SRAM, 32-channel eTPU2, optional FlexRay™ and on-board knock detection. This unique set of features makes the Qorivva MPC564xA ideal for lowering overall system cost, optimizing fuel economy, reducing emissions and improving shift control.
The e200z4 core host processor is 100 percent user-mode compatible with the classic Power Architecture instruction set. The Qorivva MPC564xA also offers pin, peripheral and tool compatibility with the 32-bit Qorivva MPC563xM devices to support design flexibility across architectures. Three package options allow developers to design applications that require different amounts of I/O.
View Qorivva MPC564xA full Fact sheet here.